Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 1 | if ARCH_DAVINCI |
| 2 | |
| 3 | choice |
| 4 | prompt "DaVinci board select" |
Joe Hershberger | f069960 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 5 | optional |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 6 | |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 7 | config TARGET_DA850EVM |
| 8 | bool "DA850 EVM board" |
Adam Ford | d1f15a1 | 2018-01-11 08:20:27 -0600 | [diff] [blame] | 9 | select MACH_DAVINCI_DA850_EVM |
| 10 | select SOC_DA850 |
Masahiro Yamada | 6e0971b | 2014-10-20 17:45:56 +0900 | [diff] [blame] | 11 | select SUPPORT_SPL |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 12 | |
Simon Glass | a6664e9 | 2015-08-30 19:18:59 -0600 | [diff] [blame] | 13 | config TARGET_OMAPL138_LCDK |
| 14 | bool "OMAPL138 LCDK" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 15 | select SOC_DA8XX |
Simon Glass | a6664e9 | 2015-08-30 19:18:59 -0600 | [diff] [blame] | 16 | select SUPPORT_SPL |
Bartosz Golaszewski | f1412ef | 2019-11-14 16:10:30 +0100 | [diff] [blame] | 17 | select SPL_BOARD_INIT |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 18 | |
David Lechner | a67f16f | 2016-02-26 00:46:07 -0600 | [diff] [blame] | 19 | config TARGET_LEGOEV3 |
| 20 | bool "LEGO MINDSTORMS EV3" |
Adam Ford | d1f15a1 | 2018-01-11 08:20:27 -0600 | [diff] [blame] | 21 | select MACH_DAVINCI_DA850_EVM |
| 22 | select SOC_DA850 |
David Lechner | a67f16f | 2016-02-26 00:46:07 -0600 | [diff] [blame] | 23 | |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 24 | endchoice |
| 25 | |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 26 | config SYS_SOC |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 27 | default "davinci" |
| 28 | |
Adam Ford | d1f15a1 | 2018-01-11 08:20:27 -0600 | [diff] [blame] | 29 | config DA850_LOWLEVEL |
| 30 | bool "Enable Lowlevel DA850 initialization" |
| 31 | depends on SOC_DA850 |
| 32 | |
Fabien Parent | b1bd48b | 2016-11-29 14:23:36 +0100 | [diff] [blame] | 33 | config SYS_DA850_PLL_INIT |
| 34 | bool |
| 35 | |
Fabien Parent | 06372b6 | 2016-11-29 14:23:37 +0100 | [diff] [blame] | 36 | config SYS_DA850_DDR_INIT |
| 37 | bool |
| 38 | |
Adam Ford | d1f15a1 | 2018-01-11 08:20:27 -0600 | [diff] [blame] | 39 | config SOC_DA850 |
| 40 | bool |
| 41 | select SOC_DA8XX |
Adam Ford | d1f15a1 | 2018-01-11 08:20:27 -0600 | [diff] [blame] | 42 | |
| 43 | config SOC_DA8XX |
| 44 | bool |
Lokesh Vutla | bcb8d28 | 2018-03-16 14:22:12 +0530 | [diff] [blame] | 45 | select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL |
Michal Simek | 7e7ba3b | 2018-07-23 15:55:15 +0200 | [diff] [blame] | 46 | select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL |
Adam Ford | d1f15a1 | 2018-01-11 08:20:27 -0600 | [diff] [blame] | 47 | |
| 48 | config MACH_DAVINCI_DA850_EVM |
| 49 | bool |
| 50 | |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 51 | if SYS_DA850_PLL_INIT |
| 52 | comment "DA850 PLL Initialization Parameters" |
| 53 | |
| 54 | config SYS_DV_CLKMODE |
| 55 | int "PLLCTL Clock Mode" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 56 | default 0 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 57 | help |
| 58 | Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator |
| 59 | |
| 60 | config SYS_DA850_PLL0_POSTDIV |
| 61 | int "PLLC0 PLL Post-Divider" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 62 | default 1 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 63 | help |
| 64 | Value written to PLLC0 PLL Post-Divider Control Register |
| 65 | |
| 66 | config SYS_DA850_PLL0_PLLDIV1 |
| 67 | hex "PLLC0 Divider 1" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 68 | default 0x8000 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 69 | help |
| 70 | Value written to PLLC0 Divider 1 register |
| 71 | |
| 72 | config SYS_DA850_PLL0_PLLDIV2 |
| 73 | hex "PLLC0 Divider 2" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 74 | default 0x8001 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 75 | help |
| 76 | Value written to PLLC0 Divider 2 register |
| 77 | |
| 78 | config SYS_DA850_PLL0_PLLDIV3 |
| 79 | hex "PLLC0 Divider 3" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 80 | default 0x8002 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 81 | help |
| 82 | Value written to PLLC0 Divider 3 register |
| 83 | |
| 84 | config SYS_DA850_PLL0_PLLDIV4 |
| 85 | hex "PLLC0 Divider 4" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 86 | default 0x8003 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 87 | help |
| 88 | Value written to PLLC0 Divider 4 register |
| 89 | |
| 90 | config SYS_DA850_PLL0_PLLDIV5 |
| 91 | hex "PLLC0 Divider 5" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 92 | default 0x8002 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 93 | help |
| 94 | Value written to PLLC0 Divider 5 register |
| 95 | |
| 96 | config SYS_DA850_PLL0_PLLDIV6 |
| 97 | hex "PLLC0 Divider 6" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 98 | default 0x8000 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 99 | help |
| 100 | Value written to PLLC0 Divider 6 register |
| 101 | |
| 102 | config SYS_DA850_PLL0_PLLDIV7 |
| 103 | hex "PLLC0 Divider 7" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 104 | default 0x8005 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 105 | help |
| 106 | Value written to PLLC0 Divider 7 register |
| 107 | |
| 108 | config SYS_DA850_PLL1_POSTDIV |
| 109 | hex "PLLC1 PLL Post-Divider" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 110 | default 1 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 111 | help |
| 112 | Value written to PLLC1 PLL Post-Divider Control Register |
| 113 | |
| 114 | config SYS_DA850_PLL1_PLLDIV1 |
| 115 | hex "PLLC1 Divider 2" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 116 | default 0x8000 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 117 | help |
| 118 | Value written to PLLC1 Divider 1 register |
| 119 | |
| 120 | config SYS_DA850_PLL1_PLLDIV2 |
| 121 | hex "PLLC1 Divider 2" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 122 | default 0x8001 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 123 | help |
| 124 | Value written to PLLC1 Divider 2 register |
| 125 | |
| 126 | config SYS_DA850_PLL1_PLLDIV3 |
| 127 | hex "PLLC1 Divider 3" |
Tom Rini | d97ca59 | 2018-01-31 15:34:49 -0500 | [diff] [blame] | 128 | default 0x8002 |
Adam Ford | 71750ee | 2018-01-23 04:04:28 -0600 | [diff] [blame] | 129 | help |
| 130 | Value written to PLLC1 Divider 3 register |
| 131 | |
| 132 | endif |
| 133 | |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 134 | source "board/davinci/da8xxevm/Kconfig" |
David Lechner | a67f16f | 2016-02-26 00:46:07 -0600 | [diff] [blame] | 135 | source "board/lego/ev3/Kconfig" |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 136 | |
Masahiro Yamada | e604ef9 | 2014-08-31 07:11:01 +0900 | [diff] [blame] | 137 | endif |