Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Atmel Corporation |
| 3 | * |
| 4 | * Configuation settings for the AT91SAM9X5EK board. |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_H__ |
| 10 | #define __CONFIG_H__ |
| 11 | |
| 12 | #include <asm/hardware.h> |
| 13 | |
Bo Shen | 337a2d8 | 2013-08-13 14:50:49 +0800 | [diff] [blame] | 14 | #define CONFIG_SYS_TEXT_BASE 0x26f00000 |
| 15 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 16 | /* ARM asynchronous clock */ |
| 17 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
| 18 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 19 | |
| 20 | #define CONFIG_AT91SAM9X5EK |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 21 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 22 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 23 | #define CONFIG_SETUP_MEMORY_TAGS |
| 24 | #define CONFIG_INITRD_TAG |
| 25 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 26 | #define CONFIG_BOARD_EARLY_INIT_F |
| 27 | #define CONFIG_DISPLAY_CPUINFO |
| 28 | |
Nicolas Ferre | e4f3623 | 2013-02-20 00:16:24 +0000 | [diff] [blame] | 29 | #define CONFIG_CMD_BOOTZ |
Bo Shen | 70390ab | 2012-09-04 23:22:55 +0000 | [diff] [blame] | 30 | #define CONFIG_OF_LIBFDT |
| 31 | |
Bo Shen | 7cbe18d | 2014-04-24 11:42:16 +0800 | [diff] [blame] | 32 | #define CONFIG_SYS_GENERIC_BOARD |
| 33 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 34 | /* general purpose I/O */ |
| 35 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ |
| 36 | #define CONFIG_AT91_GPIO |
| 37 | |
| 38 | /* serial console */ |
| 39 | #define CONFIG_ATMEL_USART |
| 40 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 41 | #define CONFIG_USART_ID ATMEL_ID_SYS |
| 42 | |
| 43 | /* LCD */ |
| 44 | #define CONFIG_LCD |
| 45 | #define LCD_BPP LCD_COLOR16 |
| 46 | #define LCD_OUTPUT_BPP 24 |
| 47 | #define CONFIG_LCD_LOGO |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 48 | #define CONFIG_LCD_INFO |
| 49 | #define CONFIG_LCD_INFO_BELOW_LOGO |
| 50 | #define CONFIG_SYS_WHITE_ON_BLACK |
| 51 | #define CONFIG_ATMEL_HLCD |
| 52 | #define CONFIG_ATMEL_LCD_RGB565 |
| 53 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 54 | |
| 55 | #define CONFIG_BOOTDELAY 3 |
| 56 | |
| 57 | /* |
| 58 | * BOOTP options |
| 59 | */ |
| 60 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 61 | #define CONFIG_BOOTP_BOOTPATH |
| 62 | #define CONFIG_BOOTP_GATEWAY |
| 63 | #define CONFIG_BOOTP_HOSTNAME |
| 64 | |
Bo Shen | 963a2b1 | 2013-12-10 16:14:02 +0800 | [diff] [blame] | 65 | /* no NOR flash */ |
| 66 | #define CONFIG_SYS_NO_FLASH |
| 67 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 68 | /* |
| 69 | * Command line configuration. |
| 70 | */ |
| 71 | #include <config_cmd_default.h> |
| 72 | #undef CONFIG_CMD_FPGA |
| 73 | #undef CONFIG_CMD_IMI |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 74 | |
| 75 | #define CONFIG_CMD_PING |
| 76 | #define CONFIG_CMD_DHCP |
| 77 | #define CONFIG_CMD_NAND |
Bo Shen | 4a73e58 | 2012-08-19 20:32:24 +0000 | [diff] [blame] | 78 | #define CONFIG_CMD_SF |
Wu, Josh | e32c661 | 2012-09-13 22:22:05 +0000 | [diff] [blame] | 79 | #define CONFIG_CMD_MMC |
Richard Genoud | fa2dbe7 | 2012-11-29 23:18:33 +0000 | [diff] [blame] | 80 | #define CONFIG_CMD_FAT |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 81 | #define CONFIG_CMD_USB |
| 82 | |
| 83 | /* |
| 84 | * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0) |
| 85 | * NB: in this case, USB 1.1 devices won't be recognized. |
| 86 | */ |
| 87 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 88 | |
| 89 | /* SDRAM */ |
| 90 | #define CONFIG_NR_DRAM_BANKS 1 |
| 91 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 92 | #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ |
| 93 | |
| 94 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 95 | (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) |
| 96 | |
| 97 | /* DataFlash */ |
Bo Shen | 4a73e58 | 2012-08-19 20:32:24 +0000 | [diff] [blame] | 98 | #ifdef CONFIG_CMD_SF |
| 99 | #define CONFIG_ATMEL_SPI |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 100 | #define CONFIG_SPI_FLASH |
| 101 | #define CONFIG_SPI_FLASH_ATMEL |
Bo Shen | 4a73e58 | 2012-08-19 20:32:24 +0000 | [diff] [blame] | 102 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 103 | #endif |
| 104 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 105 | /* NAND flash */ |
| 106 | #ifdef CONFIG_CMD_NAND |
| 107 | #define CONFIG_NAND_ATMEL |
| 108 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 109 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 110 | #define CONFIG_SYS_NAND_DBW_8 1 |
| 111 | /* our ALE is AD21 */ |
| 112 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 113 | /* our CLE is AD22 */ |
| 114 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 115 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 |
| 116 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 |
| 117 | |
Wu, Josh | dd359a1 | 2012-08-23 00:05:38 +0000 | [diff] [blame] | 118 | /* PMECC & PMERRLOC */ |
| 119 | #define CONFIG_ATMEL_NAND_HWECC 1 |
| 120 | #define CONFIG_ATMEL_NAND_HW_PMECC 1 |
| 121 | #define CONFIG_PMECC_CAP 2 |
| 122 | #define CONFIG_PMECC_SECTOR_SIZE 512 |
Wu, Josh | dd359a1 | 2012-08-23 00:05:38 +0000 | [diff] [blame] | 123 | |
Bo Shen | 591ef58 | 2013-06-26 10:48:53 +0800 | [diff] [blame] | 124 | #define CONFIG_CMD_NAND_TRIMFFS |
| 125 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 126 | #define CONFIG_MTD_DEVICE |
| 127 | #define CONFIG_CMD_MTDPARTS |
| 128 | #define CONFIG_MTD_PARTITIONS |
| 129 | #define CONFIG_RBTREE |
| 130 | #define CONFIG_LZO |
| 131 | #define CONFIG_CMD_UBI |
| 132 | #define CONFIG_CMD_UBIFS |
| 133 | #endif |
| 134 | |
Wu, Josh | e32c661 | 2012-09-13 22:22:05 +0000 | [diff] [blame] | 135 | /* MMC */ |
| 136 | #ifdef CONFIG_CMD_MMC |
| 137 | #define CONFIG_MMC |
Wu, Josh | e32c661 | 2012-09-13 22:22:05 +0000 | [diff] [blame] | 138 | #define CONFIG_GENERIC_MMC |
| 139 | #define CONFIG_GENERIC_ATMEL_MCI |
Richard Genoud | fa2dbe7 | 2012-11-29 23:18:33 +0000 | [diff] [blame] | 140 | #endif |
| 141 | |
| 142 | /* FAT */ |
| 143 | #ifdef CONFIG_CMD_FAT |
Wu, Josh | e32c661 | 2012-09-13 22:22:05 +0000 | [diff] [blame] | 144 | #define CONFIG_DOS_PARTITION |
| 145 | #endif |
| 146 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 147 | /* Ethernet */ |
| 148 | #define CONFIG_MACB |
| 149 | #define CONFIG_RMII |
| 150 | #define CONFIG_NET_RETRY_COUNT 20 |
| 151 | #define CONFIG_MACB_SEARCH_PHY |
| 152 | |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 153 | /* USB */ |
| 154 | #ifdef CONFIG_CMD_USB |
| 155 | #ifdef CONFIG_USB_EHCI |
| 156 | #define CONFIG_USB_EHCI_ATMEL |
| 157 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 |
| 158 | #else |
Bo Shen | 4a985df | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 159 | #define CONFIG_USB_ATMEL |
| 160 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 161 | #define CONFIG_USB_OHCI_NEW |
| 162 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 163 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI |
| 164 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" |
| 165 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 |
| 166 | #endif |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 167 | #define CONFIG_USB_STORAGE |
| 168 | #endif |
| 169 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 170 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 171 | |
| 172 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 173 | #define CONFIG_SYS_MEMTEST_END 0x26e00000 |
| 174 | |
| 175 | #ifdef CONFIG_SYS_USE_NANDFLASH |
| 176 | /* bootstrap + u-boot + env + linux in nandflash */ |
| 177 | #define CONFIG_ENV_IS_IN_NAND |
| 178 | #define CONFIG_ENV_OFFSET 0xc0000 |
| 179 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
| 180 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
| 181 | #define CONFIG_BOOTCOMMAND "nand read " \ |
| 182 | "0x22000000 0x200000 0x300000; " \ |
| 183 | "bootm 0x22000000" |
Wu, Josh | 9d68189 | 2012-11-02 00:17:27 +0000 | [diff] [blame] | 184 | #elif defined(CONFIG_SYS_USE_SPIFLASH) |
Bo Shen | 4a73e58 | 2012-08-19 20:32:24 +0000 | [diff] [blame] | 185 | /* bootstrap + u-boot + env + linux in spi flash */ |
| 186 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 187 | #define CONFIG_ENV_OFFSET 0x5000 |
| 188 | #define CONFIG_ENV_SIZE 0x3000 |
| 189 | #define CONFIG_ENV_SECT_SIZE 0x1000 |
| 190 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 |
| 191 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 192 | "sf read 0x22000000 0x100000 0x300000; " \ |
| 193 | "bootm 0x22000000" |
Bo Shen | 0a9f8ac | 2012-12-06 21:37:04 +0000 | [diff] [blame] | 194 | #elif defined(CONFIG_SYS_USE_DATAFLASH) |
| 195 | /* bootstrap + u-boot + env + linux in data flash */ |
| 196 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 197 | #define CONFIG_ENV_OFFSET 0x4200 |
| 198 | #define CONFIG_ENV_SIZE 0x4200 |
| 199 | #define CONFIG_ENV_SECT_SIZE 0x210 |
| 200 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 |
| 201 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 202 | "sf read 0x22000000 0x84000 0x294000; " \ |
| 203 | "bootm 0x22000000" |
Wu, Josh | 9d68189 | 2012-11-02 00:17:27 +0000 | [diff] [blame] | 204 | #else /* CONFIG_SYS_USE_MMC */ |
| 205 | /* bootstrap + u-boot + env + linux in mmc */ |
Wu, Josh | df0ef74 | 2015-01-20 10:33:33 +0800 | [diff] [blame] | 206 | #define CONFIG_ENV_IS_IN_FAT |
| 207 | #define CONFIG_FAT_WRITE |
| 208 | #define FAT_ENV_INTERFACE "mmc" |
| 209 | #define FAT_ENV_FILE "uboot.env" |
| 210 | #define FAT_ENV_DEVICE_AND_PART "0" |
| 211 | #define CONFIG_ENV_SIZE 0x4000 |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 212 | #endif |
| 213 | |
Wu, Josh | 9d68189 | 2012-11-02 00:17:27 +0000 | [diff] [blame] | 214 | #ifdef CONFIG_SYS_USE_MMC |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 215 | #define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \ |
| 216 | "mtdparts=atmel_nand:" \ |
| 217 | "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ |
Wu, Josh | 9d68189 | 2012-11-02 00:17:27 +0000 | [diff] [blame] | 218 | "root=/dev/mmcblk0p2 " \ |
| 219 | "rw rootfstype=ext4 rootwait" |
| 220 | #else |
Bo Shen | a8fd063 | 2013-02-20 00:16:25 +0000 | [diff] [blame] | 221 | #define CONFIG_BOOTARGS \ |
| 222 | "console=ttyS0,115200 earlyprintk " \ |
| 223 | "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ |
| 224 | "256k(env),256k(env_redundant),256k(spare)," \ |
| 225 | "512k(dtb),6M(kernel)ro,-(rootfs) " \ |
| 226 | "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw" |
Wu, Josh | 9d68189 | 2012-11-02 00:17:27 +0000 | [diff] [blame] | 227 | #endif |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 228 | |
| 229 | #define CONFIG_BAUDRATE 115200 |
| 230 | |
| 231 | #define CONFIG_SYS_PROMPT "U-Boot> " |
| 232 | #define CONFIG_SYS_CBSIZE 256 |
| 233 | #define CONFIG_SYS_MAXARGS 16 |
| 234 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \ |
| 235 | + 16) |
| 236 | #define CONFIG_SYS_LONGHELP |
| 237 | #define CONFIG_CMDLINE_EDITING |
| 238 | #define CONFIG_AUTO_COMPLETE |
| 239 | #define CONFIG_SYS_HUSH_PARSER |
| 240 | |
| 241 | /* |
| 242 | * Size of malloc() pool |
| 243 | */ |
| 244 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) |
| 245 | |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 246 | /* SPL */ |
| 247 | #define CONFIG_SPL_FRAMEWORK |
| 248 | #define CONFIG_SPL_TEXT_BASE 0x300000 |
| 249 | #define CONFIG_SPL_MAX_SIZE 0x6000 |
| 250 | #define CONFIG_SPL_STACK 0x308000 |
| 251 | |
| 252 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 253 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 254 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 255 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 256 | |
| 257 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 258 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
| 259 | #define CONFIG_SPL_GPIO_SUPPORT |
| 260 | #define CONFIG_SPL_SERIAL_SUPPORT |
| 261 | |
| 262 | #define CONFIG_SPL_BOARD_INIT |
| 263 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 264 | |
| 265 | #define CONFIG_SYS_MASTER_CLOCK 132096000 |
| 266 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 |
| 267 | #define CONFIG_SYS_MCKR 0x1301 |
| 268 | #define CONFIG_SYS_MCKR_CSS 0x1302 |
| 269 | |
| 270 | #define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC |
| 271 | |
| 272 | #ifdef CONFIG_SYS_USE_MMC |
| 273 | #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds |
| 274 | #define CONFIG_SPL_MMC_SUPPORT |
| 275 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 |
| 276 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 |
| 277 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
| 278 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
| 279 | #define CONFIG_SPL_FAT_SUPPORT |
| 280 | #define CONFIG_SPL_LIBDISK_SUPPORT |
| 281 | |
| 282 | #elif CONFIG_SYS_USE_NANDFLASH |
| 283 | #define CONFIG_SPL_NAND_SUPPORT |
| 284 | #define CONFIG_SPL_NAND_DRIVERS |
| 285 | #define CONFIG_SPL_NAND_BASE |
| 286 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 |
| 287 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 288 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 |
| 289 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 290 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 291 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 |
| 292 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 |
| 293 | #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER |
| 294 | |
| 295 | #elif CONFIG_SYS_USE_SPIFLASH |
| 296 | #define CONFIG_SPL_SPI_SUPPORT |
| 297 | #define CONFIG_SPL_SPI_FLASH_SUPPORT |
| 298 | #define CONFIG_SPL_SPI_LOAD |
| 299 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 |
| 300 | |
| 301 | #endif |
| 302 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 303 | #endif |