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wdenk8aeb24e2003-06-20 22:36:30 +00001/*
2 * (C) Copyright 2001
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
wdenkdccbda02003-07-14 22:13:32 +00005 * Modified during 2003 by
6 * Ken Chou, kchou@ieee.org
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk8aeb24e2003-06-20 22:36:30 +00009 */
10
11#include <common.h>
12#include <mpc824x.h>
13#include <pci.h>
Ben Warren8d943c82008-08-31 10:07:16 -070014#include <netdev.h>
wdenk8aeb24e2003-06-20 22:36:30 +000015
16int checkboard (void)
17{
18 ulong busfreq = get_bus_freq(0);
19 char buf[32];
20
21 printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
22 return 0;
23
24}
25
Becky Brucebd99ae72008-06-09 16:03:40 -050026phys_size_t initdram (int board_type)
wdenk8aeb24e2003-06-20 22:36:30 +000027{
wdenk87249ba2004-01-06 22:38:14 +000028 long size;
29 long new_bank0_end;
30 long mear1;
31 long emear1;
wdenk8aeb24e2003-06-20 22:36:30 +000032
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033 size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
wdenk8aeb24e2003-06-20 22:36:30 +000034
wdenk87249ba2004-01-06 22:38:14 +000035 new_bank0_end = size - 1;
36 mear1 = mpc824x_mpc107_getreg(MEAR1);
37 emear1 = mpc824x_mpc107_getreg(EMEAR1);
38 mear1 = (mear1 & 0xFFFFFF00) |
39 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
40 emear1 = (emear1 & 0xFFFFFF00) |
41 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
42 mpc824x_mpc107_setreg(MEAR1, mear1);
43 mpc824x_mpc107_setreg(EMEAR1, emear1);
wdenk8aeb24e2003-06-20 22:36:30 +000044
wdenk87249ba2004-01-06 22:38:14 +000045 return (size);
wdenk8aeb24e2003-06-20 22:36:30 +000046}
47
48/*
49 * Initialize PCI Devices
50 */
wdenk8aeb24e2003-06-20 22:36:30 +000051#ifndef CONFIG_PCI_PNP
52static struct pci_config_table pci_a3000_config_table[] = {
wdenk21136db2003-07-16 21:53:01 +000053 /* vendor, device, class */
54 /* bus, dev, func */
wdenkdccbda02003-07-14 22:13:32 +000055 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
wdenk21136db2003-07-16 21:53:01 +000056 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */
wdenk8aeb24e2003-06-20 22:36:30 +000057 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
58 PCI_ENET0_MEMADDR,
59 PCI_COMMAND_IO |
60 PCI_COMMAND_MEMORY |
61 PCI_COMMAND_MASTER }},
62 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
wdenk21136db2003-07-16 21:53:01 +000063 PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */
wdenk8aeb24e2003-06-20 22:36:30 +000064 pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
65 PCI_ENET1_MEMADDR,
66 PCI_COMMAND_IO |
67 PCI_COMMAND_MEMORY |
68 PCI_COMMAND_MASTER }},
69 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Wolfgang Denka1be4762008-05-20 16:00:29 +020070 PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
wdenk8aeb24e2003-06-20 22:36:30 +000071 pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
72 PCI_ENET2_MEMADDR,
73 PCI_COMMAND_IO |
74 PCI_COMMAND_MEMORY |
75 PCI_COMMAND_MASTER }},
wdenkdccbda02003-07-14 22:13:32 +000076 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
wdenk21136db2003-07-16 21:53:01 +000077 PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */
wdenkdccbda02003-07-14 22:13:32 +000078 pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
79 PCI_ENET3_MEMADDR,
80 PCI_COMMAND_IO |
81 PCI_COMMAND_MEMORY |
82 PCI_COMMAND_MASTER }},
wdenk8aeb24e2003-06-20 22:36:30 +000083 { }
84};
85#endif
86
wdenk8aeb24e2003-06-20 22:36:30 +000087struct pci_controller hose = {
88#ifndef CONFIG_PCI_PNP
89 config_table: pci_a3000_config_table,
90#endif
91};
92
93void pci_init_board(void)
94{
95 pci_mpc824x_init(&hose);
96}
Ben Warren8d943c82008-08-31 10:07:16 -070097
98int board_eth_init(bd_t *bis)
99{
100 return pci_eth_init(bis);
101}