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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stefan Roese5ffceb82015-03-26 15:36:56 +01002/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
Stefan Roese5ffceb82015-03-26 15:36:56 +01004 */
5
Stefan Roese5ffceb82015-03-26 15:36:56 +01006#include "ddr3_init.h"
Chris Packham1a07d212018-05-10 13:28:29 +12007#include "mv_ddr_common.h"
Stefan Roese5ffceb82015-03-26 15:36:56 +01008
Stefan Roese5ffceb82015-03-26 15:36:56 +01009static char *ddr_type = "DDR3";
10
11/*
Chris Packham1a07d212018-05-10 13:28:29 +120012 * generic_init_controller controls D-unit configuration:
13 * '1' - dynamic D-unit configuration,
Stefan Roese5ffceb82015-03-26 15:36:56 +010014 */
15u8 generic_init_controller = 1;
16
Chris Packham1a07d212018-05-10 13:28:29 +120017static int mv_ddr_training_params_set(u8 dev_num);
Stefan Roese5ffceb82015-03-26 15:36:56 +010018
19/*
Stefan Roese5ffceb82015-03-26 15:36:56 +010020 * Name: ddr3_init - Main DDR3 Init function
21 * Desc: This routine initialize the DDR3 MC and runs HW training.
22 * Args: None.
23 * Notes:
24 * Returns: None.
25 */
26int ddr3_init(void)
27{
Stefan Roese5ffceb82015-03-26 15:36:56 +010028 int status;
Chris Packham1a07d212018-05-10 13:28:29 +120029 int is_manual_cal_done;
Stefan Roese5ffceb82015-03-26 15:36:56 +010030
Chris Packham1a07d212018-05-10 13:28:29 +120031 /* Print mv_ddr version */
32 mv_ddr_ver_print();
Stefan Roese5ffceb82015-03-26 15:36:56 +010033
Chris Packham1a07d212018-05-10 13:28:29 +120034 mv_ddr_pre_training_fixup();
Stefan Roese5ffceb82015-03-26 15:36:56 +010035
Chris Packham1a07d212018-05-10 13:28:29 +120036 /* SoC/Board special initializations */
37 mv_ddr_pre_training_soc_config(ddr_type);
Stefan Roese5ffceb82015-03-26 15:36:56 +010038
Chris Packham1a07d212018-05-10 13:28:29 +120039 /* Set log level for training library */
40 mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
Stefan Roese5ffceb82015-03-26 15:36:56 +010041
Chris Packham1a07d212018-05-10 13:28:29 +120042 mv_ddr_early_init();
Stefan Roese5ffceb82015-03-26 15:36:56 +010043
Chris Packham4bf81db2018-12-03 14:26:49 +130044 if (mv_ddr_topology_map_update()) {
Chris Packham1a07d212018-05-10 13:28:29 +120045 printf("mv_ddr: failed to update topology\n");
46 return MV_FAIL;
Stefan Roese5ffceb82015-03-26 15:36:56 +010047 }
48
Chris Packham1a07d212018-05-10 13:28:29 +120049 if (mv_ddr_early_init2() != MV_OK)
50 return MV_FAIL;
Stefan Roese5ffceb82015-03-26 15:36:56 +010051
Chris Packham1a07d212018-05-10 13:28:29 +120052 /* Set training algorithm's parameters */
53 status = mv_ddr_training_params_set(0);
Stefan Roese5ffceb82015-03-26 15:36:56 +010054 if (MV_OK != status)
55 return status;
Stefan Roese5ffceb82015-03-26 15:36:56 +010056
Chris Packham1a07d212018-05-10 13:28:29 +120057 mv_ddr_mc_config();
Stefan Roese5ffceb82015-03-26 15:36:56 +010058
Chris Packham1a07d212018-05-10 13:28:29 +120059 is_manual_cal_done = mv_ddr_manual_cal_do();
Stefan Roese5ffceb82015-03-26 15:36:56 +010060
Chris Packham1a07d212018-05-10 13:28:29 +120061 mv_ddr_mc_init();
Stefan Roese5ffceb82015-03-26 15:36:56 +010062
Chris Packham1a07d212018-05-10 13:28:29 +120063 if (!is_manual_cal_done) {
Stefan Roese5ffceb82015-03-26 15:36:56 +010064 }
65
Stefan Roese5ffceb82015-03-26 15:36:56 +010066
Chris Packham1a07d212018-05-10 13:28:29 +120067 status = ddr3_silicon_post_init();
68 if (MV_OK != status) {
69 printf("DDR3 Post Init - FAILED 0x%x\n", status);
70 return status;
Stefan Roese5ffceb82015-03-26 15:36:56 +010071 }
72
Chris Packham1a07d212018-05-10 13:28:29 +120073 /* PHY initialization (Training) */
74 status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
75 if (MV_OK != status) {
76 printf("%s Training Sequence - FAILED\n", ddr_type);
77 return status;
Stefan Roese5ffceb82015-03-26 15:36:56 +010078 }
79
Stefan Roese5ffceb82015-03-26 15:36:56 +010080
Chris Packham1a07d212018-05-10 13:28:29 +120081 /* Post MC/PHY initializations */
82 mv_ddr_post_training_soc_config(ddr_type);
Stefan Roese5ffceb82015-03-26 15:36:56 +010083
Chris Packham1a07d212018-05-10 13:28:29 +120084 mv_ddr_post_training_fixup();
Stefan Roese5ffceb82015-03-26 15:36:56 +010085
Chris Packham4bf81db2018-12-03 14:26:49 +130086 if (mv_ddr_is_ecc_ena())
87 mv_ddr_mem_scrubbing();
Stefan Roese5ffceb82015-03-26 15:36:56 +010088
Chris Packham1a07d212018-05-10 13:28:29 +120089 printf("mv_ddr: completed successfully\n");
Stefan Roese5ffceb82015-03-26 15:36:56 +010090
91 return MV_OK;
92}
93
Stefan Roese5ffceb82015-03-26 15:36:56 +010094/*
Chris Packham1a07d212018-05-10 13:28:29 +120095 * Name: mv_ddr_training_params_set
Stefan Roese5ffceb82015-03-26 15:36:56 +010096 * Desc:
97 * Args:
Chris Packham1a07d212018-05-10 13:28:29 +120098 * Notes: sets internal training params
Stefan Roese5ffceb82015-03-26 15:36:56 +010099 * Returns:
100 */
Chris Packham1a07d212018-05-10 13:28:29 +1200101static int mv_ddr_training_params_set(u8 dev_num)
Stefan Roese5ffceb82015-03-26 15:36:56 +0100102{
103 struct tune_train_params params;
Baruch Siach4951d422021-02-19 17:11:17 +0100104 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
Stefan Roese5ffceb82015-03-26 15:36:56 +0100105 int status;
Chris Packham1a07d212018-05-10 13:28:29 +1200106 u32 cs_num;
Chris Packhame422adc2020-01-30 12:50:44 +1300107 int ck_delay;
Chris Packham1a07d212018-05-10 13:28:29 +1200108
Chris Packham4bf81db2018-12-03 14:26:49 +1300109 cs_num = mv_ddr_cs_num_get();
Chris Packhame422adc2020-01-30 12:50:44 +1300110 ck_delay = mv_ddr_ck_delay_get();
Stefan Roese5ffceb82015-03-26 15:36:56 +0100111
112 /* NOTE: do not remove any field initilization */
113 params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
Stefan Roese5ffceb82015-03-26 15:36:56 +0100114 params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
Chris Packham1a07d212018-05-10 13:28:29 +1200115 params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
116 params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
117 params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
118 params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
119 params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
120 params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
121 params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
122
123 params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
124 params.g_dic = TUNE_TRAINING_PARAMS_DIC;
125 params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
126 if (cs_num == 1) {
127 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
128 params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
129 } else {
130 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
131 params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
132 }
Stefan Roese5ffceb82015-03-26 15:36:56 +0100133
Chris Packhame422adc2020-01-30 12:50:44 +1300134 if (ck_delay > 0)
135 params.ck_delay = ck_delay;
136
Baruch Siach4951d422021-02-19 17:11:17 +0100137 /* Use platform specific override ODT value */
138 if (tm->odt_config)
139 params.g_odt_config = tm->odt_config;
140
Stefan Roese5ffceb82015-03-26 15:36:56 +0100141 status = ddr3_tip_tune_training_params(dev_num, &params);
142 if (MV_OK != status) {
143 printf("%s Training Sequence - FAILED\n", ddr_type);
144 return status;
145 }
146
147 return MV_OK;
148}