Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) Marvell International Ltd. and its affiliates |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 6 | #include "ddr3_init.h" |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 7 | #include "mv_ddr_common.h" |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 8 | |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 9 | static char *ddr_type = "DDR3"; |
| 10 | |
| 11 | /* |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 12 | * generic_init_controller controls D-unit configuration: |
| 13 | * '1' - dynamic D-unit configuration, |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 14 | */ |
| 15 | u8 generic_init_controller = 1; |
| 16 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 17 | static int mv_ddr_training_params_set(u8 dev_num); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 18 | |
| 19 | /* |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 20 | * Name: ddr3_init - Main DDR3 Init function |
| 21 | * Desc: This routine initialize the DDR3 MC and runs HW training. |
| 22 | * Args: None. |
| 23 | * Notes: |
| 24 | * Returns: None. |
| 25 | */ |
| 26 | int ddr3_init(void) |
| 27 | { |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 28 | int status; |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 29 | int is_manual_cal_done; |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 30 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 31 | /* Print mv_ddr version */ |
| 32 | mv_ddr_ver_print(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 33 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 34 | mv_ddr_pre_training_fixup(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 35 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 36 | /* SoC/Board special initializations */ |
| 37 | mv_ddr_pre_training_soc_config(ddr_type); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 38 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 39 | /* Set log level for training library */ |
| 40 | mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 41 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 42 | mv_ddr_early_init(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 43 | |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 44 | if (mv_ddr_topology_map_update()) { |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 45 | printf("mv_ddr: failed to update topology\n"); |
| 46 | return MV_FAIL; |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 47 | } |
| 48 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 49 | if (mv_ddr_early_init2() != MV_OK) |
| 50 | return MV_FAIL; |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 51 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 52 | /* Set training algorithm's parameters */ |
| 53 | status = mv_ddr_training_params_set(0); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 54 | if (MV_OK != status) |
| 55 | return status; |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 56 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 57 | mv_ddr_mc_config(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 58 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 59 | is_manual_cal_done = mv_ddr_manual_cal_do(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 60 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 61 | mv_ddr_mc_init(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 62 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 63 | if (!is_manual_cal_done) { |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 64 | } |
| 65 | |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 66 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 67 | status = ddr3_silicon_post_init(); |
| 68 | if (MV_OK != status) { |
| 69 | printf("DDR3 Post Init - FAILED 0x%x\n", status); |
| 70 | return status; |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 71 | } |
| 72 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 73 | /* PHY initialization (Training) */ |
| 74 | status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC); |
| 75 | if (MV_OK != status) { |
| 76 | printf("%s Training Sequence - FAILED\n", ddr_type); |
| 77 | return status; |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 78 | } |
| 79 | |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 80 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 81 | /* Post MC/PHY initializations */ |
| 82 | mv_ddr_post_training_soc_config(ddr_type); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 83 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 84 | mv_ddr_post_training_fixup(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 85 | |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 86 | if (mv_ddr_is_ecc_ena()) |
| 87 | mv_ddr_mem_scrubbing(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 88 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 89 | printf("mv_ddr: completed successfully\n"); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 90 | |
| 91 | return MV_OK; |
| 92 | } |
| 93 | |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 94 | /* |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 95 | * Name: mv_ddr_training_params_set |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 96 | * Desc: |
| 97 | * Args: |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 98 | * Notes: sets internal training params |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 99 | * Returns: |
| 100 | */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 101 | static int mv_ddr_training_params_set(u8 dev_num) |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 102 | { |
| 103 | struct tune_train_params params; |
Baruch Siach | 4951d42 | 2021-02-19 17:11:17 +0100 | [diff] [blame] | 104 | struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 105 | int status; |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 106 | u32 cs_num; |
Chris Packham | e422adc | 2020-01-30 12:50:44 +1300 | [diff] [blame] | 107 | int ck_delay; |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 108 | |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 109 | cs_num = mv_ddr_cs_num_get(); |
Chris Packham | e422adc | 2020-01-30 12:50:44 +1300 | [diff] [blame] | 110 | ck_delay = mv_ddr_ck_delay_get(); |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 111 | |
| 112 | /* NOTE: do not remove any field initilization */ |
| 113 | params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY; |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 114 | params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL; |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 115 | params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA; |
| 116 | params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA; |
| 117 | params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL; |
| 118 | params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL; |
| 119 | params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA; |
| 120 | params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL; |
| 121 | params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL; |
| 122 | |
| 123 | params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA; |
| 124 | params.g_dic = TUNE_TRAINING_PARAMS_DIC; |
| 125 | params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM; |
| 126 | if (cs_num == 1) { |
| 127 | params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS; |
| 128 | params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS; |
| 129 | } else { |
| 130 | params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS; |
| 131 | params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS; |
| 132 | } |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 133 | |
Chris Packham | e422adc | 2020-01-30 12:50:44 +1300 | [diff] [blame] | 134 | if (ck_delay > 0) |
| 135 | params.ck_delay = ck_delay; |
| 136 | |
Baruch Siach | 4951d42 | 2021-02-19 17:11:17 +0100 | [diff] [blame] | 137 | /* Use platform specific override ODT value */ |
| 138 | if (tm->odt_config) |
| 139 | params.g_odt_config = tm->odt_config; |
| 140 | |
Stefan Roese | 5ffceb8 | 2015-03-26 15:36:56 +0100 | [diff] [blame] | 141 | status = ddr3_tip_tune_training_params(dev_num, ¶ms); |
| 142 | if (MV_OK != status) { |
| 143 | printf("%s Training Sequence - FAILED\n", ddr_type); |
| 144 | return status; |
| 145 | } |
| 146 | |
| 147 | return MV_OK; |
| 148 | } |