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git01.mediatek.com / filogic / uboot / 000bb0bc55a07fe52575ed6e542044b57a333944 / . / arch / arm / dts / imx93-11x11-evk-u-boot.dtsi
blob: 408e601bc90eb69744ce1198498e01b12f814ca9 [file] [log] [blame]
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
Mathieu Othacehe0ef03ac2024-01-04 16:30:09 +0100[diff] [blame]6#include "imx93-u-boot.dtsi"
7
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]13 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]14 };
15
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]16 firmware {
17 optee {
18 compatible = "linaro,optee-tz";
19 method = "smc";
20 };
21 };
22};
23
24&{/soc@0} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-all;
26 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]27};
28
Peng Fand64ae662024-04-24 17:12:22 +0800[diff] [blame]29&lpi2c2 {
30 #address-cells = <1>;
31 #size-cells = <0>;
32 clock-frequency = <400000>;
33 pinctrl-names = "default", "sleep";
34 pinctrl-0 = <&pinctrl_lpi2c2>;
35 pinctrl-1 = <&pinctrl_lpi2c2>;
36 status = "okay";
37
38 pmic@25 {
39 compatible = "nxp,pca9451a";
40 reg = <0x25>;
41 interrupt-parent = <&pcal6524>;
42 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
43
44 regulators {
45 buck1: BUCK1 {
46 regulator-name = "BUCK1";
47 regulator-min-microvolt = <650000>;
48 regulator-max-microvolt = <2237500>;
49 regulator-boot-on;
50 regulator-always-on;
51 regulator-ramp-delay = <3125>;
52 };
53
54 buck2: BUCK2 {
55 regulator-name = "BUCK2";
56 regulator-min-microvolt = <600000>;
57 regulator-max-microvolt = <2187500>;
58 regulator-boot-on;
59 regulator-always-on;
60 regulator-ramp-delay = <3125>;
61 };
62
63 buck4: BUCK4{
64 regulator-name = "BUCK4";
65 regulator-min-microvolt = <600000>;
66 regulator-max-microvolt = <3400000>;
67 regulator-boot-on;
68 regulator-always-on;
69 };
70
71 buck5: BUCK5{
72 regulator-name = "BUCK5";
73 regulator-min-microvolt = <600000>;
74 regulator-max-microvolt = <3400000>;
75 regulator-boot-on;
76 regulator-always-on;
77 };
78
79 buck6: BUCK6 {
80 regulator-name = "BUCK6";
81 regulator-min-microvolt = <600000>;
82 regulator-max-microvolt = <3400000>;
83 regulator-boot-on;
84 regulator-always-on;
85 };
86
87 ldo1: LDO1 {
88 regulator-name = "LDO1";
89 regulator-min-microvolt = <1600000>;
90 regulator-max-microvolt = <3300000>;
91 regulator-boot-on;
92 regulator-always-on;
93 };
94
95 ldo4: LDO4 {
96 regulator-name = "LDO4";
97 regulator-min-microvolt = <800000>;
98 regulator-max-microvolt = <3300000>;
99 regulator-boot-on;
100 regulator-always-on;
101 };
102
103 ldo5: LDO5 {
104 regulator-name = "LDO5";
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <3300000>;
107 regulator-boot-on;
108 regulator-always-on;
109 };
110 };
111 };
112
113 pcal6524: gpio@22 {
114 compatible = "nxp,pcal6524";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_pcal6524>;
117 reg = <0x22>;
118 gpio-controller;
119 #gpio-cells = <2>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
122 interrupt-parent = <&gpio3>;
123 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
124 };
125
126 adp5585gpio: gpio@34 {
127 compatible = "adp5585";
128 reg = <0x34>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 };
132};
133
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]134&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-pre-ram;
136 bootph-all;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]137};
138
139&aips2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]141 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]142};
143
144&aips3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]145 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]146 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]147};
148
149&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]150 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]151 bootph-some-ram;
Peng Fand64ae662024-04-24 17:12:22 +0800[diff] [blame]152
153 pinctrl_lpi2c2: lpi2c2grp {
154 fsl,pins = <
155 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
156 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
157 >;
158 };
159
160 pinctrl_pcal6524: pcal6524grp {
161 fsl,pins = <
162 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
163 >;
164 };
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]165};
166
167&reg_usdhc2_vmmc {
168 u-boot,off-on-delay-us = <20000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]169 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]170 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]171};
172
173&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]174 bootph-pre-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]175};
176
177&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]178 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]179 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]180};
181
182&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]183 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]184 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]185};
186
187&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]188 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]189 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]190};
191
192&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]193 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]194 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]195};
196
197&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]198 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]199 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]200};
201
202&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]203 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]204 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]205};
206
207&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]208 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]209 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]210};
211
212&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]213 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]214 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]215};
216
217&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]218 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]219 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]220};
221
222&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]223 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]224 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]225 fsl,signal-voltage-switch-extra-delay-ms = <8>;
226};
227
228&lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]229 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]230 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]231};
232
233&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]234 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]235 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]236};
237
238&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]239 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]240 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]241};
242
243&pinctrl_lpi2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]244 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]245 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]246};
247
248&fec {
249 phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
250 phy-reset-duration = <15>;
251 phy-reset-post-delay = <100>;
252};
253
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]254&ethphy1 {
255 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
256 reset-assert-us = <15000>;
257 reset-deassert-us = <100000>;
258};
259
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]260&s4muap {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]261 bootph-pre-ram;
Sébastien Szymanski47c05802023-10-04 11:08:09 +0200[diff] [blame]262 bootph-some-ram;
Peng Fanb72606c2022-07-26 16:41:10 +0800[diff] [blame]263 status = "okay";
264};
Sébastien Szymanski506d2062023-07-25 10:08:56 +0200[diff] [blame]265
266&clk {
267 bootph-all;
268 bootph-pre-ram;
269 /delete-property/ assigned-clocks;
270 /delete-property/ assigned-clock-rates;
271 /delete-property/ assigned-clock-parents;
272};
273
274&osc_32k {
275 bootph-all;
276 bootph-pre-ram;
277};
278
279&osc_24m {
280 bootph-all;
281 bootph-pre-ram;
282};
283
284&clk_ext1 {
285 bootph-all;
286 bootph-pre-ram;
287};