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filogic
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uboot
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f580a300fa521c03828153ab9bc056012e967c2d
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.
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drivers
/
ddr
/
imx
/
imx8ulp
/
Kconfig
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"i.MX8ULP DDR controllers"
depends on ARCH_IMX8ULP
config IMX8ULP_DRAM
bool
"imx8m dram"
config IMX8ULP_DRAM_PHY_PLL_BYPASS
bool
"Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
depends on IMX8ULP_DRAM
endmenu