| Ye Li | 56499f6 | 2021-08-07 16:01:11 +0800 | [diff] [blame] | 1 | menu "i.MX8ULP DDR controllers" |
| 2 | depends on ARCH_IMX8ULP | ||||
| 3 | |||||
| 4 | config IMX8ULP_DRAM | ||||
| 5 | bool "imx8m dram" | ||||
| 6 | |||||
| 7 | config IMX8ULP_DRAM_PHY_PLL_BYPASS | ||||
| 8 | bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK " | ||||
| 9 | depends on IMX8ULP_DRAM | ||||
| 10 | |||||
| 11 | endmenu | ||||