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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / arch / arm / mach-socfpga / include / mach
tree: 6382a404047f30566b4210c983c31f49fa17fcd9 [path history] [tgz]
  1. altera-sysmgr.h
  2. base_addr_a10.h
  3. base_addr_ac5.h
  4. base_addr_soc64.h
  5. board.h
  6. boot0.h
  7. clock_manager.h
  8. clock_manager_agilex.h
  9. clock_manager_agilex5.h
  10. clock_manager_arria10.h
  11. clock_manager_gen5.h
  12. clock_manager_n5x.h
  13. clock_manager_s10.h
  14. clock_manager_soc64.h
  15. firewall.h
  16. fpga_manager.h
  17. fpga_manager_arria10.h
  18. fpga_manager_gen5.h
  19. freeze_controller.h
  20. gpio.h
  21. handoff_soc64.h
  22. mailbox_s10.h
  23. misc.h
  24. nic301.h
  25. pinmux.h
  26. reset_manager.h
  27. reset_manager_arria10.h
  28. reset_manager_gen5.h
  29. reset_manager_soc64.h
  30. scan_manager.h
  31. scu.h
  32. sdram.h
  33. sdram_arria10.h
  34. sdram_gen5.h
  35. secure_reg_helper.h
  36. secure_vab.h
  37. smc_api.h
  38. system_manager.h
  39. system_manager_arria10.h
  40. system_manager_gen5.h
  41. system_manager_soc64.h
  42. timer.h