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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / arch / arm / mach-socfpga
tree: f10cf55a64f8da5fd418c24afdccaf6e3e141de4 [path history] [tgz]
  1. include/
  2. altera-sysmgr.c
  3. board.c
  4. ccu_ncore3.c
  5. clock_manager.c
  6. clock_manager_agilex.c
  7. clock_manager_agilex5.c
  8. clock_manager_arria10.c
  9. clock_manager_gen5.c
  10. clock_manager_n5x.c
  11. clock_manager_s10.c
  12. firewall.c
  13. fpga_manager.c
  14. freeze_controller.c
  15. Kconfig
  16. lowlevel_init_soc64.S
  17. mailbox_s10.c
  18. Makefile
  19. misc.c
  20. misc_arria10.c
  21. misc_gen5.c
  22. misc_soc64.c
  23. mmu-arm64_s10.c
  24. pinmux_arria10.c
  25. qts-filter-a10.sh
  26. qts-filter.sh
  27. reset_manager_arria10.c
  28. reset_manager_gen5.c
  29. reset_manager_s10.c
  30. scan_manager.c
  31. secure_reg_helper.c
  32. secure_vab.c
  33. smc_api.c
  34. spl_a10.c
  35. spl_agilex.c
  36. spl_agilex5.c
  37. spl_gen5.c
  38. spl_n5x.c
  39. spl_s10.c
  40. spl_soc64.c
  41. system_manager_gen5.c
  42. system_manager_soc64.c
  43. timer.c
  44. timer_s10.c
  45. vab.c
  46. wrap_handoff_soc64.c
  47. wrap_iocsr_config.c
  48. wrap_pinmux_config.c
  49. wrap_pll_config.c
  50. wrap_pll_config_soc64.c
  51. wrap_sdram_config.c