arch/arm/dts/socfpga_agilex5-u-boot.dtsi - filogic/uboot - Gitiles

 // SPDX-License-Identifier: GPL-2.0+
 /*
  * U-Boot additions
  *
  * Copyright (C) 2024 Intel Corporation <www.intel.com>
  * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */

 #include "socfpga_soc64_fit-u-boot.dtsi"

 /{
 	memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		bootph-all;
 	};

 	soc {
 		bootph-all;

 		socfpga_ccu_config: socfpga-ccu-config {
 			compatible = "intel,socfpga-dtreg";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			bootph-all;

 			/* DSU */
 			i_ccu_caiu0@1c000000 {
 				reg = <0x1c000000 0x00001000>;
 				intel,offset-settings =
 					/* CAIUMIFSR */
 					<0x000003c4 0x00000000 0x07070777>,
 					/* DII1_MPFEREGS */
 					<0x00000414 0x00018000 0xffffffff>,
 					<0x00000418 0x00000000 0x000000ff>,
 					<0x00000410 0xc0e00200 0xc1f03e1f>,
 					/* DII2_GICREGS */
 					<0x00000424 0x0001d000 0xffffffff>,
 					<0x00000428 0x00000000 0x000000ff>,
 					<0x00000420 0xc0800400 0xc1f03e1f>,
 					/* NCAIU0_LWSOC2FPGA */
 					<0x00000444 0x00020000 0xffffffff>,
 					<0x00000448 0x00000000 0x000000ff>,
 					<0x00000440 0xc1100006 0xc1f03e1f>,
 					/* NCAIU0_SOC2FPGA_1G */
 					<0x00000454 0x00040000 0xffffffff>,
 					<0x00000458 0x00000000 0x000000ff>,
 					<0x00000450 0xc1200006 0xc1f03e1f>,
 					/* DMI_SDRAM_2G */
 					<0x00000464 0x00080000 0xffffffff>,
 					<0x00000468 0x00000000 0x000000ff>,
 					/* NCAIU0_SOC2FPGA_16G */
 					<0x00000474 0x00400000 0xffffffff>,
 					<0x00000478 0x00000000 0x000000ff>,
 					<0x00000470 0xc1600006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000484 0x00800000 0xffffffff>,
 					<0x00000488 0x00000000 0x000000ff>,
 					/* NCAIU0_SOC2FPGA_256G */
 					<0x00000494 0x04000000 0xffffffff>,
 					<0x00000498 0x00000000 0x000000ff>,
 					<0x00000490 0xc1a00006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a4 0x08000000 0xffffffff>,
 					<0x000004a8 0x00000000 0x000000ff>;
 				bootph-all;
 			};

 			/* FPGA2SOC */
 			i_ccu_ncaiu0@1c001000 {
 				reg = <0x1c001000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU0MIFSR */
 					<0x000003c4 0x00000000 0x07070777>,
 					/* PSS */
 					<0x00000404 0x00010000 0xffffffff>,
 					<0x00000408 0x00000000 0x000000ff>,
 					<0x00000400 0xC0F00000 0xc1f03e1f>,
 					/* DII1_MPFEREGS */
 					<0x00000414 0x00018000 0xffffffff>,
 					<0x00000418 0x00000000 0x000000ff>,
 					<0x00000410 0xc0e00200 0xc1f03e1f>,
 					/* NCAIU0_LWSOC2FPGA */
 					<0x00000444 0x00020000 0xffffffff>,
 					<0x00000448 0x00000000 0x000000ff>,
 					<0x00000440 0xc1100006 0xc1f03e1f>,
 					/* NCAIU0_SOC2FPGA_1G */
 					<0x00000454 0x00040000 0xffffffff>,
 					<0x00000458 0x00000000 0x000000ff>,
 					<0x00000450 0xc1200006 0xc1f03e1f>,
 					/* DMI_SDRAM_2G */
 					<0x00000464 0x00080000 0xffffffff>,
 					<0x00000468 0x00000000 0x000000ff>,
 					/* NCAIU0_SOC2FPGA_16G */
 					<0x00000474 0x00400000 0xffffffff>,
 					<0x00000478 0x00000000 0x000000ff>,
 					<0x00000470 0xc1600006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000484 0x00800000 0xffffffff>,
 					<0x00000488 0x00000000 0x000000ff>,
 					/* NCAIU0_SOC2FPGA_256G */
 					<0x00000494 0x04000000 0xffffffff>,
 					<0x00000498 0x00000000 0x000000ff>,
 					<0x00000490 0xc1a00006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a4 0x08000000 0xffffffff>,
 					<0x000004a8 0x00000000 0x000000ff>;
 				bootph-all;
 			};

 			/* GIC_M */
 			i_ccu_ncaiu1@1c002000 {
 				reg = <0x1c002000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU1MIFSR */
 					<0x000003c4 0x00000000 0x07070777>,
 					/* DMI_SDRAM_2G */
 					<0x00000464 0x00080000 0xffffffff>,
 					<0x00000468 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_30G */
 					<0x00000484 0x00800000 0xffffffff>,
 					<0x00000488 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_480G */
 					<0x000004a4 0x08000000 0xffffffff>,
 					<0x000004a8 0x00000000 0x000000ff>;
 				bootph-all;
 			};

 			/* SMMU */
 			i_ccu_ncaiu2@1c003000 {
 				reg = <0x1c003000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU2MIFSR */
 					<0x000003c4 0x00000000 0x07070777>,
 					/* DMI_SDRAM_2G */
 					<0x00000464 0x00080000 0xffffffff>,
 					<0x00000468 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_30G */
 					<0x00000484 0x00800000 0xffffffff>,
 					<0x00000488 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_480G */
 					<0x000004a4 0x08000000 0xffffffff>,
 					<0x000004a8 0x00000000 0x000000ff>;
 				bootph-all;
 			};

 			/* PSS NOC */
 			i_ccu_ncaiu3@1c004000 {
 				reg = <0x1c004000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU3MIFSR */
 					<0x000003c4 0x00000000 0x07070777>,
 					/* DII1_MPFEREGS */
 					<0x00000414 0x00018000 0xffffffff>,
 					<0x00000418 0x00000000 0x000000ff>,
 					<0x00000410 0xc0e00200 0xc1f03e1f>,
 					/* DMI_SDRAM_2G */
 					<0x00000464 0x00080000 0xffffffff>,
 					<0x00000468 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_30G */
 					<0x00000484 0x00800000 0xffffffff>,
 					<0x00000488 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_480G */
 					<0x000004a4 0x08000000 0xffffffff>,
 					<0x000004a8 0x00000000 0x000000ff>;
 				bootph-all;
 			};

 			/* DCE0 */
 			i_ccu_dce0@1c005000 {
 				reg = <0x1c005000 0x00001000>;
 				intel,offset-settings =
 					/* DCEUMIFSR0 */
 					<0x000003c4 0x00000000 0x07070777>,
 					/* DMI_SDRAM_2G */
 					<0x00000464 0x00080000 0xffffffff>,
 					<0x00000468 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_30G */
 					<0x00000484 0x00800000 0xffffffff>,
 					<0x00000488 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_480G */
 					<0x000004a4 0x08000000 0xffffffff>,
 					<0x000004a8 0x00000000 0x000000ff>;
 				bootph-all;
 			};

 			/* DCE1 */
 			i_ccu_dce1@1c006000 {
 				reg = <0x1c006000 0x00001000>;
 				intel,offset-settings =
 					/* DCEUMIFSR1 */
 					<0x000003c4 0x00000000 0x07070777>,
 					/* DMI_SDRAM_2G */
 					<0x00000464 0x00080000 0xffffffff>,
 					<0x00000468 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_30G */
 					<0x00000484 0x00800000 0xffffffff>,
 					<0x00000488 0x00000000 0x000000ff>,
 					/* DMI_SDRAM_480G */
 					<0x000004a4 0x08000000 0xffffffff>,
 					<0x000004a8 0x00000000 0x000000ff>;
 				bootph-all;
 			};

 			/* DMI0 */
 			i_ccu_dmi0@1c007000 {
 				reg = <0x1c007000 0x00001000>;
 				intel,offset-settings =
 					/* DMIUSMCTCR */
 					<0x00000300 0x00000001 0x00000003>,
 					<0x00000300 0x00000003 0x00000003>;
 				bootph-all;
 			};

 			/* DMI1 */
 			i_ccu_dmi0@1c008000 {
 				reg = <0x1c008000 0x00001000>;
 				intel,offset-settings =
 					/* DMIUSMCTCR */
 					<0x00000300 0x00000001 0x00000003>,
 					<0x00000300 0x00000003 0x00000003>;
 				bootph-all;
 			};
 		};

 		socfpga_firewall_config: socfpga-firewall-config {
 			compatible = "intel,socfpga-dtreg";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			bootph-all;

 			/* L4 peripherals firewall */
 			noc_fw_l4_per@10d21000 {
 				reg = <0x10d21000 0x0000008c>;
 				intel,offset-settings =
 					/* NAND */
 					<0x00000000 0x01010001 0x01010001>,
 					/* USB0 */
 					<0x0000000c 0x01010001 0x01010001>,
 					/* USB1 */
 					<0x00000010 0x01010001 0x01010001>,
 					/* SPI_MAIN0 */
 					<0x0000001c 0x01010301 0x01010301>,
 					/* SPI_MAIN1 */
 					<0x00000020 0x01010301 0x01010301>,
 					/* SPI_SECONDARY0 */
 					<0x00000024 0x01010301 0x01010301>,
 					/* SPI_SECONDARY1 */
 					<0x00000028 0x01010301 0x01010301>,
 					/* EMAC0 */
 					<0x0000002c 0x01010001 0x01010001>,
 					/* EMAC1 */
 					<0x00000030 0x01010001 0x01010001>,
 					/* EMAC2 */
 					<0x00000034 0x01010001 0x01010001>,
 					/* SDMMC */
 					<0x00000040 0x01010001 0x01010001>,
 					/* GPIO0 */
 					<0x00000044 0x01010301 0x01010301>,
 					/* GPIO1 */
 					<0x00000048 0x01010301 0x01010301>,
 					/* I2C0 */
 					<0x00000050 0x01010301 0x01010301>,
 					/* I2C1 */
 					<0x00000054 0x01010301 0x01010301>,
 					/* I2C2 */
 					<0x00000058 0x01010301 0x01010301>,
 					/* I2C3 */
 					<0x0000005c 0x01010301 0x01010301>,
 					/* I2C4 */
 					<0x00000060 0x01010301 0x01010301>,
 					/* SP_TIMER0 */
 					<0x00000064 0x01010301 0x01010301>,
 					/* SP_TIMER1 */
 					<0x00000068 0x01010301 0x01010301>,
 					/* UART0 */
 					<0x0000006c 0x01010301 0x01010301>,
 					/* UART1 */
 					<0x00000070 0x01010301 0x01010301>,
 					/* I3C0 */
 					<0x00000074 0x01010301 0x01010301>,
 					/* I3C1 */
 					<0x00000078 0x01010301 0x01010301>,
 					/* DMA0 */
 					<0x0000007c 0x01010001 0x01010001>,
 					/* DMA1 */
 					<0x00000080 0x01010001 0x01010001>,
 					/* COMBO_PHY */
 					<0x00000084 0x01010001 0x01010001>,
 					/* NAND_SDMA */
 					<0x00000088 0x01010301 0x01010301>;
 				bootph-all;
 			};

 			/* L4 system firewall */
 			noc_fw_l4_sys@10d21100 {
 				reg = <0x10d21100 0x00000098>;
 				intel,offset-settings =
 					/* DMA_ECC */
 					<0x00000008 0x01010001 0x01010001>,
 					/* EMAC0RX_ECC */
 					<0x0000000c 0x01010001 0x01010001>,
 					/* EMAC0TX_ECC */
 					<0x00000010 0x01010001 0x01010001>,
 					/* EMAC1RX_ECC */
 					<0x00000014 0x01010001 0x01010001>,
 					/* EMAC1TX_ECC */
 					<0x00000018 0x01010001 0x01010001>,
 					/* EMAC2RX_ECC */
 					<0x0000001c 0x01010001 0x01010001>,
 					/* EMAC2TX_ECC */
 					<0x00000020 0x01010001 0x01010001>,
 					/* NAND_ECC */
 					<0x0000002c 0x01010001 0x01010001>,
 					/* NAND_READ_ECC */
 					<0x00000030 0x01010001 0x01010001>,
 					/* NAND_WRITE_ECC */
 					<0x00000034 0x01010001 0x01010001>,
 					/* OCRAM_ECC */
 					<0x00000038 0x01010001 0x01010001>,
 					/* SDMMC_ECC */
 					<0x00000040 0x01010001 0x01010001>,
 					/* USB0_ECC */
 					<0x00000044 0x01010001 0x01010001>,
 					/* USB1_CACHEECC */
 					<0x00000048 0x01010001 0x01010001>,
 					/* CLOCK_MANAGER */
 					<0x0000004c 0x01010001 0x01010001>,
 					/* IO_MANAGER */
 					<0x00000054 0x01010001 0x01010001>,
 					/* RESET_MANAGER */
 					<0x00000058 0x01010001 0x01010001>,
 					/* SYSTEM_MANAGER */
 					<0x0000005c 0x01010001 0x01010001>,
 					/* OSC0_TIMER */
 					<0x00000060 0x01010301 0x01010301>,
 					/* OSC1_TIMER0*/
 					<0x00000064 0x01010301 0x01010301>,
 					/* WATCHDOG0 */
 					<0x00000068 0x01010301 0x01010301>,
 					/* WATCHDOG1 */
 					<0x0000006c 0x01010301 0x01010301>,
 					/* WATCHDOG2 */
 					<0x00000070 0x01010301 0x01010301>,
 					/* WATCHDOG3 */
 					<0x00000074 0x01010301 0x01010301>,
 					/* DAP */
 					<0x00000078 0x03010001 0x03010001>,
 					/* WATCHDOG4 */
 					<0x0000007c 0x01010301 0x01010301>,
 					/* POWER_MANAGER */
 					<0x00000080 0x01010001 0x01010001>,
 					/* USB1_RXECC */
 					<0x00000084 0x01010001 0x01010001>,
 					/* USB1_TXECC */
 					<0x00000088 0x01010001 0x01010001>,
 					/* L4_NOC_PROBES */
 					<0x00000090 0x01010001 0x01010001>,
 					/* L4_NOC_QOS */
 					<0x00000094 0x01010001 0x01010001>;
 				bootph-all;
 			};

 			/* Light weight SoC2FPGA */
 			noc_fw_lwsoc2fpga@10d21300 {
 				reg = <0x10d21300 0x0000004>;
 				intel,offset-settings =
 					/* LWSOC2FPGA_CSR */
 					<0x00000000 0x0ffe0301 0x0ffe0301>;
 				bootph-all;
 			};

 			/* SoC2FPGA */
 			noc_fw_soc2fpga@10d21200 {
 				reg = <0x10d21200 0x0000004>;
 				intel,offset-settings =
 					/* SOC2FPGA_CSR */
 					<0x00000000 0x0ffe0301 0x0ffe0301>;
 				bootph-all;
 			};

 			/* TCU */
 			noc_fw_tcu@10d21400 {
 				reg = <0x10d21400 0x0000004>;
 				intel,offset-settings =
 					/* TCU_CSR */
 					<0x00000000 0x01010001 0x01010001>;
 				bootph-all;
 			};
 		};

 		socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
 			compatible = "intel,socfpga-dtreg";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			bootph-all;

 			/* DSU */
 			i_ccu_caiu0@1c000000 {
 				reg = <0x1c000000 0x00001000>;
 				intel,offset-settings =
 					/* CAIUAMIGR */
 					<0x000003c0 0x00000003 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81300006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81700006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81b00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* FPGA2SOC */
 			i_ccu_ncaiu0@1c001000 {
 				reg = <0x1c001000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU0AMIGR */
 					<0x000003c0 0x00000003 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81300006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81700006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81b00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* GIC_M */
 			i_ccu_ncaiu1@1c002000 {
 				reg = <0x1c002000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU1AMIGR */
 					<0x000003c0 0x00000003 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81300006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81700006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81b00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* SMMU */
 			i_ccu_ncaiu2@1c003000 {
 				reg = <0x1c003000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU2AMIGR */
 					<0x000003c0 0x00000003 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81300006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81700006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81b00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* PSS NOC */
 			i_ccu_ncaiu3@1c004000 {
 				reg = <0x1c004000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU3AMIGR */
 					<0x000003c0 0x00000003 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81300006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81700006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81b00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* DCE0 */
 			i_ccu_dce0@1c005000 {
 				reg = <0x1c005000 0x00001000>;
 				intel,offset-settings =
 					/* DCEUAMIGR0 */
 					<0x000003c0 0x00000003 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81300006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81700006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81b00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* DCE1 */
 			i_ccu_dce1@1c006000 {
 				reg = <0x1c006000 0x00001000>;
 				intel,offset-settings =
 					/* DCEUAMIGR1 */
 					<0x000003c0 0x00000003 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81300006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81700006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81b00006 0xc1f03e1f>;
 				bootph-all;
 			};
 		};

 		socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
 			compatible = "intel,socfpga-dtreg";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			bootph-all;

 			/* DSU */
 			i_ccu_caiu0@1c000000 {
 				reg = <0x1c000000 0x00001000>;
 				intel,offset-settings =
 					/* CAIUAMIGR */
 					<0x000003c0 0x00000001 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81200006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81600006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81a00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* FPGA2SOC */
 			i_ccu_ncaiu0@1c001000 {
 				reg = <0x1c001000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU0AMIGR */
 					<0x000003c0 0x00000001 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81200006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81600006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81a00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* GIC_M */
 			i_ccu_ncaiu1@1c002000 {
 				reg = <0x1c002000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU1AMIGR */
 					<0x000003c0 0x00000001 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81200006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81600006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81a00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* SMMU */
 			i_ccu_ncaiu2@1c003000 {
 				reg = <0x1c003000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU2AMIGR */
 					<0x000003c0 0x00000001 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81200006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81600006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81a00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* PSS NOC */
 			i_ccu_ncaiu3@1c004000 {
 				reg = <0x1c004000 0x00001000>;
 				intel,offset-settings =
 					/* NCAIU3AMIGR */
 					<0x000003c0 0x00000001 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81200006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81600006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81a00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* DCE0 */
 			i_ccu_dce0@1c005000 {
 				reg = <0x1c005000 0x00001000>;
 				intel,offset-settings =
 					/* DCEUAMIGR0 */
 					<0x000003c0 0x00000001 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81200006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81600006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81a00006 0xc1f03e1f>;
 				bootph-all;
 			};

 			/* DCE1 */
 			i_ccu_dce1@1c006000 {
 				reg = <0x1c006000 0x00001000>;
 				intel,offset-settings =
 					/* DCEUAMIGR1 */
 					<0x000003c0 0x00000001 0x0000001f>,
 					/* DMI_SDRAM_2G */
 					<0x00000460 0x81200006 0xc1f03e1f>,
 					/* DMI_SDRAM_30G */
 					<0x00000480 0x81600006 0xc1f03e1f>,
 					/* DMI_SDRAM_480G */
 					<0x000004a0 0x81a00006 0xc1f03e1f>;
 				bootph-all;
 			};
 		};

 		socfpga_smmu_secure_config: socfpga-smmu-secure-config {
 			compatible = "intel,socfpga-dtreg";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			bootph-all;

 			/* System manager */
 			i_sys_mgt_sysmgr_csr@10d12000 {
 				reg = <0x10d12000 0x00000500>;
 				intel,offset-settings =
 					/* dma_tbu_stream_ctrl_reg_0_dma0 */
 					<0x0000017c 0x00000000 0x0000003f>,
 					/* dma_tbu_stream_ctrl_reg_0_dma1 */
 					<0x00000180 0x00000000 0x0000003f>,
 					/* sdm_tbu_stream_ctrl_reg_1_sdm */
 					<0x00000184 0x00000000 0x0000003f>,
 					/* io_tbu_stream_ctrl_reg_2_usb2 */
 					<0x00000188 0x00000000 0x0000003f>,
 					/* io_tbu_stream_ctrl_reg_2_sdmmc */
 					<0x00000190 0x00000000 0x0000003f>,
 					/* io_tbu_stream_ctrl_reg_2_nand */
 					<0x00000194 0x00000000 0x0000003f>,
 					/* io_tbu_stream_ctrl_reg_2_etr */
 					<0x00000198 0x00000000 0x0000003f>,
 					/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
 					<0x0000019c 0x00000000 0x0000003f>,
 					/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
 					<0x000001a0 0x00000000 0x0000003f>,
 					/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
 					<0x000001a4 0x00000000 0x0000003f>;
 				bootph-all;
 			};
 		};

 		socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
 			compatible = "intel,socfpga-dtreg";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			bootph-all;

 			/* noc fw mpfe csr */
 			i_noc_fw_mpfe_csr@18000d00 {
 				reg = <0x18000d00 0x00000100>;
 				intel,offset-settings =
 					/* mpfe scr io96b0 reg*/
 					<0x00000000 0x00000001 0x00010101>,
 					/* mpfe scr io96b1 reg*/
 					<0x00000004 0x00000001 0x00010101>,
 					/* mpfe scr noc csr*/
 					<0x00000008 0x00000001 0x00010101>;
 				bootph-all;
 			};
 		};
 	};
 };

 &clkmgr {
 	bootph-all;
 };

 &i2c0 {
 	reset-names = "i2c";
 };

 &i2c1 {
 	reset-names = "i2c";
 };

 &i2c2 {
 	reset-names = "i2c";
 };

 &i2c3 {
 	reset-names = "i2c";
 };

 &mmc {
 	resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
 };

 &porta {
 	bank-name = "porta";
 };

 &portb {
 	bank-name = "portb";
 };

 &qspi {
 	bootph-all;
 };

 &rst {
 	compatible = "altr,rst-mgr";
 	altr,modrst-offset = <0x24>;
 	bootph-all;
 };

 &sdr {
 	compatible = "intel,sdr-ctl-agilex5";
 	reg = <0x18000000 0x400000>;
 	resets = <&rst DDRSCH_RESET>;
 	bootph-all;
 };

 &sysmgr {
 	compatible = "altr,sys-mgr", "syscon";
 	bootph-all;
 };

 &uart0 {
 	bootph-all;
 };

 &watchdog0 {
 	bootph-all;
 };
	// SPDX-License-Identifier: GPL-2.0+
	/*
	* U-Boot additions
	*
	* Copyright (C) 2024 Intel Corporation <www.intel.com>
	* Copyright (C) 2025 Altera Corporation <www.altera.com>
	*/

	#include "socfpga_soc64_fit-u-boot.dtsi"

	/{
	memory {
	#address-cells = <2>;
	#size-cells = <2>;
	bootph-all;
	};

	soc {
	bootph-all;

	socfpga_ccu_config: socfpga-ccu-config {
	compatible = "intel,socfpga-dtreg";
	#address-cells = <1>;
	#size-cells = <1>;
	bootph-all;

	/* DSU */
	i_ccu_caiu0@1c000000 {
	reg = <0x1c000000 0x00001000>;
	intel,offset-settings =
	/* CAIUMIFSR */
	<0x000003c4 0x00000000 0x07070777>,
	/* DII1_MPFEREGS */
	<0x00000414 0x00018000 0xffffffff>,
	<0x00000418 0x00000000 0x000000ff>,
	<0x00000410 0xc0e00200 0xc1f03e1f>,
	/* DII2_GICREGS */
	<0x00000424 0x0001d000 0xffffffff>,
	<0x00000428 0x00000000 0x000000ff>,
	<0x00000420 0xc0800400 0xc1f03e1f>,
	/* NCAIU0_LWSOC2FPGA */
	<0x00000444 0x00020000 0xffffffff>,
	<0x00000448 0x00000000 0x000000ff>,
	<0x00000440 0xc1100006 0xc1f03e1f>,
	/* NCAIU0_SOC2FPGA_1G */
	<0x00000454 0x00040000 0xffffffff>,
	<0x00000458 0x00000000 0x000000ff>,
	<0x00000450 0xc1200006 0xc1f03e1f>,
	/* DMI_SDRAM_2G */
	<0x00000464 0x00080000 0xffffffff>,
	<0x00000468 0x00000000 0x000000ff>,
	/* NCAIU0_SOC2FPGA_16G */
	<0x00000474 0x00400000 0xffffffff>,
	<0x00000478 0x00000000 0x000000ff>,
	<0x00000470 0xc1600006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000484 0x00800000 0xffffffff>,
	<0x00000488 0x00000000 0x000000ff>,
	/* NCAIU0_SOC2FPGA_256G */
	<0x00000494 0x04000000 0xffffffff>,
	<0x00000498 0x00000000 0x000000ff>,
	<0x00000490 0xc1a00006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a4 0x08000000 0xffffffff>,
	<0x000004a8 0x00000000 0x000000ff>;
	bootph-all;
	};

	/* FPGA2SOC */
	i_ccu_ncaiu0@1c001000 {
	reg = <0x1c001000 0x00001000>;
	intel,offset-settings =
	/* NCAIU0MIFSR */
	<0x000003c4 0x00000000 0x07070777>,
	/* PSS */
	<0x00000404 0x00010000 0xffffffff>,
	<0x00000408 0x00000000 0x000000ff>,
	<0x00000400 0xC0F00000 0xc1f03e1f>,
	/* DII1_MPFEREGS */
	<0x00000414 0x00018000 0xffffffff>,
	<0x00000418 0x00000000 0x000000ff>,
	<0x00000410 0xc0e00200 0xc1f03e1f>,
	/* NCAIU0_LWSOC2FPGA */
	<0x00000444 0x00020000 0xffffffff>,
	<0x00000448 0x00000000 0x000000ff>,
	<0x00000440 0xc1100006 0xc1f03e1f>,
	/* NCAIU0_SOC2FPGA_1G */
	<0x00000454 0x00040000 0xffffffff>,
	<0x00000458 0x00000000 0x000000ff>,
	<0x00000450 0xc1200006 0xc1f03e1f>,
	/* DMI_SDRAM_2G */
	<0x00000464 0x00080000 0xffffffff>,
	<0x00000468 0x00000000 0x000000ff>,
	/* NCAIU0_SOC2FPGA_16G */
	<0x00000474 0x00400000 0xffffffff>,
	<0x00000478 0x00000000 0x000000ff>,
	<0x00000470 0xc1600006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000484 0x00800000 0xffffffff>,
	<0x00000488 0x00000000 0x000000ff>,
	/* NCAIU0_SOC2FPGA_256G */
	<0x00000494 0x04000000 0xffffffff>,
	<0x00000498 0x00000000 0x000000ff>,
	<0x00000490 0xc1a00006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a4 0x08000000 0xffffffff>,
	<0x000004a8 0x00000000 0x000000ff>;
	bootph-all;
	};

	/* GIC_M */
	i_ccu_ncaiu1@1c002000 {
	reg = <0x1c002000 0x00001000>;
	intel,offset-settings =
	/* NCAIU1MIFSR */
	<0x000003c4 0x00000000 0x07070777>,
	/* DMI_SDRAM_2G */
	<0x00000464 0x00080000 0xffffffff>,
	<0x00000468 0x00000000 0x000000ff>,
	/* DMI_SDRAM_30G */
	<0x00000484 0x00800000 0xffffffff>,
	<0x00000488 0x00000000 0x000000ff>,
	/* DMI_SDRAM_480G */
	<0x000004a4 0x08000000 0xffffffff>,
	<0x000004a8 0x00000000 0x000000ff>;
	bootph-all;
	};

	/* SMMU */
	i_ccu_ncaiu2@1c003000 {
	reg = <0x1c003000 0x00001000>;
	intel,offset-settings =
	/* NCAIU2MIFSR */
	<0x000003c4 0x00000000 0x07070777>,
	/* DMI_SDRAM_2G */
	<0x00000464 0x00080000 0xffffffff>,
	<0x00000468 0x00000000 0x000000ff>,
	/* DMI_SDRAM_30G */
	<0x00000484 0x00800000 0xffffffff>,
	<0x00000488 0x00000000 0x000000ff>,
	/* DMI_SDRAM_480G */
	<0x000004a4 0x08000000 0xffffffff>,
	<0x000004a8 0x00000000 0x000000ff>;
	bootph-all;
	};

	/* PSS NOC */
	i_ccu_ncaiu3@1c004000 {
	reg = <0x1c004000 0x00001000>;
	intel,offset-settings =
	/* NCAIU3MIFSR */
	<0x000003c4 0x00000000 0x07070777>,
	/* DII1_MPFEREGS */
	<0x00000414 0x00018000 0xffffffff>,
	<0x00000418 0x00000000 0x000000ff>,
	<0x00000410 0xc0e00200 0xc1f03e1f>,
	/* DMI_SDRAM_2G */
	<0x00000464 0x00080000 0xffffffff>,
	<0x00000468 0x00000000 0x000000ff>,
	/* DMI_SDRAM_30G */
	<0x00000484 0x00800000 0xffffffff>,
	<0x00000488 0x00000000 0x000000ff>,
	/* DMI_SDRAM_480G */
	<0x000004a4 0x08000000 0xffffffff>,
	<0x000004a8 0x00000000 0x000000ff>;
	bootph-all;
	};

	/* DCE0 */
	i_ccu_dce0@1c005000 {
	reg = <0x1c005000 0x00001000>;
	intel,offset-settings =
	/* DCEUMIFSR0 */
	<0x000003c4 0x00000000 0x07070777>,
	/* DMI_SDRAM_2G */
	<0x00000464 0x00080000 0xffffffff>,
	<0x00000468 0x00000000 0x000000ff>,
	/* DMI_SDRAM_30G */
	<0x00000484 0x00800000 0xffffffff>,
	<0x00000488 0x00000000 0x000000ff>,
	/* DMI_SDRAM_480G */
	<0x000004a4 0x08000000 0xffffffff>,
	<0x000004a8 0x00000000 0x000000ff>;
	bootph-all;
	};

	/* DCE1 */
	i_ccu_dce1@1c006000 {
	reg = <0x1c006000 0x00001000>;
	intel,offset-settings =
	/* DCEUMIFSR1 */
	<0x000003c4 0x00000000 0x07070777>,
	/* DMI_SDRAM_2G */
	<0x00000464 0x00080000 0xffffffff>,
	<0x00000468 0x00000000 0x000000ff>,
	/* DMI_SDRAM_30G */
	<0x00000484 0x00800000 0xffffffff>,
	<0x00000488 0x00000000 0x000000ff>,
	/* DMI_SDRAM_480G */
	<0x000004a4 0x08000000 0xffffffff>,
	<0x000004a8 0x00000000 0x000000ff>;
	bootph-all;
	};

	/* DMI0 */
	i_ccu_dmi0@1c007000 {
	reg = <0x1c007000 0x00001000>;
	intel,offset-settings =
	/* DMIUSMCTCR */
	<0x00000300 0x00000001 0x00000003>,
	<0x00000300 0x00000003 0x00000003>;
	bootph-all;
	};

	/* DMI1 */
	i_ccu_dmi0@1c008000 {
	reg = <0x1c008000 0x00001000>;
	intel,offset-settings =
	/* DMIUSMCTCR */
	<0x00000300 0x00000001 0x00000003>,
	<0x00000300 0x00000003 0x00000003>;
	bootph-all;
	};
	};

	socfpga_firewall_config: socfpga-firewall-config {
	compatible = "intel,socfpga-dtreg";
	#address-cells = <1>;
	#size-cells = <1>;
	bootph-all;

	/* L4 peripherals firewall */
	noc_fw_l4_per@10d21000 {
	reg = <0x10d21000 0x0000008c>;
	intel,offset-settings =
	/* NAND */
	<0x00000000 0x01010001 0x01010001>,
	/* USB0 */
	<0x0000000c 0x01010001 0x01010001>,
	/* USB1 */
	<0x00000010 0x01010001 0x01010001>,
	/* SPI_MAIN0 */
	<0x0000001c 0x01010301 0x01010301>,
	/* SPI_MAIN1 */
	<0x00000020 0x01010301 0x01010301>,
	/* SPI_SECONDARY0 */
	<0x00000024 0x01010301 0x01010301>,
	/* SPI_SECONDARY1 */
	<0x00000028 0x01010301 0x01010301>,
	/* EMAC0 */
	<0x0000002c 0x01010001 0x01010001>,
	/* EMAC1 */
	<0x00000030 0x01010001 0x01010001>,
	/* EMAC2 */
	<0x00000034 0x01010001 0x01010001>,
	/* SDMMC */
	<0x00000040 0x01010001 0x01010001>,
	/* GPIO0 */
	<0x00000044 0x01010301 0x01010301>,
	/* GPIO1 */
	<0x00000048 0x01010301 0x01010301>,
	/* I2C0 */
	<0x00000050 0x01010301 0x01010301>,
	/* I2C1 */
	<0x00000054 0x01010301 0x01010301>,
	/* I2C2 */
	<0x00000058 0x01010301 0x01010301>,
	/* I2C3 */
	<0x0000005c 0x01010301 0x01010301>,
	/* I2C4 */
	<0x00000060 0x01010301 0x01010301>,
	/* SP_TIMER0 */
	<0x00000064 0x01010301 0x01010301>,
	/* SP_TIMER1 */
	<0x00000068 0x01010301 0x01010301>,
	/* UART0 */
	<0x0000006c 0x01010301 0x01010301>,
	/* UART1 */
	<0x00000070 0x01010301 0x01010301>,
	/* I3C0 */
	<0x00000074 0x01010301 0x01010301>,
	/* I3C1 */
	<0x00000078 0x01010301 0x01010301>,
	/* DMA0 */
	<0x0000007c 0x01010001 0x01010001>,
	/* DMA1 */
	<0x00000080 0x01010001 0x01010001>,
	/* COMBO_PHY */
	<0x00000084 0x01010001 0x01010001>,
	/* NAND_SDMA */
	<0x00000088 0x01010301 0x01010301>;
	bootph-all;
	};

	/* L4 system firewall */
	noc_fw_l4_sys@10d21100 {
	reg = <0x10d21100 0x00000098>;
	intel,offset-settings =
	/* DMA_ECC */
	<0x00000008 0x01010001 0x01010001>,
	/* EMAC0RX_ECC */
	<0x0000000c 0x01010001 0x01010001>,
	/* EMAC0TX_ECC */
	<0x00000010 0x01010001 0x01010001>,
	/* EMAC1RX_ECC */
	<0x00000014 0x01010001 0x01010001>,
	/* EMAC1TX_ECC */
	<0x00000018 0x01010001 0x01010001>,
	/* EMAC2RX_ECC */
	<0x0000001c 0x01010001 0x01010001>,
	/* EMAC2TX_ECC */
	<0x00000020 0x01010001 0x01010001>,
	/* NAND_ECC */
	<0x0000002c 0x01010001 0x01010001>,
	/* NAND_READ_ECC */
	<0x00000030 0x01010001 0x01010001>,
	/* NAND_WRITE_ECC */
	<0x00000034 0x01010001 0x01010001>,
	/* OCRAM_ECC */
	<0x00000038 0x01010001 0x01010001>,
	/* SDMMC_ECC */
	<0x00000040 0x01010001 0x01010001>,
	/* USB0_ECC */
	<0x00000044 0x01010001 0x01010001>,
	/* USB1_CACHEECC */
	<0x00000048 0x01010001 0x01010001>,
	/* CLOCK_MANAGER */
	<0x0000004c 0x01010001 0x01010001>,
	/* IO_MANAGER */
	<0x00000054 0x01010001 0x01010001>,
	/* RESET_MANAGER */
	<0x00000058 0x01010001 0x01010001>,
	/* SYSTEM_MANAGER */
	<0x0000005c 0x01010001 0x01010001>,
	/* OSC0_TIMER */
	<0x00000060 0x01010301 0x01010301>,
	/* OSC1_TIMER0*/
	<0x00000064 0x01010301 0x01010301>,
	/* WATCHDOG0 */
	<0x00000068 0x01010301 0x01010301>,
	/* WATCHDOG1 */
	<0x0000006c 0x01010301 0x01010301>,
	/* WATCHDOG2 */
	<0x00000070 0x01010301 0x01010301>,
	/* WATCHDOG3 */
	<0x00000074 0x01010301 0x01010301>,
	/* DAP */
	<0x00000078 0x03010001 0x03010001>,
	/* WATCHDOG4 */
	<0x0000007c 0x01010301 0x01010301>,
	/* POWER_MANAGER */
	<0x00000080 0x01010001 0x01010001>,
	/* USB1_RXECC */
	<0x00000084 0x01010001 0x01010001>,
	/* USB1_TXECC */
	<0x00000088 0x01010001 0x01010001>,
	/* L4_NOC_PROBES */
	<0x00000090 0x01010001 0x01010001>,
	/* L4_NOC_QOS */
	<0x00000094 0x01010001 0x01010001>;
	bootph-all;
	};

	/* Light weight SoC2FPGA */
	noc_fw_lwsoc2fpga@10d21300 {
	reg = <0x10d21300 0x0000004>;
	intel,offset-settings =
	/* LWSOC2FPGA_CSR */
	<0x00000000 0x0ffe0301 0x0ffe0301>;
	bootph-all;
	};

	/* SoC2FPGA */
	noc_fw_soc2fpga@10d21200 {
	reg = <0x10d21200 0x0000004>;
	intel,offset-settings =
	/* SOC2FPGA_CSR */
	<0x00000000 0x0ffe0301 0x0ffe0301>;
	bootph-all;
	};

	/* TCU */
	noc_fw_tcu@10d21400 {
	reg = <0x10d21400 0x0000004>;
	intel,offset-settings =
	/* TCU_CSR */
	<0x00000000 0x01010001 0x01010001>;
	bootph-all;
	};
	};

	socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
	compatible = "intel,socfpga-dtreg";
	#address-cells = <1>;
	#size-cells = <1>;
	bootph-all;

	/* DSU */
	i_ccu_caiu0@1c000000 {
	reg = <0x1c000000 0x00001000>;
	intel,offset-settings =
	/* CAIUAMIGR */
	<0x000003c0 0x00000003 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81300006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81700006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81b00006 0xc1f03e1f>;
	bootph-all;
	};

	/* FPGA2SOC */
	i_ccu_ncaiu0@1c001000 {
	reg = <0x1c001000 0x00001000>;
	intel,offset-settings =
	/* NCAIU0AMIGR */
	<0x000003c0 0x00000003 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81300006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81700006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81b00006 0xc1f03e1f>;
	bootph-all;
	};

	/* GIC_M */
	i_ccu_ncaiu1@1c002000 {
	reg = <0x1c002000 0x00001000>;
	intel,offset-settings =
	/* NCAIU1AMIGR */
	<0x000003c0 0x00000003 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81300006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81700006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81b00006 0xc1f03e1f>;
	bootph-all;
	};

	/* SMMU */
	i_ccu_ncaiu2@1c003000 {
	reg = <0x1c003000 0x00001000>;
	intel,offset-settings =
	/* NCAIU2AMIGR */
	<0x000003c0 0x00000003 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81300006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81700006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81b00006 0xc1f03e1f>;
	bootph-all;
	};

	/* PSS NOC */
	i_ccu_ncaiu3@1c004000 {
	reg = <0x1c004000 0x00001000>;
	intel,offset-settings =
	/* NCAIU3AMIGR */
	<0x000003c0 0x00000003 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81300006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81700006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81b00006 0xc1f03e1f>;
	bootph-all;
	};

	/* DCE0 */
	i_ccu_dce0@1c005000 {
	reg = <0x1c005000 0x00001000>;
	intel,offset-settings =
	/* DCEUAMIGR0 */
	<0x000003c0 0x00000003 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81300006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81700006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81b00006 0xc1f03e1f>;
	bootph-all;
	};

	/* DCE1 */
	i_ccu_dce1@1c006000 {
	reg = <0x1c006000 0x00001000>;
	intel,offset-settings =
	/* DCEUAMIGR1 */
	<0x000003c0 0x00000003 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81300006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81700006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81b00006 0xc1f03e1f>;
	bootph-all;
	};
	};

	socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
	compatible = "intel,socfpga-dtreg";
	#address-cells = <1>;
	#size-cells = <1>;
	bootph-all;

	/* DSU */
	i_ccu_caiu0@1c000000 {
	reg = <0x1c000000 0x00001000>;
	intel,offset-settings =
	/* CAIUAMIGR */
	<0x000003c0 0x00000001 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81200006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81600006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81a00006 0xc1f03e1f>;
	bootph-all;
	};

	/* FPGA2SOC */
	i_ccu_ncaiu0@1c001000 {
	reg = <0x1c001000 0x00001000>;
	intel,offset-settings =
	/* NCAIU0AMIGR */
	<0x000003c0 0x00000001 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81200006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81600006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81a00006 0xc1f03e1f>;
	bootph-all;
	};

	/* GIC_M */
	i_ccu_ncaiu1@1c002000 {
	reg = <0x1c002000 0x00001000>;
	intel,offset-settings =
	/* NCAIU1AMIGR */
	<0x000003c0 0x00000001 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81200006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81600006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81a00006 0xc1f03e1f>;
	bootph-all;
	};

	/* SMMU */
	i_ccu_ncaiu2@1c003000 {
	reg = <0x1c003000 0x00001000>;
	intel,offset-settings =
	/* NCAIU2AMIGR */
	<0x000003c0 0x00000001 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81200006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81600006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81a00006 0xc1f03e1f>;
	bootph-all;
	};

	/* PSS NOC */
	i_ccu_ncaiu3@1c004000 {
	reg = <0x1c004000 0x00001000>;
	intel,offset-settings =
	/* NCAIU3AMIGR */
	<0x000003c0 0x00000001 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81200006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81600006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81a00006 0xc1f03e1f>;
	bootph-all;
	};

	/* DCE0 */
	i_ccu_dce0@1c005000 {
	reg = <0x1c005000 0x00001000>;
	intel,offset-settings =
	/* DCEUAMIGR0 */
	<0x000003c0 0x00000001 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81200006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81600006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81a00006 0xc1f03e1f>;
	bootph-all;
	};

	/* DCE1 */
	i_ccu_dce1@1c006000 {
	reg = <0x1c006000 0x00001000>;
	intel,offset-settings =
	/* DCEUAMIGR1 */
	<0x000003c0 0x00000001 0x0000001f>,
	/* DMI_SDRAM_2G */
	<0x00000460 0x81200006 0xc1f03e1f>,
	/* DMI_SDRAM_30G */
	<0x00000480 0x81600006 0xc1f03e1f>,
	/* DMI_SDRAM_480G */
	<0x000004a0 0x81a00006 0xc1f03e1f>;
	bootph-all;
	};
	};

	socfpga_smmu_secure_config: socfpga-smmu-secure-config {
	compatible = "intel,socfpga-dtreg";
	#address-cells = <1>;
	#size-cells = <1>;
	bootph-all;

	/* System manager */
	i_sys_mgt_sysmgr_csr@10d12000 {
	reg = <0x10d12000 0x00000500>;
	intel,offset-settings =
	/* dma_tbu_stream_ctrl_reg_0_dma0 */
	<0x0000017c 0x00000000 0x0000003f>,
	/* dma_tbu_stream_ctrl_reg_0_dma1 */
	<0x00000180 0x00000000 0x0000003f>,
	/* sdm_tbu_stream_ctrl_reg_1_sdm */
	<0x00000184 0x00000000 0x0000003f>,
	/* io_tbu_stream_ctrl_reg_2_usb2 */
	<0x00000188 0x00000000 0x0000003f>,
	/* io_tbu_stream_ctrl_reg_2_sdmmc */
	<0x00000190 0x00000000 0x0000003f>,
	/* io_tbu_stream_ctrl_reg_2_nand */
	<0x00000194 0x00000000 0x0000003f>,
	/* io_tbu_stream_ctrl_reg_2_etr */
	<0x00000198 0x00000000 0x0000003f>,
	/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
	<0x0000019c 0x00000000 0x0000003f>,
	/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
	<0x000001a0 0x00000000 0x0000003f>,
	/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
	<0x000001a4 0x00000000 0x0000003f>;
	bootph-all;
	};
	};

	socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
	compatible = "intel,socfpga-dtreg";
	#address-cells = <1>;
	#size-cells = <1>;
	bootph-all;

	/* noc fw mpfe csr */
	i_noc_fw_mpfe_csr@18000d00 {
	reg = <0x18000d00 0x00000100>;
	intel,offset-settings =
	/* mpfe scr io96b0 reg*/
	<0x00000000 0x00000001 0x00010101>,
	/* mpfe scr io96b1 reg*/
	<0x00000004 0x00000001 0x00010101>,
	/* mpfe scr noc csr*/
	<0x00000008 0x00000001 0x00010101>;
	bootph-all;
	};
	};
	};
	};

	&clkmgr {
	bootph-all;
	};

	&i2c0 {
	reset-names = "i2c";
	};

	&i2c1 {
	reset-names = "i2c";
	};

	&i2c2 {
	reset-names = "i2c";
	};

	&i2c3 {
	reset-names = "i2c";
	};

	&mmc {
	resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
	};

	&porta {
	bank-name = "porta";
	};

	&portb {
	bank-name = "portb";
	};

	&qspi {
	bootph-all;
	};

	&rst {
	compatible = "altr,rst-mgr";
	altr,modrst-offset = <0x24>;
	bootph-all;
	};

	&sdr {
	compatible = "intel,sdr-ctl-agilex5";
	reg = <0x18000000 0x400000>;
	resets = <&rst DDRSCH_RESET>;
	bootph-all;
	};

	&sysmgr {
	compatible = "altr,sys-mgr", "syscon";
	bootph-all;
	};

	&uart0 {
	bootph-all;
	};

	&watchdog0 {
	bootph-all;
	};