| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
| */ |
| |
| #include <dm.h> |
| #include <syscon.h> |
| #include <dm/pinctrl.h> |
| #include <asm/io.h> |
| #include <asm/arch-rockchip/clock.h> |
| #include <asm/arch-rockchip/hardware.h> |
| #include <asm/arch-rockchip/grf_rk3399.h> |
| #include <asm/arch-rockchip/misc.h> |
| #include "../common/common.h" |
| |
| static void setup_iodomain(void) |
| { |
| const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3; |
| struct rk3399_grf_regs *grf = |
| syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
| |
| /* |
| * Set bit 3 in GRF_IO_VSEL so PCIE_RST# works (pin GPIO4_C6). |
| * Linux assumes that PCIE_RST# works out of the box as it probes |
| * PCIe before loading the iodomain driver. |
| */ |
| rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT); |
| } |
| |
| int misc_init_r(void) |
| { |
| const u32 cpuid_offset = 0x7; |
| const u32 cpuid_length = 0x10; |
| u8 cpuid[cpuid_length]; |
| int ret; |
| |
| ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); |
| if (ret) |
| return ret; |
| |
| ret = rockchip_cpuid_set(cpuid, cpuid_length); |
| if (ret) |
| return ret; |
| |
| ret = rockchip_setup_macaddr(); |
| if (ret) |
| return ret; |
| |
| setup_iodomain(); |
| setup_boottargets(); |
| |
| return 0; |
| } |