| /* |
| * (C) Copyright 2010,2011 |
| * NVIDIA Corporation <www.nvidia.com> |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #ifndef __TEGRA2_COMMON_H |
| #define __TEGRA2_COMMON_H |
| #include <asm/sizes.h> |
| |
| /* |
| * High Level Configuration Options |
| */ |
| #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ |
| #define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */ |
| #define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */ |
| #define CONFIG_L2_OFF /* No L2 cache */ |
| |
| #define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */ |
| |
| #include <asm/arch/tegra2.h> /* get chip and board defs */ |
| |
| /* |
| * Display CPU and Board information |
| */ |
| #define CONFIG_DISPLAY_CPUINFO |
| #define CONFIG_DISPLAY_BOARDINFO |
| |
| #define CONFIG_SKIP_RELOCATE_UBOOT |
| #define CONFIG_SKIP_LOWLEVEL_INIT |
| |
| #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| |
| /* Environment */ |
| #define CONFIG_ENV_IS_NOWHERE |
| #define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */ |
| |
| /* |
| * Size of malloc() pool |
| */ |
| #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ |
| |
| /* |
| * PllX Configuration |
| */ |
| #define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ |
| |
| /* |
| * NS16550 Configuration |
| */ |
| #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ |
| |
| #define CONFIG_SYS_NS16550 |
| #define CONFIG_SYS_NS16550_SERIAL |
| #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
| |
| /* |
| * select serial console configuration |
| */ |
| #define CONFIG_CONS_INDEX 1 |
| |
| /* allow to overwrite serial and ethaddr */ |
| #define CONFIG_ENV_OVERWRITE |
| #define CONFIG_BAUDRATE 115200 |
| #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 115200} |
| |
| /* include default commands */ |
| #include <config_cmd_default.h> |
| |
| /* remove unused commands */ |
| #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
| #undef CONFIG_CMD_FPGA /* FPGA configuration support */ |
| #undef CONFIG_CMD_IMI |
| #undef CONFIG_CMD_IMLS |
| #undef CONFIG_CMD_NFS /* NFS support */ |
| #undef CONFIG_CMD_NET /* network support */ |
| |
| /* turn on command-line edit/hist/auto */ |
| #define CONFIG_CMDLINE_EDITING |
| #define CONFIG_COMMAND_HISTORY |
| #define CONFIG_AUTOCOMPLETE |
| |
| #define CONFIG_SYS_NO_FLASH |
| |
| /* Environment information */ |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| "console=ttyS0,115200n8\0" \ |
| "mem=" TEGRA2_SYSMEM "\0" \ |
| "smpflag=smp\0" \ |
| |
| #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ |
| #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ |
| |
| /* |
| * Miscellaneous configurable options |
| */ |
| #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
| #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| #define CONFIG_SYS_PROMPT V_PROMPT |
| /* |
| * Increasing the size of the IO buffer as default nfsargs size is more |
| * than 256 and so it is not possible to edit it |
| */ |
| #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ |
| /* Print Buffer Size */ |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| sizeof(CONFIG_SYS_PROMPT) + 16) |
| #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| /* Boot Argument Buffer Size */ |
| #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
| |
| #define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000) |
| #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) |
| |
| #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ |
| #define CONFIG_SYS_HZ 1000 |
| |
| /*----------------------------------------------------------------------- |
| * Stack sizes |
| * |
| * The stack sizes are set up in start.S using the settings below |
| */ |
| #define CONFIG_STACKBASE 0x2800000 /* 40MB */ |
| #define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/ |
| |
| /*----------------------------------------------------------------------- |
| * Physical Memory Map |
| */ |
| #define CONFIG_NR_DRAM_BANKS 1 |
| #define PHYS_SDRAM_1 TEGRA2_SDRC_CS0 |
| #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ |
| |
| #define CONFIG_SYS_TEXT_BASE 0x00E08000 |
| #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| |
| #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
| #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN |
| #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| CONFIG_SYS_INIT_RAM_SIZE - \ |
| GENERATED_GBL_DATA_SIZE) |
| |
| #endif /* __TEGRA2_COMMON_H */ |