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git01.mediatek.com / filogic / rdk-b / meta-filogic / d0c89454d1508a87e6d6ef257e4be2556cd41672 / . / recipes-wifi / linux-mt76 / files / patches-3.x / 0108-mtk-mt76-add-internal-debug-tool.patch
blob: 37f775992c430541141f606545e319f365039e18 [file] [log] [blame]
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]1From 9ba1059c52cbf12123e8b3531291623e692fe1d9 Mon Sep 17 00:00:00 2001
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Mon, 22 Apr 2024 12:22:05 +0800
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]4Subject: [PATCH 108/223] mtk: mt76: add internal debug tool
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]5
6Add the following DebugFS knobs:
7- reset_counter: reset TX/RX statistical counters in FW, WTBL, and MT76.
8- per: show PER, which is calculated using MPDU-based statistics from CMDRPT-TX.
9
10Sources of statistics stored in Eagle mt76_sta_stats are summarized below.
11<tx_bytes> source: CMDRPT-TX
12<tx_packets> unit: MSDU. source: WTBL.
13<tx_retries> unit: MPDU. source: TX-Free-Done Event
14<tx_failed> unit: MPDU. source: TX-Free-Done Event
15<tx_total_mpdu_cnt> unit: MPDU. source: CMDRPT-TX
16<tx_failed_mpdu_cnt> unit: MPDU. source: CMDRPT-TX
17<rx_bytes> source: RXRPT
18<rx_packets> unit: MSDU. source: WTBL.
19<rx_errors> Not used.
20<rx_drops> Not used.
21
22Add token pending time
23
24Refactor DebugFS knob amsdu_info to read unambiguous CR addresses for HW-AMSDU information.
25
26Remove the duplicate function in mtk_debugfs.c & mtk_debug_i.c
27Only enable mt7996_mcu_fw_log_2_host function in mcu.c
28
29mtk: wifi: mt76: mt7996: add more ids support for eagle and kite
30
31IDS is the internal debug commands for firmware debug usage. This
32debugfs will be called only when we use chihuahua tool. Since MT7990 and
33MT7992 use the same firmware branch. This commit change some ids idx and
34support mode ids options as below:
35
361. set fw_dbg=2:62 for MUCOP
372. set fw_dbg=1:85 for BSRP
383. set fw_dbg=1:86 for Tput Monitor
394. set fw_dbg=1:100 for MLO
405. set fw_dbg=1:101 for ERROR Log
41
42mtk: wifi: mt76: mt7996: revise DebugFS command ple_info to show correct TXCMD queue information
43
44Each band has its own set of TXCMD queues in PLE module.
45However, the original codebase only specifies one shared set of queues with wrong queue indices.
46
47mtk: wifi: mt76: mt7992: revise DebugFS command ple_info to accommodate Kite
48
49Because Kite only supports 512 STAs, the number of AC_QUEUE_EMPTY CRs is less than that of Eagle.
50Consequently, some related macros have to be revised to prevent reading wrong CRs.
51
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]52Change-Id: I22331b413b0583c4209f733ad197369fa8939d97
53Change-Id: Ic01c288fda25886a9c384441704cb7a9f86f6209
54Change-Id: I3515144170aad82c23d38a6eedad8843f818058d
55Change-Id: Iea052180b469e8ae8ba759ddb4bcf028fce3dace
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]56Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
57Signed-off-by: MeiChia Chiu <meichia.chiu@mediatek.com>
58Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
59Signed-off-by: Benjamin Lin <benjamin-jw.lin@mediatek.com>
60Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
61---
62 mt7996/Makefile | 3 +-
63 mt7996/debugfs.c | 6 +-
64 mt7996/init.c | 4 +
65 mt7996/mac.c | 2 +
66 mt7996/mt7996.h | 12 +
67 mt7996/mtk_debug_i.h | 987 +++++++++++++++++++++++++++++++++++++++++
68 mt7996/mtk_debugfs_i.c | 720 ++++++++++++++++++++++++++++++
69 7 files changed, 1732 insertions(+), 2 deletions(-)
70 create mode 100644 mt7996/mtk_debug_i.h
71 create mode 100644 mt7996/mtk_debugfs_i.c
72
73diff --git a/mt7996/Makefile b/mt7996/Makefile
74index 6643c7a3..49ec9154 100644
75--- a/mt7996/Makefile
76+++ b/mt7996/Makefile
77@@ -1,4 +1,5 @@
78 # SPDX-License-Identifier: ISC
79+EXTRA_CFLAGS += -Werror
80 EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
81 EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
82 EXTRA_CFLAGS += -DCONFIG_MTK_VENDOR
83@@ -11,4 +12,4 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
84 mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o
85 mt7996e-$(CONFIG_NL80211_TESTMODE) += testmode.o
86
87-mt7996e-y += mtk_debugfs.o mtk_mcu.o
88+mt7996e-y += mtk_debugfs.o mtk_mcu.o mtk_debugfs_i.o
89diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]90index db41e378..7e545f61 100644
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]91--- a/mt7996/debugfs.c
92+++ b/mt7996/debugfs.c
93@@ -1118,8 +1118,12 @@ int mt7996_init_debugfs(struct mt7996_phy *phy)
94 debugfs_create_file("fw_debug_muru_disable", 0600, dir, dev,
95 &fops_fw_debug_muru_disable);
96
97- if (phy == &dev->phy)
98+ if (phy == &dev->phy) {
99 dev->debugfs_dir = dir;
100+#ifdef CONFIG_MTK_DEBUG
101+ mt7996_mtk_init_debugfs_internal(phy, dir);
102+#endif
103+ }
104
105 #ifdef CONFIG_MTK_DEBUG
106 debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
107diff --git a/mt7996/init.c b/mt7996/init.c
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]108index 211ad40c..1d31e96a 100644
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]109--- a/mt7996/init.c
110+++ b/mt7996/init.c
111@@ -886,6 +886,10 @@ void mt7996_rro_hw_init(struct mt7996_dev *dev)
112 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0,
113 dev->wed_rro.addr_elem[0].phy_addr);
114 } else {
115+ INIT_LIST_HEAD(&dev->wed_rro.pg_addr_cache);
116+ for (i = 0; i < MT7996_RRO_MSDU_PG_HASH_SIZE; i++)
117+ INIT_LIST_HEAD(&dev->wed_rro.pg_hash_head[i]);
118+
119 /* TODO: remove line after WM has set */
120 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK);
121
122diff --git a/mt7996/mac.c b/mt7996/mac.c
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]123index cd139111..2e27e3b3 100644
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]124--- a/mt7996/mac.c
125+++ b/mt7996/mac.c
126@@ -334,6 +334,7 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q,
127 #ifdef CONFIG_MTK_DEBUG
128 if (dev->dbg.dump_rx_raw)
129 mt7996_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
130+ mt7996_dump_bmac_rxd_info(dev, rxd);
131 #endif
132 hw_aggr = status->aggr;
133 memset(status, 0, sizeof(*status));
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]134@@ -1007,6 +1008,7 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]135 mt7996_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
136 if (dev->dbg.dump_tx_pkt)
137 mt7996_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
138+ mt7996_dump_bmac_txd_info(NULL, dev, (__le32 *)txwi, true, false);
139 #endif
140
141 return 0;
142diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]143index 00023a5e..e23ed8e7 100644
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]144--- a/mt7996/mt7996.h
145+++ b/mt7996/mt7996.h
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]146@@ -103,6 +103,7 @@
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]147
148 #define MT7996_BUILD_TIME_LEN 24
149
150+#define MT7996_RRO_MSDU_PG_HASH_SIZE 127
151 #define MT7996_RRO_MAX_SESSION 1024
152 #define MT7996_RRO_WINDOW_MAX_LEN 1024
153 #define MT7996_RRO_ADDR_ELEM_LEN 128
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]154@@ -689,6 +690,9 @@ struct mt7996_dev {
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]155 struct work_struct work;
156 struct list_head poll_list;
157 spinlock_t lock;
158+
159+ struct list_head pg_addr_cache;
160+ struct list_head pg_hash_head[MT7996_RRO_MSDU_PG_HASH_SIZE];
161 } wed_rro;
162
163 bool testmode_enable;
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]164@@ -749,7 +753,11 @@ struct mt7996_dev {
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]165 bool dump_tx_pkt:1;
166 bool dump_rx_pkt:1;
167 bool dump_rx_raw:1;
168+ u8 dump_ple_txd;
169 u32 token_idx;
170+ u32 rxd_read_cnt;
171+ u32 txd_read_cnt;
172+ u32 fid_idx;
173 } dbg;
174 const struct mt7996_dbg_reg_desc *dbg_reg;
175 #endif
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]176@@ -1292,6 +1300,10 @@ enum {
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]177 };
178
179 void mt7996_packet_log_to_host(struct mt7996_dev *dev, const void *data, int len, int type, int des_len);
180+void mt7996_dump_bmac_rxd_info(struct mt7996_dev *dev, __le32 *rxd);
181+void mt7996_dump_bmac_txd_info(struct seq_file *s, struct mt7996_dev *dev,
182+ __le32 *txd, bool is_hif_txd, bool dump_txp);
183+int mt7996_mtk_init_debugfs_internal(struct mt7996_phy *phy, struct dentry *dir);
184 #endif
185
186 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
187diff --git a/mt7996/mtk_debug_i.h b/mt7996/mtk_debug_i.h
188new file mode 100644
189index 00000000..d3756fa2
190--- /dev/null
191+++ b/mt7996/mtk_debug_i.h
192@@ -0,0 +1,987 @@
193+#ifndef __MTK_DEBUG_I_H
194+#define __MTK_DEBUG_I_H
195+
196+#ifdef CONFIG_MTK_DEBUG
197+
198+// DW0
199+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_DW 0
200+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_ADDR 0
201+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_MASK 0x0000ffff // 15- 0
202+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_SHIFT 0
203+#define WF_RX_DESCRIPTOR_PACKET_TYPE_DW 0
204+#define WF_RX_DESCRIPTOR_PACKET_TYPE_ADDR 0
205+#define WF_RX_DESCRIPTOR_PACKET_TYPE_MASK 0xf8000000 // 31-27
206+#define WF_RX_DESCRIPTOR_PACKET_TYPE_SHIFT 27
207+// DW1
208+#define WF_RX_DESCRIPTOR_MLD_ID_DW 1
209+#define WF_RX_DESCRIPTOR_MLD_ID_ADDR 4
210+#define WF_RX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0
211+#define WF_RX_DESCRIPTOR_MLD_ID_SHIFT 0
212+#define WF_RX_DESCRIPTOR_GROUP_VLD_DW 1
213+#define WF_RX_DESCRIPTOR_GROUP_VLD_ADDR 4
214+#define WF_RX_DESCRIPTOR_GROUP_VLD_MASK 0x001f0000 // 20-16
215+#define WF_RX_DESCRIPTOR_GROUP_VLD_SHIFT 16
216+#define WF_RX_DESCRIPTOR_KID_DW 1
217+#define WF_RX_DESCRIPTOR_KID_ADDR 4
218+#define WF_RX_DESCRIPTOR_KID_MASK 0x00600000 // 22-21
219+#define WF_RX_DESCRIPTOR_KID_SHIFT 21
220+#define WF_RX_DESCRIPTOR_CM_DW 1
221+#define WF_RX_DESCRIPTOR_CM_ADDR 4
222+#define WF_RX_DESCRIPTOR_CM_MASK 0x00800000 // 23-23
223+#define WF_RX_DESCRIPTOR_CM_SHIFT 23
224+#define WF_RX_DESCRIPTOR_CLM_DW 1
225+#define WF_RX_DESCRIPTOR_CLM_ADDR 4
226+#define WF_RX_DESCRIPTOR_CLM_MASK 0x01000000 // 24-24
227+#define WF_RX_DESCRIPTOR_CLM_SHIFT 24
228+#define WF_RX_DESCRIPTOR_I_DW 1
229+#define WF_RX_DESCRIPTOR_I_ADDR 4
230+#define WF_RX_DESCRIPTOR_I_MASK 0x02000000 // 25-25
231+#define WF_RX_DESCRIPTOR_I_SHIFT 25
232+#define WF_RX_DESCRIPTOR_T_DW 1
233+#define WF_RX_DESCRIPTOR_T_ADDR 4
234+#define WF_RX_DESCRIPTOR_T_MASK 0x04000000 // 26-26
235+#define WF_RX_DESCRIPTOR_T_SHIFT 26
236+#define WF_RX_DESCRIPTOR_BN_DW 1
237+#define WF_RX_DESCRIPTOR_BN_ADDR 4
238+#define WF_RX_DESCRIPTOR_BN_MASK 0x18000000 // 28-27
239+#define WF_RX_DESCRIPTOR_BN_SHIFT 27
240+#define WF_RX_DESCRIPTOR_BIPN_FAIL_DW 1
241+#define WF_RX_DESCRIPTOR_BIPN_FAIL_ADDR 4
242+#define WF_RX_DESCRIPTOR_BIPN_FAIL_MASK 0x20000000 // 29-29
243+#define WF_RX_DESCRIPTOR_BIPN_FAIL_SHIFT 29
244+// DW2
245+#define WF_RX_DESCRIPTOR_BSSID_DW 2
246+#define WF_RX_DESCRIPTOR_BSSID_ADDR 8
247+#define WF_RX_DESCRIPTOR_BSSID_MASK 0x0000003f // 5- 0
248+#define WF_RX_DESCRIPTOR_BSSID_SHIFT 0
249+#define WF_RX_DESCRIPTOR_H_DW 2
250+#define WF_RX_DESCRIPTOR_H_ADDR 8
251+#define WF_RX_DESCRIPTOR_H_MASK 0x00000080 // 7- 7
252+#define WF_RX_DESCRIPTOR_H_SHIFT 7
253+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_DW 2
254+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_ADDR 8
255+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_MASK 0x00001f00 // 12- 8
256+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_SHIFT 8
257+#define WF_RX_DESCRIPTOR_HO_DW 2
258+#define WF_RX_DESCRIPTOR_HO_ADDR 8
259+#define WF_RX_DESCRIPTOR_HO_MASK 0x0000e000 // 15-13
260+#define WF_RX_DESCRIPTOR_HO_SHIFT 13
261+#define WF_RX_DESCRIPTOR_SEC_MODE_DW 2
262+#define WF_RX_DESCRIPTOR_SEC_MODE_ADDR 8
263+#define WF_RX_DESCRIPTOR_SEC_MODE_MASK 0x001f0000 // 20-16
264+#define WF_RX_DESCRIPTOR_SEC_MODE_SHIFT 16
265+#define WF_RX_DESCRIPTOR_MUBAR_DW 2
266+#define WF_RX_DESCRIPTOR_MUBAR_ADDR 8
267+#define WF_RX_DESCRIPTOR_MUBAR_MASK 0x00200000 // 21-21
268+#define WF_RX_DESCRIPTOR_MUBAR_SHIFT 21
269+#define WF_RX_DESCRIPTOR_SWBIT_DW 2
270+#define WF_RX_DESCRIPTOR_SWBIT_ADDR 8
271+#define WF_RX_DESCRIPTOR_SWBIT_MASK 0x00400000 // 22-22
272+#define WF_RX_DESCRIPTOR_SWBIT_SHIFT 22
273+#define WF_RX_DESCRIPTOR_DAF_DW 2
274+#define WF_RX_DESCRIPTOR_DAF_ADDR 8
275+#define WF_RX_DESCRIPTOR_DAF_MASK 0x00800000 // 23-23
276+#define WF_RX_DESCRIPTOR_DAF_SHIFT 23
277+#define WF_RX_DESCRIPTOR_EL_DW 2
278+#define WF_RX_DESCRIPTOR_EL_ADDR 8
279+#define WF_RX_DESCRIPTOR_EL_MASK 0x01000000 // 24-24
280+#define WF_RX_DESCRIPTOR_EL_SHIFT 24
281+#define WF_RX_DESCRIPTOR_HTF_DW 2
282+#define WF_RX_DESCRIPTOR_HTF_ADDR 8
283+#define WF_RX_DESCRIPTOR_HTF_MASK 0x02000000 // 25-25
284+#define WF_RX_DESCRIPTOR_HTF_SHIFT 25
285+#define WF_RX_DESCRIPTOR_INTF_DW 2
286+#define WF_RX_DESCRIPTOR_INTF_ADDR 8
287+#define WF_RX_DESCRIPTOR_INTF_MASK 0x04000000 // 26-26
288+#define WF_RX_DESCRIPTOR_INTF_SHIFT 26
289+#define WF_RX_DESCRIPTOR_FRAG_DW 2
290+#define WF_RX_DESCRIPTOR_FRAG_ADDR 8
291+#define WF_RX_DESCRIPTOR_FRAG_MASK 0x08000000 // 27-27
292+#define WF_RX_DESCRIPTOR_FRAG_SHIFT 27
293+#define WF_RX_DESCRIPTOR_NUL_DW 2
294+#define WF_RX_DESCRIPTOR_NUL_ADDR 8
295+#define WF_RX_DESCRIPTOR_NUL_MASK 0x10000000 // 28-28
296+#define WF_RX_DESCRIPTOR_NUL_SHIFT 28
297+#define WF_RX_DESCRIPTOR_NDATA_DW 2
298+#define WF_RX_DESCRIPTOR_NDATA_ADDR 8
299+#define WF_RX_DESCRIPTOR_NDATA_MASK 0x20000000 // 29-29
300+#define WF_RX_DESCRIPTOR_NDATA_SHIFT 29
301+#define WF_RX_DESCRIPTOR_NAMP_DW 2
302+#define WF_RX_DESCRIPTOR_NAMP_ADDR 8
303+#define WF_RX_DESCRIPTOR_NAMP_MASK 0x40000000 // 30-30
304+#define WF_RX_DESCRIPTOR_NAMP_SHIFT 30
305+#define WF_RX_DESCRIPTOR_BF_RPT_DW 2
306+#define WF_RX_DESCRIPTOR_BF_RPT_ADDR 8
307+#define WF_RX_DESCRIPTOR_BF_RPT_MASK 0x80000000 // 31-31
308+#define WF_RX_DESCRIPTOR_BF_RPT_SHIFT 31
309+// DW3
310+#define WF_RX_DESCRIPTOR_RXV_SN_DW 3
311+#define WF_RX_DESCRIPTOR_RXV_SN_ADDR 12
312+#define WF_RX_DESCRIPTOR_RXV_SN_MASK 0x000000ff // 7- 0
313+#define WF_RX_DESCRIPTOR_RXV_SN_SHIFT 0
314+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_DW 3
315+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_ADDR 12
316+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_MASK 0x0000ff00 // 15- 8
317+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_SHIFT 8
318+#define WF_RX_DESCRIPTOR_A1_TYPE_DW 3
319+#define WF_RX_DESCRIPTOR_A1_TYPE_ADDR 12
320+#define WF_RX_DESCRIPTOR_A1_TYPE_MASK 0x00030000 // 17-16
321+#define WF_RX_DESCRIPTOR_A1_TYPE_SHIFT 16
322+#define WF_RX_DESCRIPTOR_HTC_DW 3
323+#define WF_RX_DESCRIPTOR_HTC_ADDR 12
324+#define WF_RX_DESCRIPTOR_HTC_MASK 0x00040000 // 18-18
325+#define WF_RX_DESCRIPTOR_HTC_SHIFT 18
326+#define WF_RX_DESCRIPTOR_TCL_DW 3
327+#define WF_RX_DESCRIPTOR_TCL_ADDR 12
328+#define WF_RX_DESCRIPTOR_TCL_MASK 0x00080000 // 19-19
329+#define WF_RX_DESCRIPTOR_TCL_SHIFT 19
330+#define WF_RX_DESCRIPTOR_BBM_DW 3
331+#define WF_RX_DESCRIPTOR_BBM_ADDR 12
332+#define WF_RX_DESCRIPTOR_BBM_MASK 0x00100000 // 20-20
333+#define WF_RX_DESCRIPTOR_BBM_SHIFT 20
334+#define WF_RX_DESCRIPTOR_BU_DW 3
335+#define WF_RX_DESCRIPTOR_BU_ADDR 12
336+#define WF_RX_DESCRIPTOR_BU_MASK 0x00200000 // 21-21
337+#define WF_RX_DESCRIPTOR_BU_SHIFT 21
338+#define WF_RX_DESCRIPTOR_CO_ANT_DW 3
339+#define WF_RX_DESCRIPTOR_CO_ANT_ADDR 12
340+#define WF_RX_DESCRIPTOR_CO_ANT_MASK 0x00400000 // 22-22
341+#define WF_RX_DESCRIPTOR_CO_ANT_SHIFT 22
342+#define WF_RX_DESCRIPTOR_BF_CQI_DW 3
343+#define WF_RX_DESCRIPTOR_BF_CQI_ADDR 12
344+#define WF_RX_DESCRIPTOR_BF_CQI_MASK 0x00800000 // 23-23
345+#define WF_RX_DESCRIPTOR_BF_CQI_SHIFT 23
346+#define WF_RX_DESCRIPTOR_FC_DW 3
347+#define WF_RX_DESCRIPTOR_FC_ADDR 12
348+#define WF_RX_DESCRIPTOR_FC_MASK 0x01000000 // 24-24
349+#define WF_RX_DESCRIPTOR_FC_SHIFT 24
350+#define WF_RX_DESCRIPTOR_VLAN_DW 3
351+#define WF_RX_DESCRIPTOR_VLAN_ADDR 12
352+#define WF_RX_DESCRIPTOR_VLAN_MASK 0x80000000 // 31-31
353+#define WF_RX_DESCRIPTOR_VLAN_SHIFT 31
354+// DW4
355+#define WF_RX_DESCRIPTOR_PF_DW 4
356+#define WF_RX_DESCRIPTOR_PF_ADDR 16
357+#define WF_RX_DESCRIPTOR_PF_MASK 0x00000003 // 1- 0
358+#define WF_RX_DESCRIPTOR_PF_SHIFT 0
359+#define WF_RX_DESCRIPTOR_MAC_DW 4
360+#define WF_RX_DESCRIPTOR_MAC_ADDR 16
361+#define WF_RX_DESCRIPTOR_MAC_MASK 0x00000004 // 2- 2
362+#define WF_RX_DESCRIPTOR_MAC_SHIFT 2
363+#define WF_RX_DESCRIPTOR_TID_DW 4
364+#define WF_RX_DESCRIPTOR_TID_ADDR 16
365+#define WF_RX_DESCRIPTOR_TID_MASK 0x00000078 // 6- 3
366+#define WF_RX_DESCRIPTOR_TID_SHIFT 3
367+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 4
368+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 16
369+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x00003f80 // 13- 7
370+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 7
371+#define WF_RX_DESCRIPTOR_IP_DW 4
372+#define WF_RX_DESCRIPTOR_IP_ADDR 16
373+#define WF_RX_DESCRIPTOR_IP_MASK 0x00004000 // 14-14
374+#define WF_RX_DESCRIPTOR_IP_SHIFT 14
375+#define WF_RX_DESCRIPTOR_UT_DW 4
376+#define WF_RX_DESCRIPTOR_UT_ADDR 16
377+#define WF_RX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15
378+#define WF_RX_DESCRIPTOR_UT_SHIFT 15
379+#define WF_RX_DESCRIPTOR_PSE_FID_DW 4
380+#define WF_RX_DESCRIPTOR_PSE_FID_ADDR 16
381+#define WF_RX_DESCRIPTOR_PSE_FID_MASK 0x0fff0000 // 27-16
382+#define WF_RX_DESCRIPTOR_PSE_FID_SHIFT 16
383+// DW5
384+// DW6
385+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__DW 6
386+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__ADDR 24
387+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__MASK 0xffffffff // 31- 0
388+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__SHIFT 0
389+// DW7
390+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__DW 7
391+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__ADDR 28
392+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__MASK 0x00000003 // 1- 0
393+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__SHIFT 0
394+#define WF_RX_DESCRIPTOR_DP_DW 7
395+#define WF_RX_DESCRIPTOR_DP_ADDR 28
396+#define WF_RX_DESCRIPTOR_DP_MASK 0x00080000 // 19-19
397+#define WF_RX_DESCRIPTOR_DP_SHIFT 19
398+#define WF_RX_DESCRIPTOR_CLS_DW 7
399+#define WF_RX_DESCRIPTOR_CLS_ADDR 28
400+#define WF_RX_DESCRIPTOR_CLS_MASK 0x00100000 // 20-20
401+#define WF_RX_DESCRIPTOR_CLS_SHIFT 20
402+#define WF_RX_DESCRIPTOR_OFLD_DW 7
403+#define WF_RX_DESCRIPTOR_OFLD_ADDR 28
404+#define WF_RX_DESCRIPTOR_OFLD_MASK 0x00600000 // 22-21
405+#define WF_RX_DESCRIPTOR_OFLD_SHIFT 21
406+#define WF_RX_DESCRIPTOR_MGC_DW 7
407+#define WF_RX_DESCRIPTOR_MGC_ADDR 28
408+#define WF_RX_DESCRIPTOR_MGC_MASK 0x00800000 // 23-23
409+#define WF_RX_DESCRIPTOR_MGC_SHIFT 23
410+#define WF_RX_DESCRIPTOR_WOL_DW 7
411+#define WF_RX_DESCRIPTOR_WOL_ADDR 28
412+#define WF_RX_DESCRIPTOR_WOL_MASK 0x1f000000 // 28-24
413+#define WF_RX_DESCRIPTOR_WOL_SHIFT 24
414+#define WF_RX_DESCRIPTOR_PF_MODE_DW 7
415+#define WF_RX_DESCRIPTOR_PF_MODE_ADDR 28
416+#define WF_RX_DESCRIPTOR_PF_MODE_MASK 0x20000000 // 29-29
417+#define WF_RX_DESCRIPTOR_PF_MODE_SHIFT 29
418+#define WF_RX_DESCRIPTOR_PF_STS_DW 7
419+#define WF_RX_DESCRIPTOR_PF_STS_ADDR 28
420+#define WF_RX_DESCRIPTOR_PF_STS_MASK 0xc0000000 // 31-30
421+#define WF_RX_DESCRIPTOR_PF_STS_SHIFT 30
422+// DW8
423+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_DW 8
424+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_ADDR 32
425+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_MASK 0x0000ffff // 15- 0
426+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_SHIFT 0
427+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__DW 8
428+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__ADDR 32
429+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__MASK 0xffff0000 // 31-16
430+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__SHIFT 16
431+// DW9
432+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__DW 9
433+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__ADDR 36
434+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__MASK 0xffffffff // 31- 0
435+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__SHIFT 0
436+// DW10
437+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_DW 10
438+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_ADDR 40
439+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_MASK 0x0000000f // 3- 0
440+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_SHIFT 0
441+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_DW 10
442+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_ADDR 40
443+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_MASK 0x0000fff0 // 15- 4
444+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_SHIFT 4
445+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_DW 10
446+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_ADDR 40
447+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_MASK 0xffff0000 // 31-16
448+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_SHIFT 16
449+// DW11
450+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_DW 11
451+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_ADDR 44
452+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_MASK 0xffffffff // 31- 0
453+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_SHIFT 0
454+// DW12
455+#define WF_RX_DESCRIPTOR_PN_31_0__DW 12
456+#define WF_RX_DESCRIPTOR_PN_31_0__ADDR 48
457+#define WF_RX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0
458+#define WF_RX_DESCRIPTOR_PN_31_0__SHIFT 0
459+// DW13
460+#define WF_RX_DESCRIPTOR_PN_63_32__DW 13
461+#define WF_RX_DESCRIPTOR_PN_63_32__ADDR 52
462+#define WF_RX_DESCRIPTOR_PN_63_32__MASK 0xffffffff // 31- 0
463+#define WF_RX_DESCRIPTOR_PN_63_32__SHIFT 0
464+// DW14
465+#define WF_RX_DESCRIPTOR_PN_95_64__DW 14
466+#define WF_RX_DESCRIPTOR_PN_95_64__ADDR 56
467+#define WF_RX_DESCRIPTOR_PN_95_64__MASK 0xffffffff // 31- 0
468+#define WF_RX_DESCRIPTOR_PN_95_64__SHIFT 0
469+// DW15
470+#define WF_RX_DESCRIPTOR_PN_127_96__DW 15
471+#define WF_RX_DESCRIPTOR_PN_127_96__ADDR 60
472+#define WF_RX_DESCRIPTOR_PN_127_96__MASK 0xffffffff // 31- 0
473+#define WF_RX_DESCRIPTOR_PN_127_96__SHIFT 0
474+// DW16
475+#define WF_RX_DESCRIPTOR_TIMESTAMP_DW 16
476+#define WF_RX_DESCRIPTOR_TIMESTAMP_ADDR 64
477+#define WF_RX_DESCRIPTOR_TIMESTAMP_MASK 0xffffffff // 31- 0
478+#define WF_RX_DESCRIPTOR_TIMESTAMP_SHIFT 0
479+// DW17
480+#define WF_RX_DESCRIPTOR_CRC_DW 17
481+#define WF_RX_DESCRIPTOR_CRC_ADDR 68
482+#define WF_RX_DESCRIPTOR_CRC_MASK 0xffffffff // 31- 0
483+#define WF_RX_DESCRIPTOR_CRC_SHIFT 0
484+// DW18
485+// DW19
486+// DW20
487+#define WF_RX_DESCRIPTOR_P_RXV_DW 20
488+#define WF_RX_DESCRIPTOR_P_RXV_ADDR 80
489+#define WF_RX_DESCRIPTOR_P_RXV_MASK 0xffffffff // 31- 0
490+#define WF_RX_DESCRIPTOR_P_RXV_SHIFT 0
491+// DW21
492+// DO NOT process repeat field(p_rxv)
493+// DW22
494+#define WF_RX_DESCRIPTOR_DBW_DW 22
495+#define WF_RX_DESCRIPTOR_DBW_ADDR 88
496+#define WF_RX_DESCRIPTOR_DBW_MASK 0x00000007 // 2- 0
497+#define WF_RX_DESCRIPTOR_DBW_SHIFT 0
498+#define WF_RX_DESCRIPTOR_GI_DW 22
499+#define WF_RX_DESCRIPTOR_GI_ADDR 88
500+#define WF_RX_DESCRIPTOR_GI_MASK 0x00000018 // 4- 3
501+#define WF_RX_DESCRIPTOR_GI_SHIFT 3
502+#define WF_RX_DESCRIPTOR_DCM_DW 22
503+#define WF_RX_DESCRIPTOR_DCM_ADDR 88
504+#define WF_RX_DESCRIPTOR_DCM_MASK 0x00000020 // 5- 5
505+#define WF_RX_DESCRIPTOR_DCM_SHIFT 5
506+#define WF_RX_DESCRIPTOR_NUM_RX_DW 22
507+#define WF_RX_DESCRIPTOR_NUM_RX_ADDR 88
508+#define WF_RX_DESCRIPTOR_NUM_RX_MASK 0x000001c0 // 8- 6
509+#define WF_RX_DESCRIPTOR_NUM_RX_SHIFT 6
510+#define WF_RX_DESCRIPTOR_STBC_DW 22
511+#define WF_RX_DESCRIPTOR_STBC_ADDR 88
512+#define WF_RX_DESCRIPTOR_STBC_MASK 0x00000600 // 10- 9
513+#define WF_RX_DESCRIPTOR_STBC_SHIFT 9
514+#define WF_RX_DESCRIPTOR_TX_MODE_DW 22
515+#define WF_RX_DESCRIPTOR_TX_MODE_ADDR 88
516+#define WF_RX_DESCRIPTOR_TX_MODE_MASK 0x00007800 // 14-11
517+#define WF_RX_DESCRIPTOR_TX_MODE_SHIFT 11
518+// DW23
519+#define WF_RX_DESCRIPTOR_RCPI_DW 23
520+#define WF_RX_DESCRIPTOR_RCPI_ADDR 92
521+#define WF_RX_DESCRIPTOR_RCPI_MASK 0xffffffff // 31- 0
522+#define WF_RX_DESCRIPTOR_RCPI_SHIFT 0
523+// DW24
524+#define WF_RX_DESCRIPTOR_C_RXV_DW 24
525+#define WF_RX_DESCRIPTOR_C_RXV_ADDR 96
526+#define WF_RX_DESCRIPTOR_C_RXV_MASK 0xffffffff // 31- 0
527+#define WF_RX_DESCRIPTOR_C_RXV_SHIFT 0
528+// DW25
529+// DO NOT process repeat field(c_rxv)
530+// DW26
531+// DO NOT process repeat field(c_rxv)
532+// DW27
533+// DO NOT process repeat field(c_rxv)
534+// DW28
535+// DO NOT process repeat field(c_rxv)
536+// DW29
537+// DO NOT process repeat field(c_rxv)
538+// DW30
539+// DO NOT process repeat field(c_rxv)
540+// DW31
541+// DO NOT process repeat field(c_rxv)
542+// DW32
543+// DO NOT process repeat field(c_rxv)
544+// DW33
545+// DO NOT process repeat field(c_rxv)
546+// DW34
547+// DO NOT process repeat field(c_rxv)
548+// DW35
549+// DO NOT process repeat field(c_rxv)
550+// DW36
551+// DO NOT process repeat field(c_rxv)
552+// DW37
553+// DO NOT process repeat field(c_rxv)
554+// DW38
555+// DO NOT process repeat field(c_rxv)
556+// DW39
557+// DO NOT process repeat field(c_rxv)
558+// DW40
559+// DO NOT process repeat field(c_rxv)
560+// DW41
561+// DO NOT process repeat field(c_rxv)
562+// DW42
563+// DO NOT process repeat field(c_rxv)
564+// DW43
565+// DO NOT process repeat field(c_rxv)
566+// DW44
567+// DO NOT process repeat field(c_rxv)
568+// DW45
569+// DO NOT process repeat field(c_rxv)
570+// DW46
571+// DW47
572+
573+/* TXD */
574+// DW0
575+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_DW 0
576+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_ADDR 0
577+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_MASK 0x0000ffff // 15- 0
578+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_SHIFT 0
579+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 0
580+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 0
581+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x007f0000 // 22-16
582+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 16
583+#define WF_TX_DESCRIPTOR_PKT_FT_DW 0
584+#define WF_TX_DESCRIPTOR_PKT_FT_ADDR 0
585+#define WF_TX_DESCRIPTOR_PKT_FT_MASK 0x01800000 // 24-23
586+#define WF_TX_DESCRIPTOR_PKT_FT_SHIFT 23
587+#define WF_TX_DESCRIPTOR_Q_IDX_DW 0
588+#define WF_TX_DESCRIPTOR_Q_IDX_ADDR 0
589+#define WF_TX_DESCRIPTOR_Q_IDX_MASK 0xfe000000 // 31-25
590+#define WF_TX_DESCRIPTOR_Q_IDX_SHIFT 25
591+// DW1
592+#define WF_TX_DESCRIPTOR_MLD_ID_DW 1
593+#define WF_TX_DESCRIPTOR_MLD_ID_ADDR 4
594+#define WF_TX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0
595+#define WF_TX_DESCRIPTOR_MLD_ID_SHIFT 0
596+#define WF_TX_DESCRIPTOR_TGID_DW 1
597+#define WF_TX_DESCRIPTOR_TGID_ADDR 4
598+#define WF_TX_DESCRIPTOR_TGID_MASK 0x00003000 // 13-12
599+#define WF_TX_DESCRIPTOR_TGID_SHIFT 12
600+#define WF_TX_DESCRIPTOR_HF_DW 1
601+#define WF_TX_DESCRIPTOR_HF_ADDR 4
602+#define WF_TX_DESCRIPTOR_HF_MASK 0x0000c000 // 15-14
603+#define WF_TX_DESCRIPTOR_HF_SHIFT 14
604+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_DW 1
605+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_ADDR 4
606+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_MASK 0x001f0000 // 20-16
607+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_SHIFT 16
608+#define WF_TX_DESCRIPTOR_MRD_DW 1
609+#define WF_TX_DESCRIPTOR_MRD_ADDR 4
610+#define WF_TX_DESCRIPTOR_MRD_MASK 0x00010000 // 16-16
611+#define WF_TX_DESCRIPTOR_MRD_SHIFT 16
612+#define WF_TX_DESCRIPTOR_EOSP_DW 1
613+#define WF_TX_DESCRIPTOR_EOSP_ADDR 4
614+#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17
615+#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17
616+#define WF_TX_DESCRIPTOR_EOSP_DW 1
617+#define WF_TX_DESCRIPTOR_EOSP_ADDR 4
618+#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17
619+#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17
620+#define WF_TX_DESCRIPTOR_AMS_DW 1
621+#define WF_TX_DESCRIPTOR_AMS_ADDR 4
622+#define WF_TX_DESCRIPTOR_AMS_MASK 0x00040000 // 18-18
623+#define WF_TX_DESCRIPTOR_AMS_SHIFT 18
624+#define WF_TX_DESCRIPTOR_RMVL_DW 1
625+#define WF_TX_DESCRIPTOR_RMVL_ADDR 4
626+#define WF_TX_DESCRIPTOR_RMVL_MASK 0x00040000 // 18-18
627+#define WF_TX_DESCRIPTOR_RMVL_SHIFT 18
628+#define WF_TX_DESCRIPTOR_VLAN_DW 1
629+#define WF_TX_DESCRIPTOR_VLAN_ADDR 4
630+#define WF_TX_DESCRIPTOR_VLAN_MASK 0x00080000 // 19-19
631+#define WF_TX_DESCRIPTOR_VLAN_SHIFT 19
632+#define WF_TX_DESCRIPTOR_ETYP_DW 1
633+#define WF_TX_DESCRIPTOR_ETYP_ADDR 4
634+#define WF_TX_DESCRIPTOR_ETYP_MASK 0x00100000 // 20-20
635+#define WF_TX_DESCRIPTOR_ETYP_SHIFT 20
636+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_DW 1
637+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_ADDR 4
638+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_MASK 0x01e00000 // 24-21
639+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_SHIFT 21
640+#define WF_TX_DESCRIPTOR_OM_DW 1
641+#define WF_TX_DESCRIPTOR_OM_ADDR 4
642+#define WF_TX_DESCRIPTOR_OM_MASK 0x7e000000 // 30-25
643+#define WF_TX_DESCRIPTOR_OM_SHIFT 25
644+#define WF_TX_DESCRIPTOR_FR_DW 1
645+#define WF_TX_DESCRIPTOR_FR_ADDR 4
646+#define WF_TX_DESCRIPTOR_FR_MASK 0x80000000 // 31-31
647+#define WF_TX_DESCRIPTOR_FR_SHIFT 31
648+// DW2
649+#define WF_TX_DESCRIPTOR_SUBTYPE_DW 2
650+#define WF_TX_DESCRIPTOR_SUBTYPE_ADDR 8
651+#define WF_TX_DESCRIPTOR_SUBTYPE_MASK 0x0000000f // 3- 0
652+#define WF_TX_DESCRIPTOR_SUBTYPE_SHIFT 0
653+#define WF_TX_DESCRIPTOR_FTYPE_DW 2
654+#define WF_TX_DESCRIPTOR_FTYPE_ADDR 8
655+#define WF_TX_DESCRIPTOR_FTYPE_MASK 0x00000030 // 5- 4
656+#define WF_TX_DESCRIPTOR_FTYPE_SHIFT 4
657+#define WF_TX_DESCRIPTOR_BF_TYPE_DW 2
658+#define WF_TX_DESCRIPTOR_BF_TYPE_ADDR 8
659+#define WF_TX_DESCRIPTOR_BF_TYPE_MASK 0x000000c0 // 7- 6
660+#define WF_TX_DESCRIPTOR_BF_TYPE_SHIFT 6
661+#define WF_TX_DESCRIPTOR_OM_MAP_DW 2
662+#define WF_TX_DESCRIPTOR_OM_MAP_ADDR 8
663+#define WF_TX_DESCRIPTOR_OM_MAP_MASK 0x00000100 // 8- 8
664+#define WF_TX_DESCRIPTOR_OM_MAP_SHIFT 8
665+#define WF_TX_DESCRIPTOR_RTS_DW 2
666+#define WF_TX_DESCRIPTOR_RTS_ADDR 8
667+#define WF_TX_DESCRIPTOR_RTS_MASK 0x00000200 // 9- 9
668+#define WF_TX_DESCRIPTOR_RTS_SHIFT 9
669+#define WF_TX_DESCRIPTOR_HEADER_PADDING_DW 2
670+#define WF_TX_DESCRIPTOR_HEADER_PADDING_ADDR 8
671+#define WF_TX_DESCRIPTOR_HEADER_PADDING_MASK 0x00000c00 // 11-10
672+#define WF_TX_DESCRIPTOR_HEADER_PADDING_SHIFT 10
673+#define WF_TX_DESCRIPTOR_DU_DW 2
674+#define WF_TX_DESCRIPTOR_DU_ADDR 8
675+#define WF_TX_DESCRIPTOR_DU_MASK 0x00001000 // 12-12
676+#define WF_TX_DESCRIPTOR_DU_SHIFT 12
677+#define WF_TX_DESCRIPTOR_HE_DW 2
678+#define WF_TX_DESCRIPTOR_HE_ADDR 8
679+#define WF_TX_DESCRIPTOR_HE_MASK 0x00002000 // 13-13
680+#define WF_TX_DESCRIPTOR_HE_SHIFT 13
681+#define WF_TX_DESCRIPTOR_FRAG_DW 2
682+#define WF_TX_DESCRIPTOR_FRAG_ADDR 8
683+#define WF_TX_DESCRIPTOR_FRAG_MASK 0x0000c000 // 15-14
684+#define WF_TX_DESCRIPTOR_FRAG_SHIFT 14
685+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_DW 2
686+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_ADDR 8
687+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_MASK 0x03ff0000 // 25-16
688+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_SHIFT 16
689+#define WF_TX_DESCRIPTOR_POWER_OFFSET_DW 2
690+#define WF_TX_DESCRIPTOR_POWER_OFFSET_ADDR 8
691+#define WF_TX_DESCRIPTOR_POWER_OFFSET_MASK 0xfc000000 // 31-26
692+#define WF_TX_DESCRIPTOR_POWER_OFFSET_SHIFT 26
693+// DW3
694+#define WF_TX_DESCRIPTOR_NA_DW 3
695+#define WF_TX_DESCRIPTOR_NA_ADDR 12
696+#define WF_TX_DESCRIPTOR_NA_MASK 0x00000001 // 0- 0
697+#define WF_TX_DESCRIPTOR_NA_SHIFT 0
698+#define WF_TX_DESCRIPTOR_PF_DW 3
699+#define WF_TX_DESCRIPTOR_PF_ADDR 12
700+#define WF_TX_DESCRIPTOR_PF_MASK 0x00000002 // 1- 1
701+#define WF_TX_DESCRIPTOR_PF_SHIFT 1
702+#define WF_TX_DESCRIPTOR_EMRD_DW 3
703+#define WF_TX_DESCRIPTOR_EMRD_ADDR 12
704+#define WF_TX_DESCRIPTOR_EMRD_MASK 0x00000004 // 2- 2
705+#define WF_TX_DESCRIPTOR_EMRD_SHIFT 2
706+#define WF_TX_DESCRIPTOR_EEOSP_DW 3
707+#define WF_TX_DESCRIPTOR_EEOSP_ADDR 12
708+#define WF_TX_DESCRIPTOR_EEOSP_MASK 0x00000008 // 3- 3
709+#define WF_TX_DESCRIPTOR_EEOSP_SHIFT 3
710+#define WF_TX_DESCRIPTOR_BM_DW 3
711+#define WF_TX_DESCRIPTOR_BM_ADDR 12
712+#define WF_TX_DESCRIPTOR_BM_MASK 0x00000010 // 4- 4
713+#define WF_TX_DESCRIPTOR_BM_SHIFT 4
714+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_DW 3
715+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_ADDR 12
716+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_MASK 0x00000020 // 5- 5
717+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_SHIFT 5
718+#define WF_TX_DESCRIPTOR_TX_COUNT_DW 3
719+#define WF_TX_DESCRIPTOR_TX_COUNT_ADDR 12
720+#define WF_TX_DESCRIPTOR_TX_COUNT_MASK 0x000007c0 // 10- 6
721+#define WF_TX_DESCRIPTOR_TX_COUNT_SHIFT 6
722+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_DW 3
723+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_ADDR 12
724+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_MASK 0x0000f800 // 15-11
725+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_SHIFT 11
726+#define WF_TX_DESCRIPTOR_SN_DW 3
727+#define WF_TX_DESCRIPTOR_SN_ADDR 12
728+#define WF_TX_DESCRIPTOR_SN_MASK 0x0fff0000 // 27-16
729+#define WF_TX_DESCRIPTOR_SN_SHIFT 16
730+#define WF_TX_DESCRIPTOR_BA_DIS_DW 3
731+#define WF_TX_DESCRIPTOR_BA_DIS_ADDR 12
732+#define WF_TX_DESCRIPTOR_BA_DIS_MASK 0x10000000 // 28-28
733+#define WF_TX_DESCRIPTOR_BA_DIS_SHIFT 28
734+#define WF_TX_DESCRIPTOR_PM_DW 3
735+#define WF_TX_DESCRIPTOR_PM_ADDR 12
736+#define WF_TX_DESCRIPTOR_PM_MASK 0x20000000 // 29-29
737+#define WF_TX_DESCRIPTOR_PM_SHIFT 29
738+#define WF_TX_DESCRIPTOR_PN_VLD_DW 3
739+#define WF_TX_DESCRIPTOR_PN_VLD_ADDR 12
740+#define WF_TX_DESCRIPTOR_PN_VLD_MASK 0x40000000 // 30-30
741+#define WF_TX_DESCRIPTOR_PN_VLD_SHIFT 30
742+#define WF_TX_DESCRIPTOR_SN_VLD_DW 3
743+#define WF_TX_DESCRIPTOR_SN_VLD_ADDR 12
744+#define WF_TX_DESCRIPTOR_SN_VLD_MASK 0x80000000 // 31-31
745+#define WF_TX_DESCRIPTOR_SN_VLD_SHIFT 31
746+// DW4
747+#define WF_TX_DESCRIPTOR_PN_31_0__DW 4
748+#define WF_TX_DESCRIPTOR_PN_31_0__ADDR 16
749+#define WF_TX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0
750+#define WF_TX_DESCRIPTOR_PN_31_0__SHIFT 0
751+// DW5
752+#define WF_TX_DESCRIPTOR_PID_DW 5
753+#define WF_TX_DESCRIPTOR_PID_ADDR 20
754+#define WF_TX_DESCRIPTOR_PID_MASK 0x000000ff // 7- 0
755+#define WF_TX_DESCRIPTOR_PID_SHIFT 0
756+#define WF_TX_DESCRIPTOR_TXSFM_DW 5
757+#define WF_TX_DESCRIPTOR_TXSFM_ADDR 20
758+#define WF_TX_DESCRIPTOR_TXSFM_MASK 0x00000100 // 8- 8
759+#define WF_TX_DESCRIPTOR_TXSFM_SHIFT 8
760+#define WF_TX_DESCRIPTOR_TXS2M_DW 5
761+#define WF_TX_DESCRIPTOR_TXS2M_ADDR 20
762+#define WF_TX_DESCRIPTOR_TXS2M_MASK 0x00000200 // 9- 9
763+#define WF_TX_DESCRIPTOR_TXS2M_SHIFT 9
764+#define WF_TX_DESCRIPTOR_TXS2H_DW 5
765+#define WF_TX_DESCRIPTOR_TXS2H_ADDR 20
766+#define WF_TX_DESCRIPTOR_TXS2H_MASK 0x00000400 // 10-10
767+#define WF_TX_DESCRIPTOR_TXS2H_SHIFT 10
768+#define WF_TX_DESCRIPTOR_FBCZ_DW 5
769+#define WF_TX_DESCRIPTOR_FBCZ_ADDR 20
770+#define WF_TX_DESCRIPTOR_FBCZ_MASK 0x00001000 // 12-12
771+#define WF_TX_DESCRIPTOR_FBCZ_SHIFT 12
772+#define WF_TX_DESCRIPTOR_BYPASS_RBB_DW 5
773+#define WF_TX_DESCRIPTOR_BYPASS_RBB_ADDR 20
774+#define WF_TX_DESCRIPTOR_BYPASS_RBB_MASK 0x00002000 // 13-13
775+#define WF_TX_DESCRIPTOR_BYPASS_RBB_SHIFT 13
776+#define WF_TX_DESCRIPTOR_BYPASS_TBB_DW 5
777+#define WF_TX_DESCRIPTOR_BYPASS_TBB_ADDR 20
778+#define WF_TX_DESCRIPTOR_BYPASS_TBB_MASK 0x00004000 // 14-14
779+#define WF_TX_DESCRIPTOR_BYPASS_TBB_SHIFT 14
780+#define WF_TX_DESCRIPTOR_FL_DW 5
781+#define WF_TX_DESCRIPTOR_FL_ADDR 20
782+#define WF_TX_DESCRIPTOR_FL_MASK 0x00008000 // 15-15
783+#define WF_TX_DESCRIPTOR_FL_SHIFT 15
784+#define WF_TX_DESCRIPTOR_PN_47_32__DW 5
785+#define WF_TX_DESCRIPTOR_PN_47_32__ADDR 20
786+#define WF_TX_DESCRIPTOR_PN_47_32__MASK 0xffff0000 // 31-16
787+#define WF_TX_DESCRIPTOR_PN_47_32__SHIFT 16
788+// DW6
789+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_DW 6
790+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_ADDR 24
791+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_MASK 0x00000002 // 1- 1
792+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_SHIFT 1
793+#define WF_TX_DESCRIPTOR_DAS_DW 6
794+#define WF_TX_DESCRIPTOR_DAS_ADDR 24
795+#define WF_TX_DESCRIPTOR_DAS_MASK 0x00000004 // 2- 2
796+#define WF_TX_DESCRIPTOR_DAS_SHIFT 2
797+#define WF_TX_DESCRIPTOR_DIS_MAT_DW 6
798+#define WF_TX_DESCRIPTOR_DIS_MAT_ADDR 24
799+#define WF_TX_DESCRIPTOR_DIS_MAT_MASK 0x00000008 // 3- 3
800+#define WF_TX_DESCRIPTOR_DIS_MAT_SHIFT 3
801+#define WF_TX_DESCRIPTOR_MSDU_COUNT_DW 6
802+#define WF_TX_DESCRIPTOR_MSDU_COUNT_ADDR 24
803+#define WF_TX_DESCRIPTOR_MSDU_COUNT_MASK 0x000003f0 // 9- 4
804+#define WF_TX_DESCRIPTOR_MSDU_COUNT_SHIFT 4
805+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_DW 6
806+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_ADDR 24
807+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_MASK 0x00007c00 // 14-10
808+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_SHIFT 10
809+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_DW 6
810+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_ADDR 24
811+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_MASK 0x00008000 // 15-15
812+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_SHIFT 15
813+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_DW 6
814+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_ADDR 24
815+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_MASK 0x003f0000 // 21-16
816+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_SHIFT 16
817+#define WF_TX_DESCRIPTOR_BW_DW 6
818+#define WF_TX_DESCRIPTOR_BW_ADDR 24
819+#define WF_TX_DESCRIPTOR_BW_MASK 0x03c00000 // 25-22
820+#define WF_TX_DESCRIPTOR_BW_SHIFT 22
821+#define WF_TX_DESCRIPTOR_VTA_DW 6
822+#define WF_TX_DESCRIPTOR_VTA_ADDR 24
823+#define WF_TX_DESCRIPTOR_VTA_MASK 0x10000000 // 28-28
824+#define WF_TX_DESCRIPTOR_VTA_SHIFT 28
825+#define WF_TX_DESCRIPTOR_SRC_DW 6
826+#define WF_TX_DESCRIPTOR_SRC_ADDR 24
827+#define WF_TX_DESCRIPTOR_SRC_MASK 0xc0000000 // 31-30
828+#define WF_TX_DESCRIPTOR_SRC_SHIFT 30
829+// DW7
830+#define WF_TX_DESCRIPTOR_SW_TX_TIME_DW 7
831+#define WF_TX_DESCRIPTOR_SW_TX_TIME_ADDR 28
832+#define WF_TX_DESCRIPTOR_SW_TX_TIME_MASK 0x000003ff // 9- 0
833+#define WF_TX_DESCRIPTOR_SW_TX_TIME_SHIFT 0
834+#define WF_TX_DESCRIPTOR_UT_DW 7
835+#define WF_TX_DESCRIPTOR_UT_ADDR 28
836+#define WF_TX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15
837+#define WF_TX_DESCRIPTOR_UT_SHIFT 15
838+#define WF_TX_DESCRIPTOR_CTXD_CNT_DW 7
839+#define WF_TX_DESCRIPTOR_CTXD_CNT_ADDR 28
840+#define WF_TX_DESCRIPTOR_CTXD_CNT_MASK 0x03c00000 // 25-22
841+#define WF_TX_DESCRIPTOR_CTXD_CNT_SHIFT 22
842+#define WF_TX_DESCRIPTOR_CTXD_DW 7
843+#define WF_TX_DESCRIPTOR_CTXD_ADDR 28
844+#define WF_TX_DESCRIPTOR_CTXD_MASK 0x04000000 // 26-26
845+#define WF_TX_DESCRIPTOR_CTXD_SHIFT 26
846+#define WF_TX_DESCRIPTOR_HM_DW 7
847+#define WF_TX_DESCRIPTOR_HM_ADDR 28
848+#define WF_TX_DESCRIPTOR_HM_MASK 0x08000000 // 27-27
849+#define WF_TX_DESCRIPTOR_HM_SHIFT 27
850+#define WF_TX_DESCRIPTOR_DP_DW 7
851+#define WF_TX_DESCRIPTOR_DP_ADDR 28
852+#define WF_TX_DESCRIPTOR_DP_MASK 0x10000000 // 28-28
853+#define WF_TX_DESCRIPTOR_DP_SHIFT 28
854+#define WF_TX_DESCRIPTOR_IP_DW 7
855+#define WF_TX_DESCRIPTOR_IP_ADDR 28
856+#define WF_TX_DESCRIPTOR_IP_MASK 0x20000000 // 29-29
857+#define WF_TX_DESCRIPTOR_IP_SHIFT 29
858+#define WF_TX_DESCRIPTOR_TXD_LEN_DW 7
859+#define WF_TX_DESCRIPTOR_TXD_LEN_ADDR 28
860+#define WF_TX_DESCRIPTOR_TXD_LEN_MASK 0xc0000000 // 31-30
861+#define WF_TX_DESCRIPTOR_TXD_LEN_SHIFT 30
862+// DW8
863+#define WF_TX_DESCRIPTOR_MSDU0_DW 8
864+#define WF_TX_DESCRIPTOR_MSDU0_ADDR 32
865+#define WF_TX_DESCRIPTOR_MSDU0_MASK 0x0000ffff // 15- 0
866+#define WF_TX_DESCRIPTOR_MSDU0_SHIFT 0
867+#define WF_TX_DESCRIPTOR_MSDU1_DW 8
868+#define WF_TX_DESCRIPTOR_MSDU1_ADDR 32
869+#define WF_TX_DESCRIPTOR_MSDU1_MASK 0xffff0000 // 31-16
870+#define WF_TX_DESCRIPTOR_MSDU1_SHIFT 16
871+// DW9
872+#define WF_TX_DESCRIPTOR_MSDU2_DW 9
873+#define WF_TX_DESCRIPTOR_MSDU2_ADDR 36
874+#define WF_TX_DESCRIPTOR_MSDU2_MASK 0x0000ffff // 15- 0
875+#define WF_TX_DESCRIPTOR_MSDU2_SHIFT 0
876+#define WF_TX_DESCRIPTOR_MSDU3_DW 9
877+#define WF_TX_DESCRIPTOR_MSDU3_ADDR 36
878+#define WF_TX_DESCRIPTOR_MSDU3_MASK 0xffff0000 // 31-16
879+#define WF_TX_DESCRIPTOR_MSDU3_SHIFT 16
880+// DW10
881+#define WF_TX_DESCRIPTOR_TXP0_DW 10
882+#define WF_TX_DESCRIPTOR_TXP0_ADDR 40
883+#define WF_TX_DESCRIPTOR_TXP0_MASK 0xffffffff // 31- 0
884+#define WF_TX_DESCRIPTOR_TXP0_SHIFT 0
885+// DW11
886+// DO NOT process repeat field(txp[0])
887+#define WF_TX_DESCRIPTOR_TXP1_DW 11
888+#define WF_TX_DESCRIPTOR_TXP1_ADDR 44
889+#define WF_TX_DESCRIPTOR_TXP1_MASK 0xffff0000 // 31-16
890+#define WF_TX_DESCRIPTOR_TXP1_SHIFT 16
891+// DW12
892+// DO NOT process repeat field(txp[1])
893+// DW13
894+#define WF_TX_DESCRIPTOR_TXP2_DW 13
895+#define WF_TX_DESCRIPTOR_TXP2_ADDR 52
896+#define WF_TX_DESCRIPTOR_TXP2_MASK 0xffffffff // 31- 0
897+#define WF_TX_DESCRIPTOR_TXP2_SHIFT 0
898+// DW14
899+// DO NOT process repeat field(txp[2])
900+#define WF_TX_DESCRIPTOR_TXP3_DW 14
901+#define WF_TX_DESCRIPTOR_TXP3_ADDR 56
902+#define WF_TX_DESCRIPTOR_TXP3_MASK 0xffff0000 // 31-16
903+#define WF_TX_DESCRIPTOR_TXP3_SHIFT 16
904+// DW15
905+// DO NOT process repeat field(txp[3])
906+// DW16
907+#define WF_TX_DESCRIPTOR_MSDU4_DW 16
908+#define WF_TX_DESCRIPTOR_MSDU4_ADDR 64
909+#define WF_TX_DESCRIPTOR_MSDU4_MASK 0x0000ffff // 15- 0
910+#define WF_TX_DESCRIPTOR_MSDU4_SHIFT 0
911+#define WF_TX_DESCRIPTOR_MSDU5_DW 16
912+#define WF_TX_DESCRIPTOR_MSDU5_ADDR 64
913+#define WF_TX_DESCRIPTOR_MSDU5_MASK 0xffff0000 // 31-16
914+#define WF_TX_DESCRIPTOR_MSDU5_SHIFT 16
915+// DW17
916+#define WF_TX_DESCRIPTOR_MSDU6_DW 17
917+#define WF_TX_DESCRIPTOR_MSDU6_ADDR 68
918+#define WF_TX_DESCRIPTOR_MSDU6_MASK 0x0000ffff // 15- 0
919+#define WF_TX_DESCRIPTOR_MSDU6_SHIFT 0
920+#define WF_TX_DESCRIPTOR_MSDU7_DW 17
921+#define WF_TX_DESCRIPTOR_MSDU7_ADDR 68
922+#define WF_TX_DESCRIPTOR_MSDU7_MASK 0xffff0000 // 31-16
923+#define WF_TX_DESCRIPTOR_MSDU7_SHIFT 16
924+// DW18
925+#define WF_TX_DESCRIPTOR_TXP4_DW 18
926+#define WF_TX_DESCRIPTOR_TXP4_ADDR 72
927+#define WF_TX_DESCRIPTOR_TXP4_MASK 0xffffffff // 31- 0
928+#define WF_TX_DESCRIPTOR_TXP4_SHIFT 0
929+// DW19
930+// DO NOT process repeat field(txp[4])
931+#define WF_TX_DESCRIPTOR_TXP5_DW 19
932+#define WF_TX_DESCRIPTOR_TXP5_ADDR 76
933+#define WF_TX_DESCRIPTOR_TXP5_MASK 0xffff0000 // 31-16
934+#define WF_TX_DESCRIPTOR_TXP5_SHIFT 16
935+// DW20
936+// DO NOT process repeat field(txp[5])
937+// DW21
938+#define WF_TX_DESCRIPTOR_TXP6_DW 21
939+#define WF_TX_DESCRIPTOR_TXP6_ADDR 84
940+#define WF_TX_DESCRIPTOR_TXP6_MASK 0xffffffff // 31- 0
941+#define WF_TX_DESCRIPTOR_TXP6_SHIFT 0
942+// DW22
943+// DO NOT process repeat field(txp[6])
944+#define WF_TX_DESCRIPTOR_TXP7_DW 22
945+#define WF_TX_DESCRIPTOR_TXP7_ADDR 88
946+#define WF_TX_DESCRIPTOR_TXP7_MASK 0xffff0000 // 31-16
947+#define WF_TX_DESCRIPTOR_TXP7_SHIFT 16
948+// DW23
949+// DO NOT process repeat field(txp[7])
950+// DW24
951+#define WF_TX_DESCRIPTOR_TXP8_DW 24
952+#define WF_TX_DESCRIPTOR_TXP8_ADDR 96
953+#define WF_TX_DESCRIPTOR_TXP8_MASK 0xffffffff // 31- 0
954+#define WF_TX_DESCRIPTOR_TXP8_SHIFT 0
955+// DW25
956+// DO NOT process repeat field(txp[8])
957+#define WF_TX_DESCRIPTOR_TXP9_DW 25
958+#define WF_TX_DESCRIPTOR_TXP9_ADDR 100
959+#define WF_TX_DESCRIPTOR_TXP9_MASK 0xffff0000 // 31-16
960+#define WF_TX_DESCRIPTOR_TXP9_SHIFT 16
961+// DW26
962+// DO NOT process repeat field(txp[9])
963+// DW27
964+#define WF_TX_DESCRIPTOR_TXP10_DW 27
965+#define WF_TX_DESCRIPTOR_TXP10_ADDR 108
966+#define WF_TX_DESCRIPTOR_TXP10_MASK 0xffffffff // 31- 0
967+#define WF_TX_DESCRIPTOR_TXP10_SHIFT 0
968+// DW28
969+// DO NOT process repeat field(txp[10])
970+#define WF_TX_DESCRIPTOR_TXP11_DW 28
971+#define WF_TX_DESCRIPTOR_TXP11_ADDR 112
972+#define WF_TX_DESCRIPTOR_TXP11_MASK 0xffff0000 // 31-16
973+#define WF_TX_DESCRIPTOR_TXP11_SHIFT 16
974+// DW29
975+// DO NOT process repeat field(txp[11])
976+// DW30
977+#define WF_TX_DESCRIPTOR_TXP12_DW 30
978+#define WF_TX_DESCRIPTOR_TXP12_ADDR 120
979+#define WF_TX_DESCRIPTOR_TXP12_MASK 0xffffffff // 31- 0
980+#define WF_TX_DESCRIPTOR_TXP12_SHIFT 0
981+// DW31
982+// DO NOT process repeat field(txp[12])
983+#define WF_TX_DESCRIPTOR_TXP13_DW 31
984+#define WF_TX_DESCRIPTOR_TXP13_ADDR 124
985+#define WF_TX_DESCRIPTOR_TXP13_MASK 0xffff0000 // 31-16
986+#define WF_TX_DESCRIPTOR_TXP13_SHIFT 16
987+// DW32
988+// DO NOT process repeat field(txp[13])
989+// DW33
990+#define WF_TX_DESCRIPTOR_TXP14_DW 33
991+#define WF_TX_DESCRIPTOR_TXP14_ADDR 132
992+#define WF_TX_DESCRIPTOR_TXP14_MASK 0xffffffff // 31- 0
993+#define WF_TX_DESCRIPTOR_TXP14_SHIFT 0
994+// DW34
995+// DO NOT process repeat field(txp[14])
996+#define WF_TX_DESCRIPTOR_TXP15_DW 34
997+#define WF_TX_DESCRIPTOR_TXP15_ADDR 136
998+#define WF_TX_DESCRIPTOR_TXP15_MASK 0xffff0000 // 31-16
999+#define WF_TX_DESCRIPTOR_TXP15_SHIFT 16
1000+// DW35
1001+// DO NOT process repeat field(txp[15])
1002+// DW36
1003+#define WF_TX_DESCRIPTOR_TXP16_DW 36
1004+#define WF_TX_DESCRIPTOR_TXP16_ADDR 144
1005+#define WF_TX_DESCRIPTOR_TXP16_MASK 0xffffffff // 31- 0
1006+#define WF_TX_DESCRIPTOR_TXP16_SHIFT 0
1007+// DW37
1008+// DO NOT process repeat field(txp[16])
1009+#define WF_TX_DESCRIPTOR_TXP17_DW 37
1010+#define WF_TX_DESCRIPTOR_TXP17_ADDR 148
1011+#define WF_TX_DESCRIPTOR_TXP17_MASK 0xffff0000 // 31-16
1012+#define WF_TX_DESCRIPTOR_TXP17_SHIFT 16
1013+// DW38
1014+// DO NOT process repeat field(txp[17])
1015+// DW39
1016+#define WF_TX_DESCRIPTOR_TXP18_DW 39
1017+#define WF_TX_DESCRIPTOR_TXP18_ADDR 156
1018+#define WF_TX_DESCRIPTOR_TXP18_MASK 0xffffffff // 31- 0
1019+#define WF_TX_DESCRIPTOR_TXP18_SHIFT 0
1020+// DW40
1021+// DO NOT process repeat field(txp[18])
1022+#define WF_TX_DESCRIPTOR_TXP19_DW 40
1023+#define WF_TX_DESCRIPTOR_TXP19_ADDR 160
1024+#define WF_TX_DESCRIPTOR_TXP19_MASK 0xffff0000 // 31-16
1025+#define WF_TX_DESCRIPTOR_TXP19_SHIFT 16
1026+// DW41
1027+// DO NOT process repeat field(txp[19])
1028+// DW42
1029+#define WF_TX_DESCRIPTOR_TXP20_DW 42
1030+#define WF_TX_DESCRIPTOR_TXP20_ADDR 168
1031+#define WF_TX_DESCRIPTOR_TXP20_MASK 0xffffffff // 31- 0
1032+#define WF_TX_DESCRIPTOR_TXP20_SHIFT 0
1033+// DW43
1034+// DO NOT process repeat field(txp[20])
1035+#define WF_TX_DESCRIPTOR_TXP21_DW 43
1036+#define WF_TX_DESCRIPTOR_TXP21_ADDR 172
1037+#define WF_TX_DESCRIPTOR_TXP21_MASK 0xffff0000 // 31-16
1038+#define WF_TX_DESCRIPTOR_TXP21_SHIFT 16
1039+// DW44
1040+// DO NOT process repeat field(txp[21])
1041+// DW45
1042+#define WF_TX_DESCRIPTOR_TXP22_DW 45
1043+#define WF_TX_DESCRIPTOR_TXP22_ADDR 180
1044+#define WF_TX_DESCRIPTOR_TXP22_MASK 0xffffffff // 31- 0
1045+#define WF_TX_DESCRIPTOR_TXP22_SHIFT 0
1046+// DW46
1047+// DO NOT process repeat field(txp[22])
1048+#define WF_TX_DESCRIPTOR_TXP23_DW 46
1049+#define WF_TX_DESCRIPTOR_TXP23_ADDR 184
1050+#define WF_TX_DESCRIPTOR_TXP23_MASK 0xffff0000 // 31-16
1051+#define WF_TX_DESCRIPTOR_TXP23_SHIFT 16
1052+// DW47
1053+// DO NOT process repeat field(txp[23])
1054+// DW48
1055+#define WF_TX_DESCRIPTOR_TXP24_DW 48
1056+#define WF_TX_DESCRIPTOR_TXP24_ADDR 192
1057+#define WF_TX_DESCRIPTOR_TXP24_MASK 0xffffffff // 31- 0
1058+#define WF_TX_DESCRIPTOR_TXP24_SHIFT 0
1059+// DW49
1060+// DO NOT process repeat field(txp[24])
1061+#define WF_TX_DESCRIPTOR_TXP25_DW 49
1062+#define WF_TX_DESCRIPTOR_TXP25_ADDR 196
1063+#define WF_TX_DESCRIPTOR_TXP25_MASK 0xffff0000 // 31-16
1064+#define WF_TX_DESCRIPTOR_TXP25_SHIFT 16
1065+// DW50
1066+// DO NOT process repeat field(txp[25])
1067+// DW51
1068+#define WF_TX_DESCRIPTOR_TXP26_DW 51
1069+#define WF_TX_DESCRIPTOR_TXP26_ADDR 204
1070+#define WF_TX_DESCRIPTOR_TXP26_MASK 0xffffffff // 31- 0
1071+#define WF_TX_DESCRIPTOR_TXP26_SHIFT 0
1072+// DW52
1073+// DO NOT process repeat field(txp[26])
1074+#define WF_TX_DESCRIPTOR_TXP27_DW 52
1075+#define WF_TX_DESCRIPTOR_TXP27_ADDR 208
1076+#define WF_TX_DESCRIPTOR_TXP27_MASK 0xffff0000 // 31-16
1077+#define WF_TX_DESCRIPTOR_TXP27_SHIFT 16
1078+// DW53
1079+// DO NOT process repeat field(txp[27])
1080+// DW54
1081+#define WF_TX_DESCRIPTOR_TXP28_DW 54
1082+#define WF_TX_DESCRIPTOR_TXP28_ADDR 216
1083+#define WF_TX_DESCRIPTOR_TXP28_MASK 0xffffffff // 31- 0
1084+#define WF_TX_DESCRIPTOR_TXP28_SHIFT 0
1085+// DW55
1086+// DO NOT process repeat field(txp[28])
1087+#define WF_TX_DESCRIPTOR_TXP29_DW 55
1088+#define WF_TX_DESCRIPTOR_TXP29_ADDR 220
1089+#define WF_TX_DESCRIPTOR_TXP29_MASK 0xffff0000 // 31-16
1090+#define WF_TX_DESCRIPTOR_TXP29_SHIFT 16
1091+// DW56
1092+// DO NOT process repeat field(txp[29])
1093+// DW57
1094+#define WF_TX_DESCRIPTOR_TXP30_DW 57
1095+#define WF_TX_DESCRIPTOR_TXP30_ADDR 228
1096+#define WF_TX_DESCRIPTOR_TXP30_MASK 0xffffffff // 31- 0
1097+#define WF_TX_DESCRIPTOR_TXP30_SHIFT 0
1098+// DW58
1099+// DO NOT process repeat field(txp[30])
1100+#define WF_TX_DESCRIPTOR_TXP31_DW 58
1101+#define WF_TX_DESCRIPTOR_TXP31_ADDR 232
1102+#define WF_TX_DESCRIPTOR_TXP31_MASK 0xffff0000 // 31-16
1103+#define WF_TX_DESCRIPTOR_TXP31_SHIFT 16
1104+// DW59
1105+// DO NOT process repeat field(txp[31])
1106+
1107+/* TXP PAO */
1108+#define HIF_TXP_V2_SIZE (24 * 4)
1109+/* DW0 */
1110+#define HIF_TXD_VERSION_SHIFT 19
1111+#define HIF_TXD_VERSION_MASK 0x00780000
1112+
1113+/* DW8 */
1114+#define HIF_TXP_PRIORITY_SHIFT 0
1115+#define HIF_TXP_PRIORITY_MASK 0x00000001
1116+#define HIF_TXP_FIXED_RATE_SHIFT 1
1117+#define HIF_TXP_FIXED_RATE_MASK 0x00000002
1118+#define HIF_TXP_TCP_SHIFT 2
1119+#define HIF_TXP_TCP_MASK 0x00000004
1120+#define HIF_TXP_NON_CIPHER_SHIFT 3
1121+#define HIF_TXP_NON_CIPHER_MASK 0x00000008
1122+#define HIF_TXP_VLAN_SHIFT 4
1123+#define HIF_TXP_VLAN_MASK 0x00000010
1124+#define HIF_TXP_BC_MC_FLAG_SHIFT 5
1125+#define HIF_TXP_BC_MC_FLAG_MASK 0x00000060
1126+#define HIF_TXP_FR_HOST_SHIFT 7
1127+#define HIF_TXP_FR_HOST_MASK 0x00000080
1128+#define HIF_TXP_ETYPE_SHIFT 8
1129+#define HIF_TXP_ETYPE_MASK 0x00000100
1130+#define HIF_TXP_TXP_AMSDU_SHIFT 9
1131+#define HIF_TXP_TXP_AMSDU_MASK 0x00000200
1132+#define HIF_TXP_TXP_MC_CLONE_SHIFT 10
1133+#define HIF_TXP_TXP_MC_CLONE_MASK 0x00000400
1134+#define HIF_TXP_TOKEN_ID_SHIFT 16
1135+#define HIF_TXP_TOKEN_ID_MASK 0xffff0000
1136+
1137+/* DW9 */
1138+#define HIF_TXP_BSS_IDX_SHIFT 0
1139+#define HIF_TXP_BSS_IDX_MASK 0x000000ff
1140+#define HIF_TXP_USER_PRIORITY_SHIFT 8
1141+#define HIF_TXP_USER_PRIORITY_MASK 0x0000ff00
1142+#define HIF_TXP_BUF_NUM_SHIFT 16
1143+#define HIF_TXP_BUF_NUM_MASK 0x001f0000
1144+#define HIF_TXP_MSDU_CNT_SHIFT 21
1145+#define HIF_TXP_MSDU_CNT_MASK 0x03e00000
1146+#define HIF_TXP_SRC_SHIFT 26
1147+#define HIF_TXP_SRC_MASK 0x0c000000
1148+
1149+/* DW10 */
1150+#define HIF_TXP_ETH_TYPE_SHIFT 0
1151+#define HIF_TXP_ETH_TYPE_MASK 0x0000ffff
1152+#define HIF_TXP_WLAN_IDX_SHIFT 16
1153+#define HIF_TXP_WLAN_IDX_MASK 0x0fff0000
1154+
1155+/* DW11 */
1156+#define HIF_TXP_PPE_INFO_SHIFT 0
1157+#define HIF_TXP_PPE_INFO_MASK 0xffffffff
1158+
1159+/* DW12 - DW31 */
1160+#define HIF_TXP_BUF_PTR0_L_SHIFT 0
1161+#define HIF_TXP_BUF_PTR0_L_MASK 0xffffffff
1162+#define HIF_TXP_BUF_LEN0_SHIFT 0
1163+#define HIF_TXP_BUF_LEN0_MASK 0x00000fff
1164+#define HIF_TXP_BUF_PTR0_H_SHIFT 12
1165+#define HIF_TXP_BUF_PTR0_H_MASK 0x0000f000
1166+#define HIF_TXP_BUF_LEN1_SHIFT 16
1167+#define HIF_TXP_BUF_LEN1_MASK 0x0fff0000
1168+#define HIF_TXP_BUF_PTR1_H_SHIFT 28
1169+#define HIF_TXP_BUF_PTR1_H_MASK 0xf0000000
1170+#define HIF_TXP_BUF_PTR1_L_SHIFT 0
1171+#define HIF_TXP_BUF_PTR1_L_MASK 0xffffffff
1172+
1173+/* DW31 */
1174+#define HIF_TXP_ML_SHIFT 16
1175+#define HIF_TXP_ML_MASK 0xffff0000
1176+
1177+#endif
1178+
1179+#endif
1180diff --git a/mt7996/mtk_debugfs_i.c b/mt7996/mtk_debugfs_i.c
1181new file mode 100644
1182index 00000000..ea412cd5
1183--- /dev/null
1184+++ b/mt7996/mtk_debugfs_i.c
1185@@ -0,0 +1,720 @@
1186+#include <linux/inet.h>
1187+#include "mt7996.h"
1188+#include "../mt76.h"
1189+#include "mcu.h"
1190+#include "mac.h"
1191+#include "eeprom.h"
1192+#include "mtk_debug.h"
1193+#include "mtk_debug_i.h"
1194+#include "mtk_mcu.h"
1195+
1196+#ifdef CONFIG_MTK_DEBUG
1197+
1198+#define info_or_seq_printf(seq, fmt, ...) do { \
1199+ if (seq) \
1200+ seq_printf(seq, fmt, ##__VA_ARGS__); \
1201+ else \
1202+ pr_info(fmt, ##__VA_ARGS__); \
1203+} while (0)
1204+
1205+static void info_or_seq_hex_dump(struct seq_file *seq, int prefix_type,
1206+ int rowsize, int groupsize, const void *buf,
1207+ size_t len, bool ascii)
1208+{
1209+ if (seq)
1210+ seq_hex_dump(seq, "", prefix_type, rowsize, groupsize,
1211+ buf, len, ascii);
1212+ else
1213+ print_hex_dump(KERN_INFO, "", prefix_type,
1214+ rowsize, groupsize, buf, len, ascii);
1215+}
1216+
1217+//bmac dump mac txp
1218+static void mt7996_dump_bmac_mac_txp_info(struct seq_file *s, struct mt7996_dev *dev,
1219+ __le32 *txp)
1220+{
1221+ struct mt7996_txp_token {
1222+ __le16 msdu[4];
1223+ } *msdu;
1224+ struct mt7996_txp_ptr {
1225+ __le32 addr1;
1226+ __le32 addr_info;
1227+ __le32 addr2;
1228+ } *ptr;
1229+ int i = 0;
1230+
1231+ for (i = 0; i < 12; i = i+2 ) {
1232+ if (i == 0 || i == 4) {
1233+ msdu = (struct mt7996_txp_token *) txp;
1234+ info_or_seq_printf(s, "msdu token(%d-%d)=%ld %ld %ld %ld (0x%08x-0x%08x)\n", i, i+3,
1235+ (msdu->msdu[0] & GENMASK(14, 0)),
1236+ (msdu->msdu[1] & GENMASK(14, 0)),
1237+ (msdu->msdu[2] & GENMASK(14, 0)),
1238+ (msdu->msdu[3] & GENMASK(14, 0)), *txp, *(txp+1));
1239+ txp = txp + 2;
1240+ }
1241+ ptr = (struct mt7996_txp_ptr *) txp;
1242+ info_or_seq_printf(s, "ptr%02d : addr(0x%08x) len(%ld) addr_h(%02lx) SRC(%d) ML(%d) \n",
1243+ i, ptr->addr1,
1244+ FIELD_GET(GENMASK(11, 0), ptr->addr_info),
1245+ FIELD_GET(GENMASK(13, 12), ptr->addr_info),
1246+ !!(ptr->addr_info & BIT(14)),
1247+ !!(ptr->addr_info & BIT(15)));
1248+ info_or_seq_printf(s, "ptr%02d : addr(0x%08x) len(%ld) addr_h(%02lx) SRC(%d) ML(%d) \n",
1249+ i+1, ptr->addr2,
1250+ FIELD_GET(GENMASK(27, 16), ptr->addr_info),
1251+ FIELD_GET(GENMASK(29, 28), ptr->addr_info),
1252+ !!(ptr->addr_info & BIT(30)),
1253+ !!(ptr->addr_info & BIT(31)));
1254+ txp = txp + 3;
1255+ }
1256+}
1257+
1258+//bmac dump hif txp
1259+void mt7996_dump_bmac_hif_txp_info(struct seq_file *s, struct mt7996_dev *dev,
1260+ __le32 *txp, u32 hif_txp_ver)
1261+{
1262+ int i, j = 0;
1263+ u32 dw;
1264+
1265+ info_or_seq_printf(s, "txp raw data: size=%d\n", HIF_TXP_V2_SIZE);
1266+ info_or_seq_hex_dump(s, DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txp, HIF_TXP_V2_SIZE, false);
1267+
1268+ info_or_seq_printf(s, "BMAC_TXP Fields:\n");
1269+
1270+ /* dw0 */
1271+ if (hif_txp_ver == 2) {
1272+ dw = le32_to_cpu(txp[0]);
1273+ info_or_seq_printf(s, "HIF_TXP_PRIORITY = %d\n",
1274+ GET_FIELD(HIF_TXP_PRIORITY, dw));
1275+ info_or_seq_printf(s, "HIF_TXP_FIXED_RATE = %d\n",
1276+ GET_FIELD(HIF_TXP_FIXED_RATE, dw));
1277+ info_or_seq_printf(s, "HIF_TXP_TCP = %d\n",
1278+ GET_FIELD(HIF_TXP_TCP, dw));
1279+ info_or_seq_printf(s, "HIF_TXP_NON_CIPHER = %d\n",
1280+ GET_FIELD(HIF_TXP_NON_CIPHER, dw));
1281+ info_or_seq_printf(s, "HIF_TXP_VLAN = %d\n",
1282+ GET_FIELD(HIF_TXP_VLAN, dw));
1283+ info_or_seq_printf(s, "HIF_TXP_BC_MC_FLAG = %d\n",
1284+ GET_FIELD(HIF_TXP_BC_MC_FLAG, dw));
1285+ info_or_seq_printf(s, "HIF_TXP_FR_HOST = %d\n",
1286+ GET_FIELD(HIF_TXP_FR_HOST, dw));
1287+ info_or_seq_printf(s, "HIF_TXP_ETYPE = %d\n",
1288+ GET_FIELD(HIF_TXP_ETYPE, dw));
1289+ info_or_seq_printf(s, "HIF_TXP_TXP_AMSDU = %d\n",
1290+ GET_FIELD(HIF_TXP_TXP_AMSDU, dw));
1291+ info_or_seq_printf(s, "HIF_TXP_TXP_MC_CLONE = %d\n",
1292+ GET_FIELD(HIF_TXP_TXP_MC_CLONE, dw));
1293+ info_or_seq_printf(s, "HIF_TXP_TOKEN_ID = %d\n",
1294+ GET_FIELD(HIF_TXP_TOKEN_ID, dw));
1295+
1296+ /* dw1 */
1297+ dw = le32_to_cpu(txp[1]);
1298+ info_or_seq_printf(s, "HIF_TXP_BSS_IDX = %d\n",
1299+ GET_FIELD(HIF_TXP_BSS_IDX, dw));
1300+ info_or_seq_printf(s, "HIF_TXP_USER_PRIORITY = %d\n",
1301+ GET_FIELD(HIF_TXP_USER_PRIORITY, dw));
1302+ info_or_seq_printf(s, "HIF_TXP_BUF_NUM = %d\n",
1303+ GET_FIELD(HIF_TXP_BUF_NUM, dw));
1304+ info_or_seq_printf(s, "HIF_TXP_MSDU_CNT = %d\n",
1305+ GET_FIELD(HIF_TXP_MSDU_CNT, dw));
1306+ info_or_seq_printf(s, "HIF_TXP_SRC = %d\n",
1307+ GET_FIELD(HIF_TXP_SRC, dw));
1308+
1309+ /* dw2 */
1310+ dw = le32_to_cpu(txp[2]);
1311+ info_or_seq_printf(s, "HIF_TXP_ETH_TYPE(network-endian) = 0x%x\n",
1312+ GET_FIELD(HIF_TXP_ETH_TYPE, dw));
1313+ info_or_seq_printf(s, "HIF_TXP_WLAN_IDX = %d\n",
1314+ GET_FIELD(HIF_TXP_WLAN_IDX, dw));
1315+
1316+ /* dw3 */
1317+ dw = le32_to_cpu(txp[3]);
1318+ info_or_seq_printf(s, "HIF_TXP_PPE_INFO = 0x%x\n",
1319+ GET_FIELD(HIF_TXP_PPE_INFO, dw));
1320+
1321+ for (i = 0; i < 13; i++) {
1322+ if (i % 2 == 0) {
1323+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_L = 0x%x\n",
1324+ i, GET_FIELD(HIF_TXP_BUF_PTR0_L,
1325+ le32_to_cpu(txp[4 + j])));
1326+ j++;
1327+ info_or_seq_printf(s, "HIF_TXP_BUF_LEN%d = %d\n",
1328+ i, GET_FIELD(HIF_TXP_BUF_LEN0, le32_to_cpu(txp[4 + j])));
1329+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_H = 0x%x\n",
1330+ i, GET_FIELD(HIF_TXP_BUF_PTR0_H, le32_to_cpu(txp[4 + j])));
1331+ if (i <= 10) {
1332+ info_or_seq_printf(s, "HIF_TXP_BUF_LEN%d = %d\n",
1333+ i + 1, GET_FIELD(HIF_TXP_BUF_LEN1, le32_to_cpu(txp[4 + j])));
1334+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_H = 0x%x\n",
1335+ i + 1, GET_FIELD(HIF_TXP_BUF_PTR1_H, le32_to_cpu(txp[4 + j])));
1336+ }
1337+ j++;
1338+ } else {
1339+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_L = 0x%x\n",
1340+ i, GET_FIELD(HIF_TXP_BUF_PTR1_L,
1341+ le32_to_cpu(txp[4 + j])));
1342+ j++;
1343+ }
1344+ }
1345+
1346+ info_or_seq_printf(s, "ml = 0x%x\n",
1347+ GET_FIELD(HIF_TXP_ML, le32_to_cpu(txp[23])));
1348+ } else {
1349+ struct mt76_connac_txp_common *txp_v1 = (struct mt76_connac_txp_common *)txp;
1350+
1351+ info_or_seq_printf(s, "FLAGS = (%04x)\n", txp_v1->fw.flags);
1352+
1353+ info_or_seq_printf(s, "MSDU = %d\n", txp_v1->fw.token);
1354+
1355+ info_or_seq_printf(s, "BSS_IDX = %d\n", txp_v1->fw.bss_idx);
1356+
1357+ info_or_seq_printf(s, "WCID = %d\n",txp_v1->fw.rept_wds_wcid);
1358+
1359+ info_or_seq_printf(s, "MSDU_CNT = %d\n", txp_v1->fw.nbuf);
1360+
1361+ for (i = 0; i < MT_TXP_MAX_BUF_NUM; i++)
1362+ info_or_seq_printf(s, "ptr%02d : addr(0x%08x) len(%d)\n", i, le32_to_cpu(txp_v1->fw.buf[i]),
1363+ le16_to_cpu(txp_v1->fw.len[i]));
1364+ }
1365+}
1366+
1367+/* bmac txd dump */
1368+void mt7996_dump_bmac_txd_info(struct seq_file *s, struct mt7996_dev *dev,
1369+ __le32 *txd, bool is_hif_txd, bool dump_txp)
1370+{
1371+ u32 hif_txp_ver = 0;
1372+
1373+ /* dump stop */
1374+ if (!dev->dbg.txd_read_cnt)
1375+ return;
1376+
1377+ /* force dump */
1378+ if (dev->dbg.txd_read_cnt > 8)
1379+ dev->dbg.txd_read_cnt = 8;
1380+
1381+ /* dump txd_read_cnt times */
1382+ if (dev->dbg.txd_read_cnt != 8)
1383+ dev->dbg.txd_read_cnt--;
1384+
1385+ info_or_seq_printf(s, "txd raw data: size=%d\n", MT_TXD_SIZE);
1386+ info_or_seq_hex_dump(s, DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txd, MT_TXD_SIZE, false);
1387+
1388+ info_or_seq_printf(s, "BMAC_TXD Fields:\n");
1389+ /* dw0 */
1390+ if (is_hif_txd) {
1391+ hif_txp_ver = FIELD_GET(GENMASK(22, 19), txd[0]);
1392+ info_or_seq_printf(s, "HIF TXD VER = %d\n", hif_txp_ver);
1393+ }
1394+ info_or_seq_printf(s, "TX_BYTE_COUNT = %d\n",
1395+ GET_FIELD(WF_TX_DESCRIPTOR_TX_BYTE_COUNT, txd[0]));
1396+ info_or_seq_printf(s, "ETHER_TYPE_OFFSET(word) = %d\n",
1397+ GET_FIELD(WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET, txd[0]));
1398+ info_or_seq_printf(s, "PKT_FT = %d%s%s%s%s\n",
1399+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]),
1400+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 0 ? "(ct)" : "",
1401+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 1 ? "(s&f)" : "",
1402+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 2 ? "(cmd)" : "",
1403+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 3 ? "(redirect)" : "");
1404+ info_or_seq_printf(s, "Q_IDX = %d%s%s%s\n",
1405+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]),
1406+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x10 ? "(ALTX)" : "",
1407+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x11 ? "(BMC)" : "",
1408+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x12 ? "(BCN)" : "");
1409+
1410+ /* dw1 */
1411+ info_or_seq_printf(s, "MLD_ID = %d\n",
1412+ GET_FIELD(WF_TX_DESCRIPTOR_MLD_ID, txd[1]));
1413+ info_or_seq_printf(s, "TGID = %d\n",
1414+ GET_FIELD(WF_TX_DESCRIPTOR_TGID, txd[1]));
1415+ info_or_seq_printf(s, "HF = %d%s%s%s%s\n",
1416+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]),
1417+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? "(eth/802.3)" : "",
1418+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 1 ? "(cmd)" : "",
1419+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? "(802.11)" : "",
1420+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? "(802.11 enhanced" : "");
1421+ info_or_seq_printf(s, "802.11 HEADER_LENGTH = %d\n",
1422+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ?
1423+ GET_FIELD(WF_TX_DESCRIPTOR_HEADER_LENGTH, txd[1]) : 0);
1424+ info_or_seq_printf(s, "MRD = %d\n",
1425+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1426+ GET_FIELD(WF_TX_DESCRIPTOR_MRD, txd[1]) : 0);
1427+ info_or_seq_printf(s, "EOSP = %d\n",
1428+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1429+ GET_FIELD(WF_TX_DESCRIPTOR_EOSP, txd[1]) : 0);
1430+ info_or_seq_printf(s, "AMS = %d\n",
1431+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ?
1432+ GET_FIELD(WF_TX_DESCRIPTOR_AMS, txd[1]) : 0);
1433+ info_or_seq_printf(s, "RMVL = %d\n",
1434+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1435+ GET_FIELD(WF_TX_DESCRIPTOR_RMVL, txd[1]): 0);
1436+ info_or_seq_printf(s, "VLAN = %d\n",
1437+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1438+ GET_FIELD(WF_TX_DESCRIPTOR_VLAN, txd[1]) : 0);
1439+ info_or_seq_printf(s, "ETYP = %d\n",
1440+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1441+ GET_FIELD(WF_TX_DESCRIPTOR_ETYP, txd[1]) : 0);
1442+ info_or_seq_printf(s, "TID_MGMT_TYPE = %d\n",
1443+ GET_FIELD(WF_TX_DESCRIPTOR_TID_MGMT_TYPE, txd[1]));
1444+ info_or_seq_printf(s, "OM = %d\n",
1445+ GET_FIELD(WF_TX_DESCRIPTOR_OM, txd[1]));
1446+ info_or_seq_printf(s, "FR = %d\n",
1447+ GET_FIELD(WF_TX_DESCRIPTOR_FR, txd[1]));
1448+
1449+ /* dw2 */
1450+ info_or_seq_printf(s, "SUBTYPE = %d%s%s%s%s\n",
1451+ GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]),
1452+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0) &&
1453+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 13) ?
1454+ "(action)" : "",
1455+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1) &&
1456+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 8) ?
1457+ "(bar)" : "",
1458+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) &&
1459+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 4) ?
1460+ "(null)" : "",
1461+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) &&
1462+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 12) ?
1463+ "(qos null)" : "");
1464+
1465+ info_or_seq_printf(s, "FTYPE = %d%s%s%s\n",
1466+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]),
1467+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0 ? "(mgmt)" : "",
1468+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1 ? "(ctl)" : "",
1469+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2 ? "(data)" : "");
1470+ info_or_seq_printf(s, "BF_TYPE = %d\n",
1471+ GET_FIELD(WF_TX_DESCRIPTOR_BF_TYPE, txd[2]));
1472+ info_or_seq_printf(s, "OM_MAP = %d\n",
1473+ GET_FIELD(WF_TX_DESCRIPTOR_OM_MAP, txd[2]));
1474+ info_or_seq_printf(s, "RTS = %d\n",
1475+ GET_FIELD(WF_TX_DESCRIPTOR_RTS, txd[2]));
1476+ info_or_seq_printf(s, "HEADER_PADDING = %d\n",
1477+ GET_FIELD(WF_TX_DESCRIPTOR_HEADER_PADDING, txd[2]));
1478+ info_or_seq_printf(s, "DU = %d\n",
1479+ GET_FIELD(WF_TX_DESCRIPTOR_DU, txd[2]));
1480+ info_or_seq_printf(s, "HE = %d\n",
1481+ GET_FIELD(WF_TX_DESCRIPTOR_HE, txd[2]));
1482+ info_or_seq_printf(s, "FRAG = %d\n",
1483+ GET_FIELD(WF_TX_DESCRIPTOR_FRAG, txd[2]));
1484+ info_or_seq_printf(s, "REMAINING_TX_TIME = %d\n",
1485+ GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_TIME, txd[2]));
1486+ info_or_seq_printf(s, "POWER_OFFSET = %d\n",
1487+ GET_FIELD(WF_TX_DESCRIPTOR_POWER_OFFSET, txd[2]));
1488+
1489+ /* dw3 */
1490+ info_or_seq_printf(s, "NA = %d\n",
1491+ GET_FIELD(WF_TX_DESCRIPTOR_NA, txd[3]));
1492+ info_or_seq_printf(s, "PF = %d\n",
1493+ GET_FIELD(WF_TX_DESCRIPTOR_PF, txd[3]));
1494+ info_or_seq_printf(s, "EMRD = %d\n",
1495+ GET_FIELD(WF_TX_DESCRIPTOR_EMRD, txd[3]));
1496+ info_or_seq_printf(s, "EEOSP = %d\n",
1497+ GET_FIELD(WF_TX_DESCRIPTOR_EEOSP, txd[3]));
1498+ info_or_seq_printf(s, "BM = %d\n",
1499+ GET_FIELD(WF_TX_DESCRIPTOR_BM, txd[3]));
1500+ info_or_seq_printf(s, "HW_AMSDU_CAP = %d\n",
1501+ GET_FIELD(WF_TX_DESCRIPTOR_HW_AMSDU_CAP, txd[3]));
1502+ info_or_seq_printf(s, "TX_COUNT = %d\n",
1503+ GET_FIELD(WF_TX_DESCRIPTOR_TX_COUNT, txd[3]));
1504+ info_or_seq_printf(s, "REMAINING_TX_COUNT = %d\n",
1505+ GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_COUNT, txd[3]));
1506+ info_or_seq_printf(s, "SN = %d\n",
1507+ GET_FIELD(WF_TX_DESCRIPTOR_SN, txd[3]));
1508+ info_or_seq_printf(s, "BA_DIS = %d\n",
1509+ GET_FIELD(WF_TX_DESCRIPTOR_BA_DIS, txd[3]));
1510+ info_or_seq_printf(s, "PM = %d\n",
1511+ GET_FIELD(WF_TX_DESCRIPTOR_PM, txd[3]));
1512+ info_or_seq_printf(s, "PN_VLD = %d\n",
1513+ GET_FIELD(WF_TX_DESCRIPTOR_PN_VLD, txd[3]));
1514+ info_or_seq_printf(s, "SN_VLD = %d\n",
1515+ GET_FIELD(WF_TX_DESCRIPTOR_SN_VLD, txd[3]));
1516+
1517+ /* dw4 */
1518+ info_or_seq_printf(s, "PN_31_0 = 0x%x\n",
1519+ GET_FIELD(WF_TX_DESCRIPTOR_PN_31_0_, txd[4]));
1520+
1521+ /* dw5 */
1522+ info_or_seq_printf(s, "PID = %d\n",
1523+ GET_FIELD(WF_TX_DESCRIPTOR_PID, txd[5]));
1524+ info_or_seq_printf(s, "TXSFM = %d\n",
1525+ GET_FIELD(WF_TX_DESCRIPTOR_TXSFM, txd[5]));
1526+ info_or_seq_printf(s, "TXS2M = %d\n",
1527+ GET_FIELD(WF_TX_DESCRIPTOR_TXS2M, txd[5]));
1528+ info_or_seq_printf(s, "TXS2H = %d\n",
1529+ GET_FIELD(WF_TX_DESCRIPTOR_TXS2H, txd[5]));
1530+ info_or_seq_printf(s, "FBCZ = %d\n",
1531+ GET_FIELD(WF_TX_DESCRIPTOR_FBCZ, txd[5]));
1532+ info_or_seq_printf(s, "BYPASS_RBB = %d\n",
1533+ GET_FIELD(WF_TX_DESCRIPTOR_BYPASS_RBB, txd[5]));
1534+
1535+ info_or_seq_printf(s, "FL = %d\n",
1536+ GET_FIELD(WF_TX_DESCRIPTOR_FL, txd[5]));
1537+ info_or_seq_printf(s, "PN_47_32 = 0x%x\n",
1538+ GET_FIELD(WF_TX_DESCRIPTOR_PN_47_32_, txd[5]));
1539+
1540+ /* dw6 */
1541+ info_or_seq_printf(s, "AMSDU_CAP_UTXB = %d\n",
1542+ GET_FIELD(WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB, txd[6]));
1543+ info_or_seq_printf(s, "DAS = %d\n",
1544+ GET_FIELD(WF_TX_DESCRIPTOR_DAS, txd[6]));
1545+ info_or_seq_printf(s, "DIS_MAT = %d\n",
1546+ GET_FIELD(WF_TX_DESCRIPTOR_DIS_MAT, txd[6]));
1547+ info_or_seq_printf(s, "MSDU_COUNT = %d\n",
1548+ GET_FIELD(WF_TX_DESCRIPTOR_MSDU_COUNT, txd[6]));
1549+ info_or_seq_printf(s, "TIMESTAMP_OFFSET = %d\n",
1550+ GET_FIELD(WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX, txd[6]));
1551+ info_or_seq_printf(s, "FIXED_RATE_IDX = %d\n",
1552+ GET_FIELD(WF_TX_DESCRIPTOR_FIXED_RATE_IDX, txd[6]));
1553+ info_or_seq_printf(s, "BW = %d\n",
1554+ GET_FIELD(WF_TX_DESCRIPTOR_BW, txd[6]));
1555+ info_or_seq_printf(s, "VTA = %d\n",
1556+ GET_FIELD(WF_TX_DESCRIPTOR_VTA, txd[6]));
1557+ info_or_seq_printf(s, "SRC = %d\n",
1558+ GET_FIELD(WF_TX_DESCRIPTOR_SRC, txd[6]));
1559+
1560+ /* dw7 */
1561+ info_or_seq_printf(s, "SW_TX_TIME(unit:65536ns) = %d\n",
1562+ GET_FIELD(WF_TX_DESCRIPTOR_SW_TX_TIME , txd[7]));
1563+ info_or_seq_printf(s, "UT = %d\n",
1564+ GET_FIELD(WF_TX_DESCRIPTOR_UT, txd[7]));
1565+ info_or_seq_printf(s, "CTXD_CNT = %d\n",
1566+ GET_FIELD(WF_TX_DESCRIPTOR_CTXD_CNT, txd[7]));
1567+ info_or_seq_printf(s, "HM = %d\n",
1568+ GET_FIELD(WF_TX_DESCRIPTOR_HM, txd[7]));
1569+ info_or_seq_printf(s, "DP = %d\n",
1570+ GET_FIELD(WF_TX_DESCRIPTOR_DP, txd[7]));
1571+ info_or_seq_printf(s, "IP = %d\n",
1572+ GET_FIELD(WF_TX_DESCRIPTOR_IP, txd[7]));
1573+ info_or_seq_printf(s, "TXD_LEN = %d\n",
1574+ GET_FIELD(WF_TX_DESCRIPTOR_TXD_LEN, txd[7]));
1575+
1576+ if (dump_txp) {
1577+ __le32 *txp = txd + 8;
1578+
1579+ if (is_hif_txd)
1580+ mt7996_dump_bmac_hif_txp_info(s, dev, txp, hif_txp_ver);
1581+ else
1582+ mt7996_dump_bmac_mac_txp_info(s, dev, txp);
1583+ }
1584+}
1585+
1586+static void
1587+mt7996_dump_mac_fid(struct seq_file *s, struct mt7996_dev *dev, u32 fid, bool is_ple)
1588+{
1589+#define PLE_MEM_SIZE 128
1590+#define PSE_MEM_SIZE 256
1591+ u8 data[PSE_MEM_SIZE] = {0};
1592+ u32 addr = 0;
1593+ int i = 0, cr_cnt = PSE_MEM_SIZE;
1594+ u32 *ptr = (u32 *) data;
1595+
1596+ if (is_ple) {
1597+ cr_cnt = PLE_MEM_SIZE;
1598+ seq_printf(s, "dump ple: fid = 0x%08x\n", fid);
1599+ } else {
1600+ seq_printf(s, "dump pse: fid = 0x%08x\n", fid);
1601+ }
1602+
1603+ for (i = 0; i < cr_cnt; i = i + 4) {
1604+ if (is_ple)
1605+ addr = (0xa << 28 | fid << 15) + i;
1606+ else
1607+ addr = (0xb << 28 | fid << 15) + i;
1608+ *ptr = mt76_rr(dev, addr);
1609+ ptr++;
1610+ }
1611+
1612+ seq_printf(s, "raw data: size=%d\n", cr_cnt);
1613+
1614+ seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)data, cr_cnt, false);
1615+ /* dump one txd info */
1616+ if (is_ple) {
1617+ dev->dbg.txd_read_cnt = 1;
1618+ mt7996_dump_bmac_txd_info(s, dev, (__le32 *)&data[0], false, true);
1619+ }
1620+}
1621+
1622+static int
1623+mt7996_ple_fid_read(struct seq_file *s, void *data) {
1624+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1625+
1626+ mt7996_dump_mac_fid(s, dev, dev->dbg.fid_idx, true);
1627+ return 0;
1628+}
1629+
1630+static int
1631+mt7996_pse_fid_read(struct seq_file *s, void *data) {
1632+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1633+
1634+ mt7996_dump_mac_fid(s, dev, dev->dbg.fid_idx, false);
1635+ return 0;
1636+}
1637+
1638+void mt7996_dump_bmac_rxd_info(struct mt7996_dev *dev, __le32 *rxd)
1639+{
1640+ /* dump stop */
1641+ if (!dev->dbg.rxd_read_cnt)
1642+ return;
1643+
1644+ /* force dump */
1645+ if (dev->dbg.rxd_read_cnt > 8)
1646+ dev->dbg.rxd_read_cnt = 8;
1647+
1648+ /* dump txd_read_cnt times */
1649+ if (dev->dbg.rxd_read_cnt != 8)
1650+ dev->dbg.rxd_read_cnt--;
1651+
1652+ printk("rxd raw data: size=%d\n", MT_TXD_SIZE);
1653+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)rxd, 96, false);
1654+
1655+ printk("BMAC_RXD Fields:\n");
1656+
1657+ /* group0 */
1658+ /* dw0 */
1659+ printk("RX_BYTE_COUNT = %d\n",
1660+ GET_FIELD(WF_RX_DESCRIPTOR_RX_BYTE_COUNT, le32_to_cpu(rxd[0])));
1661+ printk("PACKET_TYPE = %d\n",
1662+ GET_FIELD(WF_RX_DESCRIPTOR_PACKET_TYPE, le32_to_cpu(rxd[0])));
1663+
1664+ /* dw1 */
1665+ printk("MLD_ID = %d\n",
1666+ GET_FIELD(WF_RX_DESCRIPTOR_MLD_ID, le32_to_cpu(rxd[1])));
1667+ printk("GROUP_VLD = 0x%x%s%s%s%s%s\n",
1668+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])),
1669+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1670+ & BMAC_GROUP_VLD_1 ? "[group1]" : "",
1671+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1672+ & BMAC_GROUP_VLD_2 ? "[group2]" : "",
1673+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1674+ & BMAC_GROUP_VLD_3 ? "[group3]" : "",
1675+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1676+ & BMAC_GROUP_VLD_4 ? "[group4]" : "",
1677+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1678+ & BMAC_GROUP_VLD_5 ? "[group5]" : "");
1679+ printk("KID = %d\n",
1680+ GET_FIELD(WF_RX_DESCRIPTOR_KID, le32_to_cpu(rxd[1])));
1681+ printk("CM = %d\n",
1682+ GET_FIELD(WF_RX_DESCRIPTOR_CM, le32_to_cpu(rxd[1])));
1683+ printk("CLM = %d\n",
1684+ GET_FIELD(WF_RX_DESCRIPTOR_CLM, le32_to_cpu(rxd[1])));
1685+ printk("I = %d\n",
1686+ GET_FIELD(WF_RX_DESCRIPTOR_I, le32_to_cpu(rxd[1])));
1687+ printk("T = %d\n",
1688+ GET_FIELD(WF_RX_DESCRIPTOR_T, le32_to_cpu(rxd[1])));
1689+ printk("BN = %d\n",
1690+ GET_FIELD(WF_RX_DESCRIPTOR_BN, le32_to_cpu(rxd[1])));
1691+ printk("BIPN_FAIL = %d\n",
1692+ GET_FIELD(WF_RX_DESCRIPTOR_BIPN_FAIL, le32_to_cpu(rxd[1])));
1693+
1694+ /* dw2 */
1695+ printk("BSSID = %d\n",
1696+ GET_FIELD(WF_RX_DESCRIPTOR_BSSID, le32_to_cpu(rxd[2])));
1697+ printk("H = %d%s\n",
1698+ GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])),
1699+ GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])) == 0 ?
1700+ "802.11 frame" : "eth/802.3 frame");
1701+ printk("HEADER_LENGTH(word) = %d\n",
1702+ GET_FIELD(WF_RX_DESCRIPTOR_HEADER_LENGTH, le32_to_cpu(rxd[2])));
1703+ printk("HO(word) = %d\n",
1704+ GET_FIELD(WF_RX_DESCRIPTOR_HO, le32_to_cpu(rxd[2])));
1705+ printk("SEC_MODE = %d\n",
1706+ GET_FIELD(WF_RX_DESCRIPTOR_SEC_MODE, le32_to_cpu(rxd[2])));
1707+ printk("MUBAR = %d\n",
1708+ GET_FIELD(WF_RX_DESCRIPTOR_MUBAR, le32_to_cpu(rxd[2])));
1709+ printk("SWBIT = %d\n",
1710+ GET_FIELD(WF_RX_DESCRIPTOR_SWBIT, le32_to_cpu(rxd[2])));
1711+ printk("DAF = %d\n",
1712+ GET_FIELD(WF_RX_DESCRIPTOR_DAF, le32_to_cpu(rxd[2])));
1713+ printk("EL = %d\n",
1714+ GET_FIELD(WF_RX_DESCRIPTOR_EL, le32_to_cpu(rxd[2])));
1715+ printk("HTF = %d\n",
1716+ GET_FIELD(WF_RX_DESCRIPTOR_HTF, le32_to_cpu(rxd[2])));
1717+ printk("INTF = %d\n",
1718+ GET_FIELD(WF_RX_DESCRIPTOR_INTF, le32_to_cpu(rxd[2])));
1719+ printk("FRAG = %d\n",
1720+ GET_FIELD(WF_RX_DESCRIPTOR_FRAG, le32_to_cpu(rxd[2])));
1721+ printk("NUL = %d\n",
1722+ GET_FIELD(WF_RX_DESCRIPTOR_NUL, le32_to_cpu(rxd[2])));
1723+ printk("NDATA = %d%s\n",
1724+ GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])),
1725+ GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])) == 0 ?
1726+ "[data frame]" : "[mgmt/ctl frame]");
1727+ printk("NAMP = %d%s\n",
1728+ GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])),
1729+ GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])) == 0 ?
1730+ "[ampdu frame]" : "[mpdu frame]");
1731+ printk("BF_RPT = %d\n",
1732+ GET_FIELD(WF_RX_DESCRIPTOR_BF_RPT, le32_to_cpu(rxd[2])));
1733+
1734+ /* dw3 */
1735+ printk("RXV_SN = %d\n",
1736+ GET_FIELD(WF_RX_DESCRIPTOR_RXV_SN, le32_to_cpu(rxd[3])));
1737+ printk("CH_FREQUENCY = %d\n",
1738+ GET_FIELD(WF_RX_DESCRIPTOR_CH_FREQUENCY, le32_to_cpu(rxd[3])));
1739+ printk("A1_TYPE = %d%s%s%s%s\n",
1740+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])),
1741+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 0 ?
1742+ "[reserved]" : "",
1743+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 1 ?
1744+ "[uc2me]" : "",
1745+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 2 ?
1746+ "[mc]" : "",
1747+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 3 ?
1748+ "[bc]" : "");
1749+ printk("HTC = %d\n",
1750+ GET_FIELD(WF_RX_DESCRIPTOR_HTC, le32_to_cpu(rxd[3])));
1751+ printk("TCL = %d\n",
1752+ GET_FIELD(WF_RX_DESCRIPTOR_TCL, le32_to_cpu(rxd[3])));
1753+ printk("BBM = %d\n",
1754+ GET_FIELD(WF_RX_DESCRIPTOR_BBM, le32_to_cpu(rxd[3])));
1755+ printk("BU = %d\n",
1756+ GET_FIELD(WF_RX_DESCRIPTOR_BU, le32_to_cpu(rxd[3])));
1757+ printk("CO_ANT = %d\n",
1758+ GET_FIELD(WF_RX_DESCRIPTOR_CO_ANT, le32_to_cpu(rxd[3])));
1759+ printk("BF_CQI = %d\n",
1760+ GET_FIELD(WF_RX_DESCRIPTOR_BF_CQI, le32_to_cpu(rxd[3])));
1761+ printk("FC = %d\n",
1762+ GET_FIELD(WF_RX_DESCRIPTOR_FC, le32_to_cpu(rxd[3])));
1763+ printk("VLAN = %d\n",
1764+ GET_FIELD(WF_RX_DESCRIPTOR_VLAN, le32_to_cpu(rxd[3])));
1765+
1766+ /* dw4 */
1767+ printk("PF = %d%s%s%s%s\n",
1768+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])),
1769+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 0 ?
1770+ "[msdu]" : "",
1771+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 1 ?
1772+ "[final amsdu]" : "",
1773+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 2 ?
1774+ "[middle amsdu]" : "",
1775+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 3 ?
1776+ "[first amsdu]" : "");
1777+ printk("MAC = %d\n",
1778+ GET_FIELD(WF_RX_DESCRIPTOR_MAC, le32_to_cpu(rxd[4])));
1779+ printk("TID = %d\n",
1780+ GET_FIELD(WF_RX_DESCRIPTOR_TID, le32_to_cpu(rxd[4])));
1781+ printk("ETHER_TYPE_OFFSET = %d\n",
1782+ GET_FIELD(WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET, le32_to_cpu(rxd[4])));
1783+ printk("IP = %d\n",
1784+ GET_FIELD(WF_RX_DESCRIPTOR_IP, le32_to_cpu(rxd[4])));
1785+ printk("UT = %d\n",
1786+ GET_FIELD(WF_RX_DESCRIPTOR_UT, le32_to_cpu(rxd[4])));
1787+ printk("PSE_FID = %d\n",
1788+ GET_FIELD(WF_RX_DESCRIPTOR_PSE_FID, le32_to_cpu(rxd[4])));
1789+
1790+ /* group4 */
1791+ /* dw0 */
1792+ printk("FRAME_CONTROL_FIELD = 0x%x\n",
1793+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1794+ & BMAC_GROUP_VLD_4 ?
1795+ GET_FIELD(WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD, le32_to_cpu(rxd[8])) : 0);
1796+ printk("PEER_MLD_ADDRESS_15_0 = 0x%x\n",
1797+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1798+ & BMAC_GROUP_VLD_4 ?
1799+ GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0_,
1800+ le32_to_cpu(rxd[8])) : 0);
1801+
1802+ /* dw1 */
1803+ printk("PEER_MLD_ADDRESS_47_16 = 0x%x\n",
1804+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1805+ & BMAC_GROUP_VLD_4 ?
1806+ GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16_,
1807+ le32_to_cpu(rxd[9])) : 0);
1808+
1809+ /* dw2 */
1810+ printk("FRAGMENT_NUMBER = %d\n",
1811+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1812+ & BMAC_GROUP_VLD_4 ?
1813+ GET_FIELD(WF_RX_DESCRIPTOR_FRAGMENT_NUMBER,
1814+ le32_to_cpu(rxd[10])) : 0);
1815+ printk("SEQUENCE_NUMBER = %d\n",
1816+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1817+ & BMAC_GROUP_VLD_4 ?
1818+ GET_FIELD(WF_RX_DESCRIPTOR_SEQUENCE_NUMBER,
1819+ le32_to_cpu(rxd[10])) : 0);
1820+ printk("QOS_CONTROL_FIELD = 0x%x\n",
1821+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1822+ & BMAC_GROUP_VLD_4 ?
1823+ GET_FIELD(WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD,
1824+ le32_to_cpu(rxd[10])) : 0);
1825+
1826+ /* dw3 */
1827+ printk("HT_CONTROL_FIELD = 0x%x\n",
1828+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1829+ & BMAC_GROUP_VLD_4 ?
1830+ GET_FIELD(WF_RX_DESCRIPTOR_HT_CONTROL_FIELD,
1831+ le32_to_cpu(rxd[11])) : 0);
1832+}
1833+
1834+static int mt7996_token_txd_read(struct seq_file *s, void *data)
1835+{
1836+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1837+ struct mt76_txwi_cache *t;
1838+ u8* txwi;
1839+
1840+ seq_printf(s, "\n");
1841+ spin_lock_bh(&dev->mt76.token_lock);
1842+
1843+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
1844+ if (t != NULL) {
1845+ struct mt76_dev *mdev = &dev->mt76;
1846+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
1847+ /* dump one txd info */
1848+ dev->dbg.txd_read_cnt = 1;
1849+ mt7996_dump_bmac_txd_info(s, dev, (__le32 *)txwi, true, true);
1850+ seq_printf(s, "\n");
1851+ seq_printf(s, "[SKB]\n");
1852+ seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
1853+ seq_printf(s, "\n");
1854+ }
1855+ spin_unlock_bh(&dev->mt76.token_lock);
1856+ return 0;
1857+}
1858+
1859+static int mt7996_rx_msdu_pg_read(struct seq_file *s, void *data)
1860+{
1861+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1862+ struct list_head *p;
1863+ int i, count = 0, total = 0;
1864+
1865+ seq_printf(s, "Rx Msdu page:\n");
1866+ spin_lock(&dev->wed_rro.lock);
1867+ for (i = 0; i < MT7996_RRO_MSDU_PG_HASH_SIZE; i++) {
1868+ list_for_each(p, &dev->wed_rro.pg_hash_head[i]) {
1869+ count++;
1870+ }
1871+ }
1872+
1873+ total = count;
1874+ list_for_each(p, &dev->wed_rro.pg_addr_cache) {
1875+ total++;
1876+ }
1877+ seq_printf(s, "\ttotal:%8d used:%8d\n", total, count);
1878+ spin_unlock(&dev->wed_rro.lock);
1879+
1880+ return 0;
1881+}
1882+
1883+int mt7996_mtk_init_debugfs_internal(struct mt7996_phy *phy, struct dentry *dir)
1884+{
1885+ struct mt7996_dev *dev = phy->dev;
1886+
1887+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
1888+ mt7996_token_txd_read);
1889+ debugfs_create_u32("txd_dump", 0600, dir, &dev->dbg.txd_read_cnt);
1890+ debugfs_create_u32("rxd_dump", 0600, dir, &dev->dbg.rxd_read_cnt);
1891+ debugfs_create_devm_seqfile(dev->mt76.dev, "rx_msdu_pg", dir,
1892+ mt7996_rx_msdu_pg_read);
1893+
1894+ /* ple/pse fid raw data dump */
1895+ debugfs_create_u32("fid_idx", 0600, dir, &dev->dbg.fid_idx);
1896+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_fid", dir,
1897+ mt7996_ple_fid_read);
1898+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_fid", dir,
1899+ mt7996_pse_fid_read);
1900+
1901+ debugfs_create_u8("dump_ple_txd", 0600, dir, &dev->dbg.dump_ple_txd);
1902+ return 0;
1903+}
1904+
1905+#endif
1906--
developerd0c89452024-10-11 16:53:27 +0800[diff] [blame^]19072.45.2
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame]1908