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git01.mediatek.com / filogic / rdk-b / meta-filogic / 05f3b2be78bc66ffe25f0298d8edf45ca46a1ca2 / . / recipes-wifi / linux-mt76 / files / patches-3.x / 0120-mtk-mt76-add-internal-debug-tool.patch
blob: 99adad3d0ffeea8f919d4c1603b6544db704b535 [file] [log] [blame]
developer05f3b2b2024-08-19 19:17:34 +0800[diff] [blame^]1From a63950272ed7934e2777155cb8ea06bb82d75c33 Mon Sep 17 00:00:00 2001
2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Mon, 22 Apr 2024 12:22:05 +0800
4Subject: [PATCH 120/199] mtk: mt76: add internal debug tool
5
6Add the following DebugFS knobs:
7- reset_counter: reset TX/RX statistical counters in FW, WTBL, and MT76.
8- per: show PER, which is calculated using MPDU-based statistics from CMDRPT-TX.
9
10Sources of statistics stored in Eagle mt76_sta_stats are summarized below.
11<tx_bytes> source: CMDRPT-TX
12<tx_packets> unit: MSDU. source: WTBL.
13<tx_retries> unit: MPDU. source: TX-Free-Done Event
14<tx_failed> unit: MPDU. source: TX-Free-Done Event
15<tx_total_mpdu_cnt> unit: MPDU. source: CMDRPT-TX
16<tx_failed_mpdu_cnt> unit: MPDU. source: CMDRPT-TX
17<rx_bytes> source: RXRPT
18<rx_packets> unit: MSDU. source: WTBL.
19<rx_errors> Not used.
20<rx_drops> Not used.
21
22Add token pending time
23
24Refactor DebugFS knob amsdu_info to read unambiguous CR addresses for HW-AMSDU information.
25
26Remove the duplicate function in mtk_debugfs.c & mtk_debug_i.c
27Only enable mt7996_mcu_fw_log_2_host function in mcu.c
28
29mtk: wifi: mt76: mt7996: add more ids support for eagle and kite
30
31IDS is the internal debug commands for firmware debug usage. This
32debugfs will be called only when we use chihuahua tool. Since MT7990 and
33MT7992 use the same firmware branch. This commit change some ids idx and
34support mode ids options as below:
35
361. set fw_dbg=2:62 for MUCOP
372. set fw_dbg=1:85 for BSRP
383. set fw_dbg=1:86 for Tput Monitor
394. set fw_dbg=1:100 for MLO
405. set fw_dbg=1:101 for ERROR Log
41
42mtk: wifi: mt76: mt7996: revise DebugFS command ple_info to show correct TXCMD queue information
43
44Each band has its own set of TXCMD queues in PLE module.
45However, the original codebase only specifies one shared set of queues with wrong queue indices.
46
47mtk: wifi: mt76: mt7992: revise DebugFS command ple_info to accommodate Kite
48
49Because Kite only supports 512 STAs, the number of AC_QUEUE_EMPTY CRs is less than that of Eagle.
50Consequently, some related macros have to be revised to prevent reading wrong CRs.
51
52Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
53Signed-off-by: MeiChia Chiu <meichia.chiu@mediatek.com>
54Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
55Signed-off-by: Benjamin Lin <benjamin-jw.lin@mediatek.com>
56Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
57---
58 mt7996/Makefile | 3 +-
59 mt7996/debugfs.c | 6 +-
60 mt7996/init.c | 4 +
61 mt7996/mac.c | 2 +
62 mt7996/mt7996.h | 12 +
63 mt7996/mtk_debug_i.h | 987 +++++++++++++++++++++++++++++++++++++++++
64 mt7996/mtk_debugfs_i.c | 720 ++++++++++++++++++++++++++++++
65 7 files changed, 1732 insertions(+), 2 deletions(-)
66 create mode 100644 mt7996/mtk_debug_i.h
67 create mode 100644 mt7996/mtk_debugfs_i.c
68
69diff --git a/mt7996/Makefile b/mt7996/Makefile
70index 6643c7a3..49ec9154 100644
71--- a/mt7996/Makefile
72+++ b/mt7996/Makefile
73@@ -1,4 +1,5 @@
74 # SPDX-License-Identifier: ISC
75+EXTRA_CFLAGS += -Werror
76 EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
77 EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
78 EXTRA_CFLAGS += -DCONFIG_MTK_VENDOR
79@@ -11,4 +12,4 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
80 mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o
81 mt7996e-$(CONFIG_NL80211_TESTMODE) += testmode.o
82
83-mt7996e-y += mtk_debugfs.o mtk_mcu.o
84+mt7996e-y += mtk_debugfs.o mtk_mcu.o mtk_debugfs_i.o
85diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
86index 63b8887d..2c553cf3 100644
87--- a/mt7996/debugfs.c
88+++ b/mt7996/debugfs.c
89@@ -1118,8 +1118,12 @@ int mt7996_init_debugfs(struct mt7996_phy *phy)
90 debugfs_create_file("fw_debug_muru_disable", 0600, dir, dev,
91 &fops_fw_debug_muru_disable);
92
93- if (phy == &dev->phy)
94+ if (phy == &dev->phy) {
95 dev->debugfs_dir = dir;
96+#ifdef CONFIG_MTK_DEBUG
97+ mt7996_mtk_init_debugfs_internal(phy, dir);
98+#endif
99+ }
100
101 #ifdef CONFIG_MTK_DEBUG
102 debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
103diff --git a/mt7996/init.c b/mt7996/init.c
104index a1941869..057d20db 100644
105--- a/mt7996/init.c
106+++ b/mt7996/init.c
107@@ -886,6 +886,10 @@ void mt7996_rro_hw_init(struct mt7996_dev *dev)
108 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0,
109 dev->wed_rro.addr_elem[0].phy_addr);
110 } else {
111+ INIT_LIST_HEAD(&dev->wed_rro.pg_addr_cache);
112+ for (i = 0; i < MT7996_RRO_MSDU_PG_HASH_SIZE; i++)
113+ INIT_LIST_HEAD(&dev->wed_rro.pg_hash_head[i]);
114+
115 /* TODO: remove line after WM has set */
116 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK);
117
118diff --git a/mt7996/mac.c b/mt7996/mac.c
119index 6462c64c..c6816ab5 100644
120--- a/mt7996/mac.c
121+++ b/mt7996/mac.c
122@@ -334,6 +334,7 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q,
123 #ifdef CONFIG_MTK_DEBUG
124 if (dev->dbg.dump_rx_raw)
125 mt7996_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
126+ mt7996_dump_bmac_rxd_info(dev, rxd);
127 #endif
128 hw_aggr = status->aggr;
129 memset(status, 0, sizeof(*status));
130@@ -995,6 +996,7 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
131 mt7996_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
132 if (dev->dbg.dump_tx_pkt)
133 mt7996_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
134+ mt7996_dump_bmac_txd_info(NULL, dev, (__le32 *)txwi, true, false);
135 #endif
136
137 return 0;
138diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
139index ff13d00e..ef544957 100644
140--- a/mt7996/mt7996.h
141+++ b/mt7996/mt7996.h
142@@ -101,6 +101,7 @@
143
144 #define MT7996_BUILD_TIME_LEN 24
145
146+#define MT7996_RRO_MSDU_PG_HASH_SIZE 127
147 #define MT7996_RRO_MAX_SESSION 1024
148 #define MT7996_RRO_WINDOW_MAX_LEN 1024
149 #define MT7996_RRO_ADDR_ELEM_LEN 128
150@@ -688,6 +689,9 @@ struct mt7996_dev {
151 struct work_struct work;
152 struct list_head poll_list;
153 spinlock_t lock;
154+
155+ struct list_head pg_addr_cache;
156+ struct list_head pg_hash_head[MT7996_RRO_MSDU_PG_HASH_SIZE];
157 } wed_rro;
158
159 bool testmode_enable;
160@@ -744,7 +748,11 @@ struct mt7996_dev {
161 bool dump_tx_pkt:1;
162 bool dump_rx_pkt:1;
163 bool dump_rx_raw:1;
164+ u8 dump_ple_txd;
165 u32 token_idx;
166+ u32 rxd_read_cnt;
167+ u32 txd_read_cnt;
168+ u32 fid_idx;
169 } dbg;
170 const struct mt7996_dbg_reg_desc *dbg_reg;
171 #endif
172@@ -1288,6 +1296,10 @@ enum {
173 };
174
175 void mt7996_packet_log_to_host(struct mt7996_dev *dev, const void *data, int len, int type, int des_len);
176+void mt7996_dump_bmac_rxd_info(struct mt7996_dev *dev, __le32 *rxd);
177+void mt7996_dump_bmac_txd_info(struct seq_file *s, struct mt7996_dev *dev,
178+ __le32 *txd, bool is_hif_txd, bool dump_txp);
179+int mt7996_mtk_init_debugfs_internal(struct mt7996_phy *phy, struct dentry *dir);
180 #endif
181
182 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
183diff --git a/mt7996/mtk_debug_i.h b/mt7996/mtk_debug_i.h
184new file mode 100644
185index 00000000..d3756fa2
186--- /dev/null
187+++ b/mt7996/mtk_debug_i.h
188@@ -0,0 +1,987 @@
189+#ifndef __MTK_DEBUG_I_H
190+#define __MTK_DEBUG_I_H
191+
192+#ifdef CONFIG_MTK_DEBUG
193+
194+// DW0
195+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_DW 0
196+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_ADDR 0
197+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_MASK 0x0000ffff // 15- 0
198+#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_SHIFT 0
199+#define WF_RX_DESCRIPTOR_PACKET_TYPE_DW 0
200+#define WF_RX_DESCRIPTOR_PACKET_TYPE_ADDR 0
201+#define WF_RX_DESCRIPTOR_PACKET_TYPE_MASK 0xf8000000 // 31-27
202+#define WF_RX_DESCRIPTOR_PACKET_TYPE_SHIFT 27
203+// DW1
204+#define WF_RX_DESCRIPTOR_MLD_ID_DW 1
205+#define WF_RX_DESCRIPTOR_MLD_ID_ADDR 4
206+#define WF_RX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0
207+#define WF_RX_DESCRIPTOR_MLD_ID_SHIFT 0
208+#define WF_RX_DESCRIPTOR_GROUP_VLD_DW 1
209+#define WF_RX_DESCRIPTOR_GROUP_VLD_ADDR 4
210+#define WF_RX_DESCRIPTOR_GROUP_VLD_MASK 0x001f0000 // 20-16
211+#define WF_RX_DESCRIPTOR_GROUP_VLD_SHIFT 16
212+#define WF_RX_DESCRIPTOR_KID_DW 1
213+#define WF_RX_DESCRIPTOR_KID_ADDR 4
214+#define WF_RX_DESCRIPTOR_KID_MASK 0x00600000 // 22-21
215+#define WF_RX_DESCRIPTOR_KID_SHIFT 21
216+#define WF_RX_DESCRIPTOR_CM_DW 1
217+#define WF_RX_DESCRIPTOR_CM_ADDR 4
218+#define WF_RX_DESCRIPTOR_CM_MASK 0x00800000 // 23-23
219+#define WF_RX_DESCRIPTOR_CM_SHIFT 23
220+#define WF_RX_DESCRIPTOR_CLM_DW 1
221+#define WF_RX_DESCRIPTOR_CLM_ADDR 4
222+#define WF_RX_DESCRIPTOR_CLM_MASK 0x01000000 // 24-24
223+#define WF_RX_DESCRIPTOR_CLM_SHIFT 24
224+#define WF_RX_DESCRIPTOR_I_DW 1
225+#define WF_RX_DESCRIPTOR_I_ADDR 4
226+#define WF_RX_DESCRIPTOR_I_MASK 0x02000000 // 25-25
227+#define WF_RX_DESCRIPTOR_I_SHIFT 25
228+#define WF_RX_DESCRIPTOR_T_DW 1
229+#define WF_RX_DESCRIPTOR_T_ADDR 4
230+#define WF_RX_DESCRIPTOR_T_MASK 0x04000000 // 26-26
231+#define WF_RX_DESCRIPTOR_T_SHIFT 26
232+#define WF_RX_DESCRIPTOR_BN_DW 1
233+#define WF_RX_DESCRIPTOR_BN_ADDR 4
234+#define WF_RX_DESCRIPTOR_BN_MASK 0x18000000 // 28-27
235+#define WF_RX_DESCRIPTOR_BN_SHIFT 27
236+#define WF_RX_DESCRIPTOR_BIPN_FAIL_DW 1
237+#define WF_RX_DESCRIPTOR_BIPN_FAIL_ADDR 4
238+#define WF_RX_DESCRIPTOR_BIPN_FAIL_MASK 0x20000000 // 29-29
239+#define WF_RX_DESCRIPTOR_BIPN_FAIL_SHIFT 29
240+// DW2
241+#define WF_RX_DESCRIPTOR_BSSID_DW 2
242+#define WF_RX_DESCRIPTOR_BSSID_ADDR 8
243+#define WF_RX_DESCRIPTOR_BSSID_MASK 0x0000003f // 5- 0
244+#define WF_RX_DESCRIPTOR_BSSID_SHIFT 0
245+#define WF_RX_DESCRIPTOR_H_DW 2
246+#define WF_RX_DESCRIPTOR_H_ADDR 8
247+#define WF_RX_DESCRIPTOR_H_MASK 0x00000080 // 7- 7
248+#define WF_RX_DESCRIPTOR_H_SHIFT 7
249+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_DW 2
250+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_ADDR 8
251+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_MASK 0x00001f00 // 12- 8
252+#define WF_RX_DESCRIPTOR_HEADER_LENGTH_SHIFT 8
253+#define WF_RX_DESCRIPTOR_HO_DW 2
254+#define WF_RX_DESCRIPTOR_HO_ADDR 8
255+#define WF_RX_DESCRIPTOR_HO_MASK 0x0000e000 // 15-13
256+#define WF_RX_DESCRIPTOR_HO_SHIFT 13
257+#define WF_RX_DESCRIPTOR_SEC_MODE_DW 2
258+#define WF_RX_DESCRIPTOR_SEC_MODE_ADDR 8
259+#define WF_RX_DESCRIPTOR_SEC_MODE_MASK 0x001f0000 // 20-16
260+#define WF_RX_DESCRIPTOR_SEC_MODE_SHIFT 16
261+#define WF_RX_DESCRIPTOR_MUBAR_DW 2
262+#define WF_RX_DESCRIPTOR_MUBAR_ADDR 8
263+#define WF_RX_DESCRIPTOR_MUBAR_MASK 0x00200000 // 21-21
264+#define WF_RX_DESCRIPTOR_MUBAR_SHIFT 21
265+#define WF_RX_DESCRIPTOR_SWBIT_DW 2
266+#define WF_RX_DESCRIPTOR_SWBIT_ADDR 8
267+#define WF_RX_DESCRIPTOR_SWBIT_MASK 0x00400000 // 22-22
268+#define WF_RX_DESCRIPTOR_SWBIT_SHIFT 22
269+#define WF_RX_DESCRIPTOR_DAF_DW 2
270+#define WF_RX_DESCRIPTOR_DAF_ADDR 8
271+#define WF_RX_DESCRIPTOR_DAF_MASK 0x00800000 // 23-23
272+#define WF_RX_DESCRIPTOR_DAF_SHIFT 23
273+#define WF_RX_DESCRIPTOR_EL_DW 2
274+#define WF_RX_DESCRIPTOR_EL_ADDR 8
275+#define WF_RX_DESCRIPTOR_EL_MASK 0x01000000 // 24-24
276+#define WF_RX_DESCRIPTOR_EL_SHIFT 24
277+#define WF_RX_DESCRIPTOR_HTF_DW 2
278+#define WF_RX_DESCRIPTOR_HTF_ADDR 8
279+#define WF_RX_DESCRIPTOR_HTF_MASK 0x02000000 // 25-25
280+#define WF_RX_DESCRIPTOR_HTF_SHIFT 25
281+#define WF_RX_DESCRIPTOR_INTF_DW 2
282+#define WF_RX_DESCRIPTOR_INTF_ADDR 8
283+#define WF_RX_DESCRIPTOR_INTF_MASK 0x04000000 // 26-26
284+#define WF_RX_DESCRIPTOR_INTF_SHIFT 26
285+#define WF_RX_DESCRIPTOR_FRAG_DW 2
286+#define WF_RX_DESCRIPTOR_FRAG_ADDR 8
287+#define WF_RX_DESCRIPTOR_FRAG_MASK 0x08000000 // 27-27
288+#define WF_RX_DESCRIPTOR_FRAG_SHIFT 27
289+#define WF_RX_DESCRIPTOR_NUL_DW 2
290+#define WF_RX_DESCRIPTOR_NUL_ADDR 8
291+#define WF_RX_DESCRIPTOR_NUL_MASK 0x10000000 // 28-28
292+#define WF_RX_DESCRIPTOR_NUL_SHIFT 28
293+#define WF_RX_DESCRIPTOR_NDATA_DW 2
294+#define WF_RX_DESCRIPTOR_NDATA_ADDR 8
295+#define WF_RX_DESCRIPTOR_NDATA_MASK 0x20000000 // 29-29
296+#define WF_RX_DESCRIPTOR_NDATA_SHIFT 29
297+#define WF_RX_DESCRIPTOR_NAMP_DW 2
298+#define WF_RX_DESCRIPTOR_NAMP_ADDR 8
299+#define WF_RX_DESCRIPTOR_NAMP_MASK 0x40000000 // 30-30
300+#define WF_RX_DESCRIPTOR_NAMP_SHIFT 30
301+#define WF_RX_DESCRIPTOR_BF_RPT_DW 2
302+#define WF_RX_DESCRIPTOR_BF_RPT_ADDR 8
303+#define WF_RX_DESCRIPTOR_BF_RPT_MASK 0x80000000 // 31-31
304+#define WF_RX_DESCRIPTOR_BF_RPT_SHIFT 31
305+// DW3
306+#define WF_RX_DESCRIPTOR_RXV_SN_DW 3
307+#define WF_RX_DESCRIPTOR_RXV_SN_ADDR 12
308+#define WF_RX_DESCRIPTOR_RXV_SN_MASK 0x000000ff // 7- 0
309+#define WF_RX_DESCRIPTOR_RXV_SN_SHIFT 0
310+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_DW 3
311+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_ADDR 12
312+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_MASK 0x0000ff00 // 15- 8
313+#define WF_RX_DESCRIPTOR_CH_FREQUENCY_SHIFT 8
314+#define WF_RX_DESCRIPTOR_A1_TYPE_DW 3
315+#define WF_RX_DESCRIPTOR_A1_TYPE_ADDR 12
316+#define WF_RX_DESCRIPTOR_A1_TYPE_MASK 0x00030000 // 17-16
317+#define WF_RX_DESCRIPTOR_A1_TYPE_SHIFT 16
318+#define WF_RX_DESCRIPTOR_HTC_DW 3
319+#define WF_RX_DESCRIPTOR_HTC_ADDR 12
320+#define WF_RX_DESCRIPTOR_HTC_MASK 0x00040000 // 18-18
321+#define WF_RX_DESCRIPTOR_HTC_SHIFT 18
322+#define WF_RX_DESCRIPTOR_TCL_DW 3
323+#define WF_RX_DESCRIPTOR_TCL_ADDR 12
324+#define WF_RX_DESCRIPTOR_TCL_MASK 0x00080000 // 19-19
325+#define WF_RX_DESCRIPTOR_TCL_SHIFT 19
326+#define WF_RX_DESCRIPTOR_BBM_DW 3
327+#define WF_RX_DESCRIPTOR_BBM_ADDR 12
328+#define WF_RX_DESCRIPTOR_BBM_MASK 0x00100000 // 20-20
329+#define WF_RX_DESCRIPTOR_BBM_SHIFT 20
330+#define WF_RX_DESCRIPTOR_BU_DW 3
331+#define WF_RX_DESCRIPTOR_BU_ADDR 12
332+#define WF_RX_DESCRIPTOR_BU_MASK 0x00200000 // 21-21
333+#define WF_RX_DESCRIPTOR_BU_SHIFT 21
334+#define WF_RX_DESCRIPTOR_CO_ANT_DW 3
335+#define WF_RX_DESCRIPTOR_CO_ANT_ADDR 12
336+#define WF_RX_DESCRIPTOR_CO_ANT_MASK 0x00400000 // 22-22
337+#define WF_RX_DESCRIPTOR_CO_ANT_SHIFT 22
338+#define WF_RX_DESCRIPTOR_BF_CQI_DW 3
339+#define WF_RX_DESCRIPTOR_BF_CQI_ADDR 12
340+#define WF_RX_DESCRIPTOR_BF_CQI_MASK 0x00800000 // 23-23
341+#define WF_RX_DESCRIPTOR_BF_CQI_SHIFT 23
342+#define WF_RX_DESCRIPTOR_FC_DW 3
343+#define WF_RX_DESCRIPTOR_FC_ADDR 12
344+#define WF_RX_DESCRIPTOR_FC_MASK 0x01000000 // 24-24
345+#define WF_RX_DESCRIPTOR_FC_SHIFT 24
346+#define WF_RX_DESCRIPTOR_VLAN_DW 3
347+#define WF_RX_DESCRIPTOR_VLAN_ADDR 12
348+#define WF_RX_DESCRIPTOR_VLAN_MASK 0x80000000 // 31-31
349+#define WF_RX_DESCRIPTOR_VLAN_SHIFT 31
350+// DW4
351+#define WF_RX_DESCRIPTOR_PF_DW 4
352+#define WF_RX_DESCRIPTOR_PF_ADDR 16
353+#define WF_RX_DESCRIPTOR_PF_MASK 0x00000003 // 1- 0
354+#define WF_RX_DESCRIPTOR_PF_SHIFT 0
355+#define WF_RX_DESCRIPTOR_MAC_DW 4
356+#define WF_RX_DESCRIPTOR_MAC_ADDR 16
357+#define WF_RX_DESCRIPTOR_MAC_MASK 0x00000004 // 2- 2
358+#define WF_RX_DESCRIPTOR_MAC_SHIFT 2
359+#define WF_RX_DESCRIPTOR_TID_DW 4
360+#define WF_RX_DESCRIPTOR_TID_ADDR 16
361+#define WF_RX_DESCRIPTOR_TID_MASK 0x00000078 // 6- 3
362+#define WF_RX_DESCRIPTOR_TID_SHIFT 3
363+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 4
364+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 16
365+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x00003f80 // 13- 7
366+#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 7
367+#define WF_RX_DESCRIPTOR_IP_DW 4
368+#define WF_RX_DESCRIPTOR_IP_ADDR 16
369+#define WF_RX_DESCRIPTOR_IP_MASK 0x00004000 // 14-14
370+#define WF_RX_DESCRIPTOR_IP_SHIFT 14
371+#define WF_RX_DESCRIPTOR_UT_DW 4
372+#define WF_RX_DESCRIPTOR_UT_ADDR 16
373+#define WF_RX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15
374+#define WF_RX_DESCRIPTOR_UT_SHIFT 15
375+#define WF_RX_DESCRIPTOR_PSE_FID_DW 4
376+#define WF_RX_DESCRIPTOR_PSE_FID_ADDR 16
377+#define WF_RX_DESCRIPTOR_PSE_FID_MASK 0x0fff0000 // 27-16
378+#define WF_RX_DESCRIPTOR_PSE_FID_SHIFT 16
379+// DW5
380+// DW6
381+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__DW 6
382+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__ADDR 24
383+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__MASK 0xffffffff // 31- 0
384+#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__SHIFT 0
385+// DW7
386+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__DW 7
387+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__ADDR 28
388+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__MASK 0x00000003 // 1- 0
389+#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__SHIFT 0
390+#define WF_RX_DESCRIPTOR_DP_DW 7
391+#define WF_RX_DESCRIPTOR_DP_ADDR 28
392+#define WF_RX_DESCRIPTOR_DP_MASK 0x00080000 // 19-19
393+#define WF_RX_DESCRIPTOR_DP_SHIFT 19
394+#define WF_RX_DESCRIPTOR_CLS_DW 7
395+#define WF_RX_DESCRIPTOR_CLS_ADDR 28
396+#define WF_RX_DESCRIPTOR_CLS_MASK 0x00100000 // 20-20
397+#define WF_RX_DESCRIPTOR_CLS_SHIFT 20
398+#define WF_RX_DESCRIPTOR_OFLD_DW 7
399+#define WF_RX_DESCRIPTOR_OFLD_ADDR 28
400+#define WF_RX_DESCRIPTOR_OFLD_MASK 0x00600000 // 22-21
401+#define WF_RX_DESCRIPTOR_OFLD_SHIFT 21
402+#define WF_RX_DESCRIPTOR_MGC_DW 7
403+#define WF_RX_DESCRIPTOR_MGC_ADDR 28
404+#define WF_RX_DESCRIPTOR_MGC_MASK 0x00800000 // 23-23
405+#define WF_RX_DESCRIPTOR_MGC_SHIFT 23
406+#define WF_RX_DESCRIPTOR_WOL_DW 7
407+#define WF_RX_DESCRIPTOR_WOL_ADDR 28
408+#define WF_RX_DESCRIPTOR_WOL_MASK 0x1f000000 // 28-24
409+#define WF_RX_DESCRIPTOR_WOL_SHIFT 24
410+#define WF_RX_DESCRIPTOR_PF_MODE_DW 7
411+#define WF_RX_DESCRIPTOR_PF_MODE_ADDR 28
412+#define WF_RX_DESCRIPTOR_PF_MODE_MASK 0x20000000 // 29-29
413+#define WF_RX_DESCRIPTOR_PF_MODE_SHIFT 29
414+#define WF_RX_DESCRIPTOR_PF_STS_DW 7
415+#define WF_RX_DESCRIPTOR_PF_STS_ADDR 28
416+#define WF_RX_DESCRIPTOR_PF_STS_MASK 0xc0000000 // 31-30
417+#define WF_RX_DESCRIPTOR_PF_STS_SHIFT 30
418+// DW8
419+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_DW 8
420+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_ADDR 32
421+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_MASK 0x0000ffff // 15- 0
422+#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_SHIFT 0
423+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__DW 8
424+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__ADDR 32
425+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__MASK 0xffff0000 // 31-16
426+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__SHIFT 16
427+// DW9
428+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__DW 9
429+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__ADDR 36
430+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__MASK 0xffffffff // 31- 0
431+#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__SHIFT 0
432+// DW10
433+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_DW 10
434+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_ADDR 40
435+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_MASK 0x0000000f // 3- 0
436+#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_SHIFT 0
437+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_DW 10
438+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_ADDR 40
439+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_MASK 0x0000fff0 // 15- 4
440+#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_SHIFT 4
441+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_DW 10
442+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_ADDR 40
443+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_MASK 0xffff0000 // 31-16
444+#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_SHIFT 16
445+// DW11
446+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_DW 11
447+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_ADDR 44
448+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_MASK 0xffffffff // 31- 0
449+#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_SHIFT 0
450+// DW12
451+#define WF_RX_DESCRIPTOR_PN_31_0__DW 12
452+#define WF_RX_DESCRIPTOR_PN_31_0__ADDR 48
453+#define WF_RX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0
454+#define WF_RX_DESCRIPTOR_PN_31_0__SHIFT 0
455+// DW13
456+#define WF_RX_DESCRIPTOR_PN_63_32__DW 13
457+#define WF_RX_DESCRIPTOR_PN_63_32__ADDR 52
458+#define WF_RX_DESCRIPTOR_PN_63_32__MASK 0xffffffff // 31- 0
459+#define WF_RX_DESCRIPTOR_PN_63_32__SHIFT 0
460+// DW14
461+#define WF_RX_DESCRIPTOR_PN_95_64__DW 14
462+#define WF_RX_DESCRIPTOR_PN_95_64__ADDR 56
463+#define WF_RX_DESCRIPTOR_PN_95_64__MASK 0xffffffff // 31- 0
464+#define WF_RX_DESCRIPTOR_PN_95_64__SHIFT 0
465+// DW15
466+#define WF_RX_DESCRIPTOR_PN_127_96__DW 15
467+#define WF_RX_DESCRIPTOR_PN_127_96__ADDR 60
468+#define WF_RX_DESCRIPTOR_PN_127_96__MASK 0xffffffff // 31- 0
469+#define WF_RX_DESCRIPTOR_PN_127_96__SHIFT 0
470+// DW16
471+#define WF_RX_DESCRIPTOR_TIMESTAMP_DW 16
472+#define WF_RX_DESCRIPTOR_TIMESTAMP_ADDR 64
473+#define WF_RX_DESCRIPTOR_TIMESTAMP_MASK 0xffffffff // 31- 0
474+#define WF_RX_DESCRIPTOR_TIMESTAMP_SHIFT 0
475+// DW17
476+#define WF_RX_DESCRIPTOR_CRC_DW 17
477+#define WF_RX_DESCRIPTOR_CRC_ADDR 68
478+#define WF_RX_DESCRIPTOR_CRC_MASK 0xffffffff // 31- 0
479+#define WF_RX_DESCRIPTOR_CRC_SHIFT 0
480+// DW18
481+// DW19
482+// DW20
483+#define WF_RX_DESCRIPTOR_P_RXV_DW 20
484+#define WF_RX_DESCRIPTOR_P_RXV_ADDR 80
485+#define WF_RX_DESCRIPTOR_P_RXV_MASK 0xffffffff // 31- 0
486+#define WF_RX_DESCRIPTOR_P_RXV_SHIFT 0
487+// DW21
488+// DO NOT process repeat field(p_rxv)
489+// DW22
490+#define WF_RX_DESCRIPTOR_DBW_DW 22
491+#define WF_RX_DESCRIPTOR_DBW_ADDR 88
492+#define WF_RX_DESCRIPTOR_DBW_MASK 0x00000007 // 2- 0
493+#define WF_RX_DESCRIPTOR_DBW_SHIFT 0
494+#define WF_RX_DESCRIPTOR_GI_DW 22
495+#define WF_RX_DESCRIPTOR_GI_ADDR 88
496+#define WF_RX_DESCRIPTOR_GI_MASK 0x00000018 // 4- 3
497+#define WF_RX_DESCRIPTOR_GI_SHIFT 3
498+#define WF_RX_DESCRIPTOR_DCM_DW 22
499+#define WF_RX_DESCRIPTOR_DCM_ADDR 88
500+#define WF_RX_DESCRIPTOR_DCM_MASK 0x00000020 // 5- 5
501+#define WF_RX_DESCRIPTOR_DCM_SHIFT 5
502+#define WF_RX_DESCRIPTOR_NUM_RX_DW 22
503+#define WF_RX_DESCRIPTOR_NUM_RX_ADDR 88
504+#define WF_RX_DESCRIPTOR_NUM_RX_MASK 0x000001c0 // 8- 6
505+#define WF_RX_DESCRIPTOR_NUM_RX_SHIFT 6
506+#define WF_RX_DESCRIPTOR_STBC_DW 22
507+#define WF_RX_DESCRIPTOR_STBC_ADDR 88
508+#define WF_RX_DESCRIPTOR_STBC_MASK 0x00000600 // 10- 9
509+#define WF_RX_DESCRIPTOR_STBC_SHIFT 9
510+#define WF_RX_DESCRIPTOR_TX_MODE_DW 22
511+#define WF_RX_DESCRIPTOR_TX_MODE_ADDR 88
512+#define WF_RX_DESCRIPTOR_TX_MODE_MASK 0x00007800 // 14-11
513+#define WF_RX_DESCRIPTOR_TX_MODE_SHIFT 11
514+// DW23
515+#define WF_RX_DESCRIPTOR_RCPI_DW 23
516+#define WF_RX_DESCRIPTOR_RCPI_ADDR 92
517+#define WF_RX_DESCRIPTOR_RCPI_MASK 0xffffffff // 31- 0
518+#define WF_RX_DESCRIPTOR_RCPI_SHIFT 0
519+// DW24
520+#define WF_RX_DESCRIPTOR_C_RXV_DW 24
521+#define WF_RX_DESCRIPTOR_C_RXV_ADDR 96
522+#define WF_RX_DESCRIPTOR_C_RXV_MASK 0xffffffff // 31- 0
523+#define WF_RX_DESCRIPTOR_C_RXV_SHIFT 0
524+// DW25
525+// DO NOT process repeat field(c_rxv)
526+// DW26
527+// DO NOT process repeat field(c_rxv)
528+// DW27
529+// DO NOT process repeat field(c_rxv)
530+// DW28
531+// DO NOT process repeat field(c_rxv)
532+// DW29
533+// DO NOT process repeat field(c_rxv)
534+// DW30
535+// DO NOT process repeat field(c_rxv)
536+// DW31
537+// DO NOT process repeat field(c_rxv)
538+// DW32
539+// DO NOT process repeat field(c_rxv)
540+// DW33
541+// DO NOT process repeat field(c_rxv)
542+// DW34
543+// DO NOT process repeat field(c_rxv)
544+// DW35
545+// DO NOT process repeat field(c_rxv)
546+// DW36
547+// DO NOT process repeat field(c_rxv)
548+// DW37
549+// DO NOT process repeat field(c_rxv)
550+// DW38
551+// DO NOT process repeat field(c_rxv)
552+// DW39
553+// DO NOT process repeat field(c_rxv)
554+// DW40
555+// DO NOT process repeat field(c_rxv)
556+// DW41
557+// DO NOT process repeat field(c_rxv)
558+// DW42
559+// DO NOT process repeat field(c_rxv)
560+// DW43
561+// DO NOT process repeat field(c_rxv)
562+// DW44
563+// DO NOT process repeat field(c_rxv)
564+// DW45
565+// DO NOT process repeat field(c_rxv)
566+// DW46
567+// DW47
568+
569+/* TXD */
570+// DW0
571+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_DW 0
572+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_ADDR 0
573+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_MASK 0x0000ffff // 15- 0
574+#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_SHIFT 0
575+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 0
576+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 0
577+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x007f0000 // 22-16
578+#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 16
579+#define WF_TX_DESCRIPTOR_PKT_FT_DW 0
580+#define WF_TX_DESCRIPTOR_PKT_FT_ADDR 0
581+#define WF_TX_DESCRIPTOR_PKT_FT_MASK 0x01800000 // 24-23
582+#define WF_TX_DESCRIPTOR_PKT_FT_SHIFT 23
583+#define WF_TX_DESCRIPTOR_Q_IDX_DW 0
584+#define WF_TX_DESCRIPTOR_Q_IDX_ADDR 0
585+#define WF_TX_DESCRIPTOR_Q_IDX_MASK 0xfe000000 // 31-25
586+#define WF_TX_DESCRIPTOR_Q_IDX_SHIFT 25
587+// DW1
588+#define WF_TX_DESCRIPTOR_MLD_ID_DW 1
589+#define WF_TX_DESCRIPTOR_MLD_ID_ADDR 4
590+#define WF_TX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0
591+#define WF_TX_DESCRIPTOR_MLD_ID_SHIFT 0
592+#define WF_TX_DESCRIPTOR_TGID_DW 1
593+#define WF_TX_DESCRIPTOR_TGID_ADDR 4
594+#define WF_TX_DESCRIPTOR_TGID_MASK 0x00003000 // 13-12
595+#define WF_TX_DESCRIPTOR_TGID_SHIFT 12
596+#define WF_TX_DESCRIPTOR_HF_DW 1
597+#define WF_TX_DESCRIPTOR_HF_ADDR 4
598+#define WF_TX_DESCRIPTOR_HF_MASK 0x0000c000 // 15-14
599+#define WF_TX_DESCRIPTOR_HF_SHIFT 14
600+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_DW 1
601+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_ADDR 4
602+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_MASK 0x001f0000 // 20-16
603+#define WF_TX_DESCRIPTOR_HEADER_LENGTH_SHIFT 16
604+#define WF_TX_DESCRIPTOR_MRD_DW 1
605+#define WF_TX_DESCRIPTOR_MRD_ADDR 4
606+#define WF_TX_DESCRIPTOR_MRD_MASK 0x00010000 // 16-16
607+#define WF_TX_DESCRIPTOR_MRD_SHIFT 16
608+#define WF_TX_DESCRIPTOR_EOSP_DW 1
609+#define WF_TX_DESCRIPTOR_EOSP_ADDR 4
610+#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17
611+#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17
612+#define WF_TX_DESCRIPTOR_EOSP_DW 1
613+#define WF_TX_DESCRIPTOR_EOSP_ADDR 4
614+#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17
615+#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17
616+#define WF_TX_DESCRIPTOR_AMS_DW 1
617+#define WF_TX_DESCRIPTOR_AMS_ADDR 4
618+#define WF_TX_DESCRIPTOR_AMS_MASK 0x00040000 // 18-18
619+#define WF_TX_DESCRIPTOR_AMS_SHIFT 18
620+#define WF_TX_DESCRIPTOR_RMVL_DW 1
621+#define WF_TX_DESCRIPTOR_RMVL_ADDR 4
622+#define WF_TX_DESCRIPTOR_RMVL_MASK 0x00040000 // 18-18
623+#define WF_TX_DESCRIPTOR_RMVL_SHIFT 18
624+#define WF_TX_DESCRIPTOR_VLAN_DW 1
625+#define WF_TX_DESCRIPTOR_VLAN_ADDR 4
626+#define WF_TX_DESCRIPTOR_VLAN_MASK 0x00080000 // 19-19
627+#define WF_TX_DESCRIPTOR_VLAN_SHIFT 19
628+#define WF_TX_DESCRIPTOR_ETYP_DW 1
629+#define WF_TX_DESCRIPTOR_ETYP_ADDR 4
630+#define WF_TX_DESCRIPTOR_ETYP_MASK 0x00100000 // 20-20
631+#define WF_TX_DESCRIPTOR_ETYP_SHIFT 20
632+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_DW 1
633+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_ADDR 4
634+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_MASK 0x01e00000 // 24-21
635+#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_SHIFT 21
636+#define WF_TX_DESCRIPTOR_OM_DW 1
637+#define WF_TX_DESCRIPTOR_OM_ADDR 4
638+#define WF_TX_DESCRIPTOR_OM_MASK 0x7e000000 // 30-25
639+#define WF_TX_DESCRIPTOR_OM_SHIFT 25
640+#define WF_TX_DESCRIPTOR_FR_DW 1
641+#define WF_TX_DESCRIPTOR_FR_ADDR 4
642+#define WF_TX_DESCRIPTOR_FR_MASK 0x80000000 // 31-31
643+#define WF_TX_DESCRIPTOR_FR_SHIFT 31
644+// DW2
645+#define WF_TX_DESCRIPTOR_SUBTYPE_DW 2
646+#define WF_TX_DESCRIPTOR_SUBTYPE_ADDR 8
647+#define WF_TX_DESCRIPTOR_SUBTYPE_MASK 0x0000000f // 3- 0
648+#define WF_TX_DESCRIPTOR_SUBTYPE_SHIFT 0
649+#define WF_TX_DESCRIPTOR_FTYPE_DW 2
650+#define WF_TX_DESCRIPTOR_FTYPE_ADDR 8
651+#define WF_TX_DESCRIPTOR_FTYPE_MASK 0x00000030 // 5- 4
652+#define WF_TX_DESCRIPTOR_FTYPE_SHIFT 4
653+#define WF_TX_DESCRIPTOR_BF_TYPE_DW 2
654+#define WF_TX_DESCRIPTOR_BF_TYPE_ADDR 8
655+#define WF_TX_DESCRIPTOR_BF_TYPE_MASK 0x000000c0 // 7- 6
656+#define WF_TX_DESCRIPTOR_BF_TYPE_SHIFT 6
657+#define WF_TX_DESCRIPTOR_OM_MAP_DW 2
658+#define WF_TX_DESCRIPTOR_OM_MAP_ADDR 8
659+#define WF_TX_DESCRIPTOR_OM_MAP_MASK 0x00000100 // 8- 8
660+#define WF_TX_DESCRIPTOR_OM_MAP_SHIFT 8
661+#define WF_TX_DESCRIPTOR_RTS_DW 2
662+#define WF_TX_DESCRIPTOR_RTS_ADDR 8
663+#define WF_TX_DESCRIPTOR_RTS_MASK 0x00000200 // 9- 9
664+#define WF_TX_DESCRIPTOR_RTS_SHIFT 9
665+#define WF_TX_DESCRIPTOR_HEADER_PADDING_DW 2
666+#define WF_TX_DESCRIPTOR_HEADER_PADDING_ADDR 8
667+#define WF_TX_DESCRIPTOR_HEADER_PADDING_MASK 0x00000c00 // 11-10
668+#define WF_TX_DESCRIPTOR_HEADER_PADDING_SHIFT 10
669+#define WF_TX_DESCRIPTOR_DU_DW 2
670+#define WF_TX_DESCRIPTOR_DU_ADDR 8
671+#define WF_TX_DESCRIPTOR_DU_MASK 0x00001000 // 12-12
672+#define WF_TX_DESCRIPTOR_DU_SHIFT 12
673+#define WF_TX_DESCRIPTOR_HE_DW 2
674+#define WF_TX_DESCRIPTOR_HE_ADDR 8
675+#define WF_TX_DESCRIPTOR_HE_MASK 0x00002000 // 13-13
676+#define WF_TX_DESCRIPTOR_HE_SHIFT 13
677+#define WF_TX_DESCRIPTOR_FRAG_DW 2
678+#define WF_TX_DESCRIPTOR_FRAG_ADDR 8
679+#define WF_TX_DESCRIPTOR_FRAG_MASK 0x0000c000 // 15-14
680+#define WF_TX_DESCRIPTOR_FRAG_SHIFT 14
681+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_DW 2
682+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_ADDR 8
683+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_MASK 0x03ff0000 // 25-16
684+#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_SHIFT 16
685+#define WF_TX_DESCRIPTOR_POWER_OFFSET_DW 2
686+#define WF_TX_DESCRIPTOR_POWER_OFFSET_ADDR 8
687+#define WF_TX_DESCRIPTOR_POWER_OFFSET_MASK 0xfc000000 // 31-26
688+#define WF_TX_DESCRIPTOR_POWER_OFFSET_SHIFT 26
689+// DW3
690+#define WF_TX_DESCRIPTOR_NA_DW 3
691+#define WF_TX_DESCRIPTOR_NA_ADDR 12
692+#define WF_TX_DESCRIPTOR_NA_MASK 0x00000001 // 0- 0
693+#define WF_TX_DESCRIPTOR_NA_SHIFT 0
694+#define WF_TX_DESCRIPTOR_PF_DW 3
695+#define WF_TX_DESCRIPTOR_PF_ADDR 12
696+#define WF_TX_DESCRIPTOR_PF_MASK 0x00000002 // 1- 1
697+#define WF_TX_DESCRIPTOR_PF_SHIFT 1
698+#define WF_TX_DESCRIPTOR_EMRD_DW 3
699+#define WF_TX_DESCRIPTOR_EMRD_ADDR 12
700+#define WF_TX_DESCRIPTOR_EMRD_MASK 0x00000004 // 2- 2
701+#define WF_TX_DESCRIPTOR_EMRD_SHIFT 2
702+#define WF_TX_DESCRIPTOR_EEOSP_DW 3
703+#define WF_TX_DESCRIPTOR_EEOSP_ADDR 12
704+#define WF_TX_DESCRIPTOR_EEOSP_MASK 0x00000008 // 3- 3
705+#define WF_TX_DESCRIPTOR_EEOSP_SHIFT 3
706+#define WF_TX_DESCRIPTOR_BM_DW 3
707+#define WF_TX_DESCRIPTOR_BM_ADDR 12
708+#define WF_TX_DESCRIPTOR_BM_MASK 0x00000010 // 4- 4
709+#define WF_TX_DESCRIPTOR_BM_SHIFT 4
710+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_DW 3
711+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_ADDR 12
712+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_MASK 0x00000020 // 5- 5
713+#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_SHIFT 5
714+#define WF_TX_DESCRIPTOR_TX_COUNT_DW 3
715+#define WF_TX_DESCRIPTOR_TX_COUNT_ADDR 12
716+#define WF_TX_DESCRIPTOR_TX_COUNT_MASK 0x000007c0 // 10- 6
717+#define WF_TX_DESCRIPTOR_TX_COUNT_SHIFT 6
718+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_DW 3
719+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_ADDR 12
720+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_MASK 0x0000f800 // 15-11
721+#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_SHIFT 11
722+#define WF_TX_DESCRIPTOR_SN_DW 3
723+#define WF_TX_DESCRIPTOR_SN_ADDR 12
724+#define WF_TX_DESCRIPTOR_SN_MASK 0x0fff0000 // 27-16
725+#define WF_TX_DESCRIPTOR_SN_SHIFT 16
726+#define WF_TX_DESCRIPTOR_BA_DIS_DW 3
727+#define WF_TX_DESCRIPTOR_BA_DIS_ADDR 12
728+#define WF_TX_DESCRIPTOR_BA_DIS_MASK 0x10000000 // 28-28
729+#define WF_TX_DESCRIPTOR_BA_DIS_SHIFT 28
730+#define WF_TX_DESCRIPTOR_PM_DW 3
731+#define WF_TX_DESCRIPTOR_PM_ADDR 12
732+#define WF_TX_DESCRIPTOR_PM_MASK 0x20000000 // 29-29
733+#define WF_TX_DESCRIPTOR_PM_SHIFT 29
734+#define WF_TX_DESCRIPTOR_PN_VLD_DW 3
735+#define WF_TX_DESCRIPTOR_PN_VLD_ADDR 12
736+#define WF_TX_DESCRIPTOR_PN_VLD_MASK 0x40000000 // 30-30
737+#define WF_TX_DESCRIPTOR_PN_VLD_SHIFT 30
738+#define WF_TX_DESCRIPTOR_SN_VLD_DW 3
739+#define WF_TX_DESCRIPTOR_SN_VLD_ADDR 12
740+#define WF_TX_DESCRIPTOR_SN_VLD_MASK 0x80000000 // 31-31
741+#define WF_TX_DESCRIPTOR_SN_VLD_SHIFT 31
742+// DW4
743+#define WF_TX_DESCRIPTOR_PN_31_0__DW 4
744+#define WF_TX_DESCRIPTOR_PN_31_0__ADDR 16
745+#define WF_TX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0
746+#define WF_TX_DESCRIPTOR_PN_31_0__SHIFT 0
747+// DW5
748+#define WF_TX_DESCRIPTOR_PID_DW 5
749+#define WF_TX_DESCRIPTOR_PID_ADDR 20
750+#define WF_TX_DESCRIPTOR_PID_MASK 0x000000ff // 7- 0
751+#define WF_TX_DESCRIPTOR_PID_SHIFT 0
752+#define WF_TX_DESCRIPTOR_TXSFM_DW 5
753+#define WF_TX_DESCRIPTOR_TXSFM_ADDR 20
754+#define WF_TX_DESCRIPTOR_TXSFM_MASK 0x00000100 // 8- 8
755+#define WF_TX_DESCRIPTOR_TXSFM_SHIFT 8
756+#define WF_TX_DESCRIPTOR_TXS2M_DW 5
757+#define WF_TX_DESCRIPTOR_TXS2M_ADDR 20
758+#define WF_TX_DESCRIPTOR_TXS2M_MASK 0x00000200 // 9- 9
759+#define WF_TX_DESCRIPTOR_TXS2M_SHIFT 9
760+#define WF_TX_DESCRIPTOR_TXS2H_DW 5
761+#define WF_TX_DESCRIPTOR_TXS2H_ADDR 20
762+#define WF_TX_DESCRIPTOR_TXS2H_MASK 0x00000400 // 10-10
763+#define WF_TX_DESCRIPTOR_TXS2H_SHIFT 10
764+#define WF_TX_DESCRIPTOR_FBCZ_DW 5
765+#define WF_TX_DESCRIPTOR_FBCZ_ADDR 20
766+#define WF_TX_DESCRIPTOR_FBCZ_MASK 0x00001000 // 12-12
767+#define WF_TX_DESCRIPTOR_FBCZ_SHIFT 12
768+#define WF_TX_DESCRIPTOR_BYPASS_RBB_DW 5
769+#define WF_TX_DESCRIPTOR_BYPASS_RBB_ADDR 20
770+#define WF_TX_DESCRIPTOR_BYPASS_RBB_MASK 0x00002000 // 13-13
771+#define WF_TX_DESCRIPTOR_BYPASS_RBB_SHIFT 13
772+#define WF_TX_DESCRIPTOR_BYPASS_TBB_DW 5
773+#define WF_TX_DESCRIPTOR_BYPASS_TBB_ADDR 20
774+#define WF_TX_DESCRIPTOR_BYPASS_TBB_MASK 0x00004000 // 14-14
775+#define WF_TX_DESCRIPTOR_BYPASS_TBB_SHIFT 14
776+#define WF_TX_DESCRIPTOR_FL_DW 5
777+#define WF_TX_DESCRIPTOR_FL_ADDR 20
778+#define WF_TX_DESCRIPTOR_FL_MASK 0x00008000 // 15-15
779+#define WF_TX_DESCRIPTOR_FL_SHIFT 15
780+#define WF_TX_DESCRIPTOR_PN_47_32__DW 5
781+#define WF_TX_DESCRIPTOR_PN_47_32__ADDR 20
782+#define WF_TX_DESCRIPTOR_PN_47_32__MASK 0xffff0000 // 31-16
783+#define WF_TX_DESCRIPTOR_PN_47_32__SHIFT 16
784+// DW6
785+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_DW 6
786+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_ADDR 24
787+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_MASK 0x00000002 // 1- 1
788+#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_SHIFT 1
789+#define WF_TX_DESCRIPTOR_DAS_DW 6
790+#define WF_TX_DESCRIPTOR_DAS_ADDR 24
791+#define WF_TX_DESCRIPTOR_DAS_MASK 0x00000004 // 2- 2
792+#define WF_TX_DESCRIPTOR_DAS_SHIFT 2
793+#define WF_TX_DESCRIPTOR_DIS_MAT_DW 6
794+#define WF_TX_DESCRIPTOR_DIS_MAT_ADDR 24
795+#define WF_TX_DESCRIPTOR_DIS_MAT_MASK 0x00000008 // 3- 3
796+#define WF_TX_DESCRIPTOR_DIS_MAT_SHIFT 3
797+#define WF_TX_DESCRIPTOR_MSDU_COUNT_DW 6
798+#define WF_TX_DESCRIPTOR_MSDU_COUNT_ADDR 24
799+#define WF_TX_DESCRIPTOR_MSDU_COUNT_MASK 0x000003f0 // 9- 4
800+#define WF_TX_DESCRIPTOR_MSDU_COUNT_SHIFT 4
801+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_DW 6
802+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_ADDR 24
803+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_MASK 0x00007c00 // 14-10
804+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_SHIFT 10
805+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_DW 6
806+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_ADDR 24
807+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_MASK 0x00008000 // 15-15
808+#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_SHIFT 15
809+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_DW 6
810+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_ADDR 24
811+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_MASK 0x003f0000 // 21-16
812+#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_SHIFT 16
813+#define WF_TX_DESCRIPTOR_BW_DW 6
814+#define WF_TX_DESCRIPTOR_BW_ADDR 24
815+#define WF_TX_DESCRIPTOR_BW_MASK 0x03c00000 // 25-22
816+#define WF_TX_DESCRIPTOR_BW_SHIFT 22
817+#define WF_TX_DESCRIPTOR_VTA_DW 6
818+#define WF_TX_DESCRIPTOR_VTA_ADDR 24
819+#define WF_TX_DESCRIPTOR_VTA_MASK 0x10000000 // 28-28
820+#define WF_TX_DESCRIPTOR_VTA_SHIFT 28
821+#define WF_TX_DESCRIPTOR_SRC_DW 6
822+#define WF_TX_DESCRIPTOR_SRC_ADDR 24
823+#define WF_TX_DESCRIPTOR_SRC_MASK 0xc0000000 // 31-30
824+#define WF_TX_DESCRIPTOR_SRC_SHIFT 30
825+// DW7
826+#define WF_TX_DESCRIPTOR_SW_TX_TIME_DW 7
827+#define WF_TX_DESCRIPTOR_SW_TX_TIME_ADDR 28
828+#define WF_TX_DESCRIPTOR_SW_TX_TIME_MASK 0x000003ff // 9- 0
829+#define WF_TX_DESCRIPTOR_SW_TX_TIME_SHIFT 0
830+#define WF_TX_DESCRIPTOR_UT_DW 7
831+#define WF_TX_DESCRIPTOR_UT_ADDR 28
832+#define WF_TX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15
833+#define WF_TX_DESCRIPTOR_UT_SHIFT 15
834+#define WF_TX_DESCRIPTOR_CTXD_CNT_DW 7
835+#define WF_TX_DESCRIPTOR_CTXD_CNT_ADDR 28
836+#define WF_TX_DESCRIPTOR_CTXD_CNT_MASK 0x03c00000 // 25-22
837+#define WF_TX_DESCRIPTOR_CTXD_CNT_SHIFT 22
838+#define WF_TX_DESCRIPTOR_CTXD_DW 7
839+#define WF_TX_DESCRIPTOR_CTXD_ADDR 28
840+#define WF_TX_DESCRIPTOR_CTXD_MASK 0x04000000 // 26-26
841+#define WF_TX_DESCRIPTOR_CTXD_SHIFT 26
842+#define WF_TX_DESCRIPTOR_HM_DW 7
843+#define WF_TX_DESCRIPTOR_HM_ADDR 28
844+#define WF_TX_DESCRIPTOR_HM_MASK 0x08000000 // 27-27
845+#define WF_TX_DESCRIPTOR_HM_SHIFT 27
846+#define WF_TX_DESCRIPTOR_DP_DW 7
847+#define WF_TX_DESCRIPTOR_DP_ADDR 28
848+#define WF_TX_DESCRIPTOR_DP_MASK 0x10000000 // 28-28
849+#define WF_TX_DESCRIPTOR_DP_SHIFT 28
850+#define WF_TX_DESCRIPTOR_IP_DW 7
851+#define WF_TX_DESCRIPTOR_IP_ADDR 28
852+#define WF_TX_DESCRIPTOR_IP_MASK 0x20000000 // 29-29
853+#define WF_TX_DESCRIPTOR_IP_SHIFT 29
854+#define WF_TX_DESCRIPTOR_TXD_LEN_DW 7
855+#define WF_TX_DESCRIPTOR_TXD_LEN_ADDR 28
856+#define WF_TX_DESCRIPTOR_TXD_LEN_MASK 0xc0000000 // 31-30
857+#define WF_TX_DESCRIPTOR_TXD_LEN_SHIFT 30
858+// DW8
859+#define WF_TX_DESCRIPTOR_MSDU0_DW 8
860+#define WF_TX_DESCRIPTOR_MSDU0_ADDR 32
861+#define WF_TX_DESCRIPTOR_MSDU0_MASK 0x0000ffff // 15- 0
862+#define WF_TX_DESCRIPTOR_MSDU0_SHIFT 0
863+#define WF_TX_DESCRIPTOR_MSDU1_DW 8
864+#define WF_TX_DESCRIPTOR_MSDU1_ADDR 32
865+#define WF_TX_DESCRIPTOR_MSDU1_MASK 0xffff0000 // 31-16
866+#define WF_TX_DESCRIPTOR_MSDU1_SHIFT 16
867+// DW9
868+#define WF_TX_DESCRIPTOR_MSDU2_DW 9
869+#define WF_TX_DESCRIPTOR_MSDU2_ADDR 36
870+#define WF_TX_DESCRIPTOR_MSDU2_MASK 0x0000ffff // 15- 0
871+#define WF_TX_DESCRIPTOR_MSDU2_SHIFT 0
872+#define WF_TX_DESCRIPTOR_MSDU3_DW 9
873+#define WF_TX_DESCRIPTOR_MSDU3_ADDR 36
874+#define WF_TX_DESCRIPTOR_MSDU3_MASK 0xffff0000 // 31-16
875+#define WF_TX_DESCRIPTOR_MSDU3_SHIFT 16
876+// DW10
877+#define WF_TX_DESCRIPTOR_TXP0_DW 10
878+#define WF_TX_DESCRIPTOR_TXP0_ADDR 40
879+#define WF_TX_DESCRIPTOR_TXP0_MASK 0xffffffff // 31- 0
880+#define WF_TX_DESCRIPTOR_TXP0_SHIFT 0
881+// DW11
882+// DO NOT process repeat field(txp[0])
883+#define WF_TX_DESCRIPTOR_TXP1_DW 11
884+#define WF_TX_DESCRIPTOR_TXP1_ADDR 44
885+#define WF_TX_DESCRIPTOR_TXP1_MASK 0xffff0000 // 31-16
886+#define WF_TX_DESCRIPTOR_TXP1_SHIFT 16
887+// DW12
888+// DO NOT process repeat field(txp[1])
889+// DW13
890+#define WF_TX_DESCRIPTOR_TXP2_DW 13
891+#define WF_TX_DESCRIPTOR_TXP2_ADDR 52
892+#define WF_TX_DESCRIPTOR_TXP2_MASK 0xffffffff // 31- 0
893+#define WF_TX_DESCRIPTOR_TXP2_SHIFT 0
894+// DW14
895+// DO NOT process repeat field(txp[2])
896+#define WF_TX_DESCRIPTOR_TXP3_DW 14
897+#define WF_TX_DESCRIPTOR_TXP3_ADDR 56
898+#define WF_TX_DESCRIPTOR_TXP3_MASK 0xffff0000 // 31-16
899+#define WF_TX_DESCRIPTOR_TXP3_SHIFT 16
900+// DW15
901+// DO NOT process repeat field(txp[3])
902+// DW16
903+#define WF_TX_DESCRIPTOR_MSDU4_DW 16
904+#define WF_TX_DESCRIPTOR_MSDU4_ADDR 64
905+#define WF_TX_DESCRIPTOR_MSDU4_MASK 0x0000ffff // 15- 0
906+#define WF_TX_DESCRIPTOR_MSDU4_SHIFT 0
907+#define WF_TX_DESCRIPTOR_MSDU5_DW 16
908+#define WF_TX_DESCRIPTOR_MSDU5_ADDR 64
909+#define WF_TX_DESCRIPTOR_MSDU5_MASK 0xffff0000 // 31-16
910+#define WF_TX_DESCRIPTOR_MSDU5_SHIFT 16
911+// DW17
912+#define WF_TX_DESCRIPTOR_MSDU6_DW 17
913+#define WF_TX_DESCRIPTOR_MSDU6_ADDR 68
914+#define WF_TX_DESCRIPTOR_MSDU6_MASK 0x0000ffff // 15- 0
915+#define WF_TX_DESCRIPTOR_MSDU6_SHIFT 0
916+#define WF_TX_DESCRIPTOR_MSDU7_DW 17
917+#define WF_TX_DESCRIPTOR_MSDU7_ADDR 68
918+#define WF_TX_DESCRIPTOR_MSDU7_MASK 0xffff0000 // 31-16
919+#define WF_TX_DESCRIPTOR_MSDU7_SHIFT 16
920+// DW18
921+#define WF_TX_DESCRIPTOR_TXP4_DW 18
922+#define WF_TX_DESCRIPTOR_TXP4_ADDR 72
923+#define WF_TX_DESCRIPTOR_TXP4_MASK 0xffffffff // 31- 0
924+#define WF_TX_DESCRIPTOR_TXP4_SHIFT 0
925+// DW19
926+// DO NOT process repeat field(txp[4])
927+#define WF_TX_DESCRIPTOR_TXP5_DW 19
928+#define WF_TX_DESCRIPTOR_TXP5_ADDR 76
929+#define WF_TX_DESCRIPTOR_TXP5_MASK 0xffff0000 // 31-16
930+#define WF_TX_DESCRIPTOR_TXP5_SHIFT 16
931+// DW20
932+// DO NOT process repeat field(txp[5])
933+// DW21
934+#define WF_TX_DESCRIPTOR_TXP6_DW 21
935+#define WF_TX_DESCRIPTOR_TXP6_ADDR 84
936+#define WF_TX_DESCRIPTOR_TXP6_MASK 0xffffffff // 31- 0
937+#define WF_TX_DESCRIPTOR_TXP6_SHIFT 0
938+// DW22
939+// DO NOT process repeat field(txp[6])
940+#define WF_TX_DESCRIPTOR_TXP7_DW 22
941+#define WF_TX_DESCRIPTOR_TXP7_ADDR 88
942+#define WF_TX_DESCRIPTOR_TXP7_MASK 0xffff0000 // 31-16
943+#define WF_TX_DESCRIPTOR_TXP7_SHIFT 16
944+// DW23
945+// DO NOT process repeat field(txp[7])
946+// DW24
947+#define WF_TX_DESCRIPTOR_TXP8_DW 24
948+#define WF_TX_DESCRIPTOR_TXP8_ADDR 96
949+#define WF_TX_DESCRIPTOR_TXP8_MASK 0xffffffff // 31- 0
950+#define WF_TX_DESCRIPTOR_TXP8_SHIFT 0
951+// DW25
952+// DO NOT process repeat field(txp[8])
953+#define WF_TX_DESCRIPTOR_TXP9_DW 25
954+#define WF_TX_DESCRIPTOR_TXP9_ADDR 100
955+#define WF_TX_DESCRIPTOR_TXP9_MASK 0xffff0000 // 31-16
956+#define WF_TX_DESCRIPTOR_TXP9_SHIFT 16
957+// DW26
958+// DO NOT process repeat field(txp[9])
959+// DW27
960+#define WF_TX_DESCRIPTOR_TXP10_DW 27
961+#define WF_TX_DESCRIPTOR_TXP10_ADDR 108
962+#define WF_TX_DESCRIPTOR_TXP10_MASK 0xffffffff // 31- 0
963+#define WF_TX_DESCRIPTOR_TXP10_SHIFT 0
964+// DW28
965+// DO NOT process repeat field(txp[10])
966+#define WF_TX_DESCRIPTOR_TXP11_DW 28
967+#define WF_TX_DESCRIPTOR_TXP11_ADDR 112
968+#define WF_TX_DESCRIPTOR_TXP11_MASK 0xffff0000 // 31-16
969+#define WF_TX_DESCRIPTOR_TXP11_SHIFT 16
970+// DW29
971+// DO NOT process repeat field(txp[11])
972+// DW30
973+#define WF_TX_DESCRIPTOR_TXP12_DW 30
974+#define WF_TX_DESCRIPTOR_TXP12_ADDR 120
975+#define WF_TX_DESCRIPTOR_TXP12_MASK 0xffffffff // 31- 0
976+#define WF_TX_DESCRIPTOR_TXP12_SHIFT 0
977+// DW31
978+// DO NOT process repeat field(txp[12])
979+#define WF_TX_DESCRIPTOR_TXP13_DW 31
980+#define WF_TX_DESCRIPTOR_TXP13_ADDR 124
981+#define WF_TX_DESCRIPTOR_TXP13_MASK 0xffff0000 // 31-16
982+#define WF_TX_DESCRIPTOR_TXP13_SHIFT 16
983+// DW32
984+// DO NOT process repeat field(txp[13])
985+// DW33
986+#define WF_TX_DESCRIPTOR_TXP14_DW 33
987+#define WF_TX_DESCRIPTOR_TXP14_ADDR 132
988+#define WF_TX_DESCRIPTOR_TXP14_MASK 0xffffffff // 31- 0
989+#define WF_TX_DESCRIPTOR_TXP14_SHIFT 0
990+// DW34
991+// DO NOT process repeat field(txp[14])
992+#define WF_TX_DESCRIPTOR_TXP15_DW 34
993+#define WF_TX_DESCRIPTOR_TXP15_ADDR 136
994+#define WF_TX_DESCRIPTOR_TXP15_MASK 0xffff0000 // 31-16
995+#define WF_TX_DESCRIPTOR_TXP15_SHIFT 16
996+// DW35
997+// DO NOT process repeat field(txp[15])
998+// DW36
999+#define WF_TX_DESCRIPTOR_TXP16_DW 36
1000+#define WF_TX_DESCRIPTOR_TXP16_ADDR 144
1001+#define WF_TX_DESCRIPTOR_TXP16_MASK 0xffffffff // 31- 0
1002+#define WF_TX_DESCRIPTOR_TXP16_SHIFT 0
1003+// DW37
1004+// DO NOT process repeat field(txp[16])
1005+#define WF_TX_DESCRIPTOR_TXP17_DW 37
1006+#define WF_TX_DESCRIPTOR_TXP17_ADDR 148
1007+#define WF_TX_DESCRIPTOR_TXP17_MASK 0xffff0000 // 31-16
1008+#define WF_TX_DESCRIPTOR_TXP17_SHIFT 16
1009+// DW38
1010+// DO NOT process repeat field(txp[17])
1011+// DW39
1012+#define WF_TX_DESCRIPTOR_TXP18_DW 39
1013+#define WF_TX_DESCRIPTOR_TXP18_ADDR 156
1014+#define WF_TX_DESCRIPTOR_TXP18_MASK 0xffffffff // 31- 0
1015+#define WF_TX_DESCRIPTOR_TXP18_SHIFT 0
1016+// DW40
1017+// DO NOT process repeat field(txp[18])
1018+#define WF_TX_DESCRIPTOR_TXP19_DW 40
1019+#define WF_TX_DESCRIPTOR_TXP19_ADDR 160
1020+#define WF_TX_DESCRIPTOR_TXP19_MASK 0xffff0000 // 31-16
1021+#define WF_TX_DESCRIPTOR_TXP19_SHIFT 16
1022+// DW41
1023+// DO NOT process repeat field(txp[19])
1024+// DW42
1025+#define WF_TX_DESCRIPTOR_TXP20_DW 42
1026+#define WF_TX_DESCRIPTOR_TXP20_ADDR 168
1027+#define WF_TX_DESCRIPTOR_TXP20_MASK 0xffffffff // 31- 0
1028+#define WF_TX_DESCRIPTOR_TXP20_SHIFT 0
1029+// DW43
1030+// DO NOT process repeat field(txp[20])
1031+#define WF_TX_DESCRIPTOR_TXP21_DW 43
1032+#define WF_TX_DESCRIPTOR_TXP21_ADDR 172
1033+#define WF_TX_DESCRIPTOR_TXP21_MASK 0xffff0000 // 31-16
1034+#define WF_TX_DESCRIPTOR_TXP21_SHIFT 16
1035+// DW44
1036+// DO NOT process repeat field(txp[21])
1037+// DW45
1038+#define WF_TX_DESCRIPTOR_TXP22_DW 45
1039+#define WF_TX_DESCRIPTOR_TXP22_ADDR 180
1040+#define WF_TX_DESCRIPTOR_TXP22_MASK 0xffffffff // 31- 0
1041+#define WF_TX_DESCRIPTOR_TXP22_SHIFT 0
1042+// DW46
1043+// DO NOT process repeat field(txp[22])
1044+#define WF_TX_DESCRIPTOR_TXP23_DW 46
1045+#define WF_TX_DESCRIPTOR_TXP23_ADDR 184
1046+#define WF_TX_DESCRIPTOR_TXP23_MASK 0xffff0000 // 31-16
1047+#define WF_TX_DESCRIPTOR_TXP23_SHIFT 16
1048+// DW47
1049+// DO NOT process repeat field(txp[23])
1050+// DW48
1051+#define WF_TX_DESCRIPTOR_TXP24_DW 48
1052+#define WF_TX_DESCRIPTOR_TXP24_ADDR 192
1053+#define WF_TX_DESCRIPTOR_TXP24_MASK 0xffffffff // 31- 0
1054+#define WF_TX_DESCRIPTOR_TXP24_SHIFT 0
1055+// DW49
1056+// DO NOT process repeat field(txp[24])
1057+#define WF_TX_DESCRIPTOR_TXP25_DW 49
1058+#define WF_TX_DESCRIPTOR_TXP25_ADDR 196
1059+#define WF_TX_DESCRIPTOR_TXP25_MASK 0xffff0000 // 31-16
1060+#define WF_TX_DESCRIPTOR_TXP25_SHIFT 16
1061+// DW50
1062+// DO NOT process repeat field(txp[25])
1063+// DW51
1064+#define WF_TX_DESCRIPTOR_TXP26_DW 51
1065+#define WF_TX_DESCRIPTOR_TXP26_ADDR 204
1066+#define WF_TX_DESCRIPTOR_TXP26_MASK 0xffffffff // 31- 0
1067+#define WF_TX_DESCRIPTOR_TXP26_SHIFT 0
1068+// DW52
1069+// DO NOT process repeat field(txp[26])
1070+#define WF_TX_DESCRIPTOR_TXP27_DW 52
1071+#define WF_TX_DESCRIPTOR_TXP27_ADDR 208
1072+#define WF_TX_DESCRIPTOR_TXP27_MASK 0xffff0000 // 31-16
1073+#define WF_TX_DESCRIPTOR_TXP27_SHIFT 16
1074+// DW53
1075+// DO NOT process repeat field(txp[27])
1076+// DW54
1077+#define WF_TX_DESCRIPTOR_TXP28_DW 54
1078+#define WF_TX_DESCRIPTOR_TXP28_ADDR 216
1079+#define WF_TX_DESCRIPTOR_TXP28_MASK 0xffffffff // 31- 0
1080+#define WF_TX_DESCRIPTOR_TXP28_SHIFT 0
1081+// DW55
1082+// DO NOT process repeat field(txp[28])
1083+#define WF_TX_DESCRIPTOR_TXP29_DW 55
1084+#define WF_TX_DESCRIPTOR_TXP29_ADDR 220
1085+#define WF_TX_DESCRIPTOR_TXP29_MASK 0xffff0000 // 31-16
1086+#define WF_TX_DESCRIPTOR_TXP29_SHIFT 16
1087+// DW56
1088+// DO NOT process repeat field(txp[29])
1089+// DW57
1090+#define WF_TX_DESCRIPTOR_TXP30_DW 57
1091+#define WF_TX_DESCRIPTOR_TXP30_ADDR 228
1092+#define WF_TX_DESCRIPTOR_TXP30_MASK 0xffffffff // 31- 0
1093+#define WF_TX_DESCRIPTOR_TXP30_SHIFT 0
1094+// DW58
1095+// DO NOT process repeat field(txp[30])
1096+#define WF_TX_DESCRIPTOR_TXP31_DW 58
1097+#define WF_TX_DESCRIPTOR_TXP31_ADDR 232
1098+#define WF_TX_DESCRIPTOR_TXP31_MASK 0xffff0000 // 31-16
1099+#define WF_TX_DESCRIPTOR_TXP31_SHIFT 16
1100+// DW59
1101+// DO NOT process repeat field(txp[31])
1102+
1103+/* TXP PAO */
1104+#define HIF_TXP_V2_SIZE (24 * 4)
1105+/* DW0 */
1106+#define HIF_TXD_VERSION_SHIFT 19
1107+#define HIF_TXD_VERSION_MASK 0x00780000
1108+
1109+/* DW8 */
1110+#define HIF_TXP_PRIORITY_SHIFT 0
1111+#define HIF_TXP_PRIORITY_MASK 0x00000001
1112+#define HIF_TXP_FIXED_RATE_SHIFT 1
1113+#define HIF_TXP_FIXED_RATE_MASK 0x00000002
1114+#define HIF_TXP_TCP_SHIFT 2
1115+#define HIF_TXP_TCP_MASK 0x00000004
1116+#define HIF_TXP_NON_CIPHER_SHIFT 3
1117+#define HIF_TXP_NON_CIPHER_MASK 0x00000008
1118+#define HIF_TXP_VLAN_SHIFT 4
1119+#define HIF_TXP_VLAN_MASK 0x00000010
1120+#define HIF_TXP_BC_MC_FLAG_SHIFT 5
1121+#define HIF_TXP_BC_MC_FLAG_MASK 0x00000060
1122+#define HIF_TXP_FR_HOST_SHIFT 7
1123+#define HIF_TXP_FR_HOST_MASK 0x00000080
1124+#define HIF_TXP_ETYPE_SHIFT 8
1125+#define HIF_TXP_ETYPE_MASK 0x00000100
1126+#define HIF_TXP_TXP_AMSDU_SHIFT 9
1127+#define HIF_TXP_TXP_AMSDU_MASK 0x00000200
1128+#define HIF_TXP_TXP_MC_CLONE_SHIFT 10
1129+#define HIF_TXP_TXP_MC_CLONE_MASK 0x00000400
1130+#define HIF_TXP_TOKEN_ID_SHIFT 16
1131+#define HIF_TXP_TOKEN_ID_MASK 0xffff0000
1132+
1133+/* DW9 */
1134+#define HIF_TXP_BSS_IDX_SHIFT 0
1135+#define HIF_TXP_BSS_IDX_MASK 0x000000ff
1136+#define HIF_TXP_USER_PRIORITY_SHIFT 8
1137+#define HIF_TXP_USER_PRIORITY_MASK 0x0000ff00
1138+#define HIF_TXP_BUF_NUM_SHIFT 16
1139+#define HIF_TXP_BUF_NUM_MASK 0x001f0000
1140+#define HIF_TXP_MSDU_CNT_SHIFT 21
1141+#define HIF_TXP_MSDU_CNT_MASK 0x03e00000
1142+#define HIF_TXP_SRC_SHIFT 26
1143+#define HIF_TXP_SRC_MASK 0x0c000000
1144+
1145+/* DW10 */
1146+#define HIF_TXP_ETH_TYPE_SHIFT 0
1147+#define HIF_TXP_ETH_TYPE_MASK 0x0000ffff
1148+#define HIF_TXP_WLAN_IDX_SHIFT 16
1149+#define HIF_TXP_WLAN_IDX_MASK 0x0fff0000
1150+
1151+/* DW11 */
1152+#define HIF_TXP_PPE_INFO_SHIFT 0
1153+#define HIF_TXP_PPE_INFO_MASK 0xffffffff
1154+
1155+/* DW12 - DW31 */
1156+#define HIF_TXP_BUF_PTR0_L_SHIFT 0
1157+#define HIF_TXP_BUF_PTR0_L_MASK 0xffffffff
1158+#define HIF_TXP_BUF_LEN0_SHIFT 0
1159+#define HIF_TXP_BUF_LEN0_MASK 0x00000fff
1160+#define HIF_TXP_BUF_PTR0_H_SHIFT 12
1161+#define HIF_TXP_BUF_PTR0_H_MASK 0x0000f000
1162+#define HIF_TXP_BUF_LEN1_SHIFT 16
1163+#define HIF_TXP_BUF_LEN1_MASK 0x0fff0000
1164+#define HIF_TXP_BUF_PTR1_H_SHIFT 28
1165+#define HIF_TXP_BUF_PTR1_H_MASK 0xf0000000
1166+#define HIF_TXP_BUF_PTR1_L_SHIFT 0
1167+#define HIF_TXP_BUF_PTR1_L_MASK 0xffffffff
1168+
1169+/* DW31 */
1170+#define HIF_TXP_ML_SHIFT 16
1171+#define HIF_TXP_ML_MASK 0xffff0000
1172+
1173+#endif
1174+
1175+#endif
1176diff --git a/mt7996/mtk_debugfs_i.c b/mt7996/mtk_debugfs_i.c
1177new file mode 100644
1178index 00000000..ea412cd5
1179--- /dev/null
1180+++ b/mt7996/mtk_debugfs_i.c
1181@@ -0,0 +1,720 @@
1182+#include <linux/inet.h>
1183+#include "mt7996.h"
1184+#include "../mt76.h"
1185+#include "mcu.h"
1186+#include "mac.h"
1187+#include "eeprom.h"
1188+#include "mtk_debug.h"
1189+#include "mtk_debug_i.h"
1190+#include "mtk_mcu.h"
1191+
1192+#ifdef CONFIG_MTK_DEBUG
1193+
1194+#define info_or_seq_printf(seq, fmt, ...) do { \
1195+ if (seq) \
1196+ seq_printf(seq, fmt, ##__VA_ARGS__); \
1197+ else \
1198+ pr_info(fmt, ##__VA_ARGS__); \
1199+} while (0)
1200+
1201+static void info_or_seq_hex_dump(struct seq_file *seq, int prefix_type,
1202+ int rowsize, int groupsize, const void *buf,
1203+ size_t len, bool ascii)
1204+{
1205+ if (seq)
1206+ seq_hex_dump(seq, "", prefix_type, rowsize, groupsize,
1207+ buf, len, ascii);
1208+ else
1209+ print_hex_dump(KERN_INFO, "", prefix_type,
1210+ rowsize, groupsize, buf, len, ascii);
1211+}
1212+
1213+//bmac dump mac txp
1214+static void mt7996_dump_bmac_mac_txp_info(struct seq_file *s, struct mt7996_dev *dev,
1215+ __le32 *txp)
1216+{
1217+ struct mt7996_txp_token {
1218+ __le16 msdu[4];
1219+ } *msdu;
1220+ struct mt7996_txp_ptr {
1221+ __le32 addr1;
1222+ __le32 addr_info;
1223+ __le32 addr2;
1224+ } *ptr;
1225+ int i = 0;
1226+
1227+ for (i = 0; i < 12; i = i+2 ) {
1228+ if (i == 0 || i == 4) {
1229+ msdu = (struct mt7996_txp_token *) txp;
1230+ info_or_seq_printf(s, "msdu token(%d-%d)=%ld %ld %ld %ld (0x%08x-0x%08x)\n", i, i+3,
1231+ (msdu->msdu[0] & GENMASK(14, 0)),
1232+ (msdu->msdu[1] & GENMASK(14, 0)),
1233+ (msdu->msdu[2] & GENMASK(14, 0)),
1234+ (msdu->msdu[3] & GENMASK(14, 0)), *txp, *(txp+1));
1235+ txp = txp + 2;
1236+ }
1237+ ptr = (struct mt7996_txp_ptr *) txp;
1238+ info_or_seq_printf(s, "ptr%02d : addr(0x%08x) len(%ld) addr_h(%02lx) SRC(%d) ML(%d) \n",
1239+ i, ptr->addr1,
1240+ FIELD_GET(GENMASK(11, 0), ptr->addr_info),
1241+ FIELD_GET(GENMASK(13, 12), ptr->addr_info),
1242+ !!(ptr->addr_info & BIT(14)),
1243+ !!(ptr->addr_info & BIT(15)));
1244+ info_or_seq_printf(s, "ptr%02d : addr(0x%08x) len(%ld) addr_h(%02lx) SRC(%d) ML(%d) \n",
1245+ i+1, ptr->addr2,
1246+ FIELD_GET(GENMASK(27, 16), ptr->addr_info),
1247+ FIELD_GET(GENMASK(29, 28), ptr->addr_info),
1248+ !!(ptr->addr_info & BIT(30)),
1249+ !!(ptr->addr_info & BIT(31)));
1250+ txp = txp + 3;
1251+ }
1252+}
1253+
1254+//bmac dump hif txp
1255+void mt7996_dump_bmac_hif_txp_info(struct seq_file *s, struct mt7996_dev *dev,
1256+ __le32 *txp, u32 hif_txp_ver)
1257+{
1258+ int i, j = 0;
1259+ u32 dw;
1260+
1261+ info_or_seq_printf(s, "txp raw data: size=%d\n", HIF_TXP_V2_SIZE);
1262+ info_or_seq_hex_dump(s, DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txp, HIF_TXP_V2_SIZE, false);
1263+
1264+ info_or_seq_printf(s, "BMAC_TXP Fields:\n");
1265+
1266+ /* dw0 */
1267+ if (hif_txp_ver == 2) {
1268+ dw = le32_to_cpu(txp[0]);
1269+ info_or_seq_printf(s, "HIF_TXP_PRIORITY = %d\n",
1270+ GET_FIELD(HIF_TXP_PRIORITY, dw));
1271+ info_or_seq_printf(s, "HIF_TXP_FIXED_RATE = %d\n",
1272+ GET_FIELD(HIF_TXP_FIXED_RATE, dw));
1273+ info_or_seq_printf(s, "HIF_TXP_TCP = %d\n",
1274+ GET_FIELD(HIF_TXP_TCP, dw));
1275+ info_or_seq_printf(s, "HIF_TXP_NON_CIPHER = %d\n",
1276+ GET_FIELD(HIF_TXP_NON_CIPHER, dw));
1277+ info_or_seq_printf(s, "HIF_TXP_VLAN = %d\n",
1278+ GET_FIELD(HIF_TXP_VLAN, dw));
1279+ info_or_seq_printf(s, "HIF_TXP_BC_MC_FLAG = %d\n",
1280+ GET_FIELD(HIF_TXP_BC_MC_FLAG, dw));
1281+ info_or_seq_printf(s, "HIF_TXP_FR_HOST = %d\n",
1282+ GET_FIELD(HIF_TXP_FR_HOST, dw));
1283+ info_or_seq_printf(s, "HIF_TXP_ETYPE = %d\n",
1284+ GET_FIELD(HIF_TXP_ETYPE, dw));
1285+ info_or_seq_printf(s, "HIF_TXP_TXP_AMSDU = %d\n",
1286+ GET_FIELD(HIF_TXP_TXP_AMSDU, dw));
1287+ info_or_seq_printf(s, "HIF_TXP_TXP_MC_CLONE = %d\n",
1288+ GET_FIELD(HIF_TXP_TXP_MC_CLONE, dw));
1289+ info_or_seq_printf(s, "HIF_TXP_TOKEN_ID = %d\n",
1290+ GET_FIELD(HIF_TXP_TOKEN_ID, dw));
1291+
1292+ /* dw1 */
1293+ dw = le32_to_cpu(txp[1]);
1294+ info_or_seq_printf(s, "HIF_TXP_BSS_IDX = %d\n",
1295+ GET_FIELD(HIF_TXP_BSS_IDX, dw));
1296+ info_or_seq_printf(s, "HIF_TXP_USER_PRIORITY = %d\n",
1297+ GET_FIELD(HIF_TXP_USER_PRIORITY, dw));
1298+ info_or_seq_printf(s, "HIF_TXP_BUF_NUM = %d\n",
1299+ GET_FIELD(HIF_TXP_BUF_NUM, dw));
1300+ info_or_seq_printf(s, "HIF_TXP_MSDU_CNT = %d\n",
1301+ GET_FIELD(HIF_TXP_MSDU_CNT, dw));
1302+ info_or_seq_printf(s, "HIF_TXP_SRC = %d\n",
1303+ GET_FIELD(HIF_TXP_SRC, dw));
1304+
1305+ /* dw2 */
1306+ dw = le32_to_cpu(txp[2]);
1307+ info_or_seq_printf(s, "HIF_TXP_ETH_TYPE(network-endian) = 0x%x\n",
1308+ GET_FIELD(HIF_TXP_ETH_TYPE, dw));
1309+ info_or_seq_printf(s, "HIF_TXP_WLAN_IDX = %d\n",
1310+ GET_FIELD(HIF_TXP_WLAN_IDX, dw));
1311+
1312+ /* dw3 */
1313+ dw = le32_to_cpu(txp[3]);
1314+ info_or_seq_printf(s, "HIF_TXP_PPE_INFO = 0x%x\n",
1315+ GET_FIELD(HIF_TXP_PPE_INFO, dw));
1316+
1317+ for (i = 0; i < 13; i++) {
1318+ if (i % 2 == 0) {
1319+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_L = 0x%x\n",
1320+ i, GET_FIELD(HIF_TXP_BUF_PTR0_L,
1321+ le32_to_cpu(txp[4 + j])));
1322+ j++;
1323+ info_or_seq_printf(s, "HIF_TXP_BUF_LEN%d = %d\n",
1324+ i, GET_FIELD(HIF_TXP_BUF_LEN0, le32_to_cpu(txp[4 + j])));
1325+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_H = 0x%x\n",
1326+ i, GET_FIELD(HIF_TXP_BUF_PTR0_H, le32_to_cpu(txp[4 + j])));
1327+ if (i <= 10) {
1328+ info_or_seq_printf(s, "HIF_TXP_BUF_LEN%d = %d\n",
1329+ i + 1, GET_FIELD(HIF_TXP_BUF_LEN1, le32_to_cpu(txp[4 + j])));
1330+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_H = 0x%x\n",
1331+ i + 1, GET_FIELD(HIF_TXP_BUF_PTR1_H, le32_to_cpu(txp[4 + j])));
1332+ }
1333+ j++;
1334+ } else {
1335+ info_or_seq_printf(s, "HIF_TXP_BUF_PTR%d_L = 0x%x\n",
1336+ i, GET_FIELD(HIF_TXP_BUF_PTR1_L,
1337+ le32_to_cpu(txp[4 + j])));
1338+ j++;
1339+ }
1340+ }
1341+
1342+ info_or_seq_printf(s, "ml = 0x%x\n",
1343+ GET_FIELD(HIF_TXP_ML, le32_to_cpu(txp[23])));
1344+ } else {
1345+ struct mt76_connac_txp_common *txp_v1 = (struct mt76_connac_txp_common *)txp;
1346+
1347+ info_or_seq_printf(s, "FLAGS = (%04x)\n", txp_v1->fw.flags);
1348+
1349+ info_or_seq_printf(s, "MSDU = %d\n", txp_v1->fw.token);
1350+
1351+ info_or_seq_printf(s, "BSS_IDX = %d\n", txp_v1->fw.bss_idx);
1352+
1353+ info_or_seq_printf(s, "WCID = %d\n",txp_v1->fw.rept_wds_wcid);
1354+
1355+ info_or_seq_printf(s, "MSDU_CNT = %d\n", txp_v1->fw.nbuf);
1356+
1357+ for (i = 0; i < MT_TXP_MAX_BUF_NUM; i++)
1358+ info_or_seq_printf(s, "ptr%02d : addr(0x%08x) len(%d)\n", i, le32_to_cpu(txp_v1->fw.buf[i]),
1359+ le16_to_cpu(txp_v1->fw.len[i]));
1360+ }
1361+}
1362+
1363+/* bmac txd dump */
1364+void mt7996_dump_bmac_txd_info(struct seq_file *s, struct mt7996_dev *dev,
1365+ __le32 *txd, bool is_hif_txd, bool dump_txp)
1366+{
1367+ u32 hif_txp_ver = 0;
1368+
1369+ /* dump stop */
1370+ if (!dev->dbg.txd_read_cnt)
1371+ return;
1372+
1373+ /* force dump */
1374+ if (dev->dbg.txd_read_cnt > 8)
1375+ dev->dbg.txd_read_cnt = 8;
1376+
1377+ /* dump txd_read_cnt times */
1378+ if (dev->dbg.txd_read_cnt != 8)
1379+ dev->dbg.txd_read_cnt--;
1380+
1381+ info_or_seq_printf(s, "txd raw data: size=%d\n", MT_TXD_SIZE);
1382+ info_or_seq_hex_dump(s, DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txd, MT_TXD_SIZE, false);
1383+
1384+ info_or_seq_printf(s, "BMAC_TXD Fields:\n");
1385+ /* dw0 */
1386+ if (is_hif_txd) {
1387+ hif_txp_ver = FIELD_GET(GENMASK(22, 19), txd[0]);
1388+ info_or_seq_printf(s, "HIF TXD VER = %d\n", hif_txp_ver);
1389+ }
1390+ info_or_seq_printf(s, "TX_BYTE_COUNT = %d\n",
1391+ GET_FIELD(WF_TX_DESCRIPTOR_TX_BYTE_COUNT, txd[0]));
1392+ info_or_seq_printf(s, "ETHER_TYPE_OFFSET(word) = %d\n",
1393+ GET_FIELD(WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET, txd[0]));
1394+ info_or_seq_printf(s, "PKT_FT = %d%s%s%s%s\n",
1395+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]),
1396+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 0 ? "(ct)" : "",
1397+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 1 ? "(s&f)" : "",
1398+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 2 ? "(cmd)" : "",
1399+ GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 3 ? "(redirect)" : "");
1400+ info_or_seq_printf(s, "Q_IDX = %d%s%s%s\n",
1401+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]),
1402+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x10 ? "(ALTX)" : "",
1403+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x11 ? "(BMC)" : "",
1404+ GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x12 ? "(BCN)" : "");
1405+
1406+ /* dw1 */
1407+ info_or_seq_printf(s, "MLD_ID = %d\n",
1408+ GET_FIELD(WF_TX_DESCRIPTOR_MLD_ID, txd[1]));
1409+ info_or_seq_printf(s, "TGID = %d\n",
1410+ GET_FIELD(WF_TX_DESCRIPTOR_TGID, txd[1]));
1411+ info_or_seq_printf(s, "HF = %d%s%s%s%s\n",
1412+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]),
1413+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? "(eth/802.3)" : "",
1414+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 1 ? "(cmd)" : "",
1415+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? "(802.11)" : "",
1416+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? "(802.11 enhanced" : "");
1417+ info_or_seq_printf(s, "802.11 HEADER_LENGTH = %d\n",
1418+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ?
1419+ GET_FIELD(WF_TX_DESCRIPTOR_HEADER_LENGTH, txd[1]) : 0);
1420+ info_or_seq_printf(s, "MRD = %d\n",
1421+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1422+ GET_FIELD(WF_TX_DESCRIPTOR_MRD, txd[1]) : 0);
1423+ info_or_seq_printf(s, "EOSP = %d\n",
1424+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1425+ GET_FIELD(WF_TX_DESCRIPTOR_EOSP, txd[1]) : 0);
1426+ info_or_seq_printf(s, "AMS = %d\n",
1427+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ?
1428+ GET_FIELD(WF_TX_DESCRIPTOR_AMS, txd[1]) : 0);
1429+ info_or_seq_printf(s, "RMVL = %d\n",
1430+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1431+ GET_FIELD(WF_TX_DESCRIPTOR_RMVL, txd[1]): 0);
1432+ info_or_seq_printf(s, "VLAN = %d\n",
1433+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1434+ GET_FIELD(WF_TX_DESCRIPTOR_VLAN, txd[1]) : 0);
1435+ info_or_seq_printf(s, "ETYP = %d\n",
1436+ GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ?
1437+ GET_FIELD(WF_TX_DESCRIPTOR_ETYP, txd[1]) : 0);
1438+ info_or_seq_printf(s, "TID_MGMT_TYPE = %d\n",
1439+ GET_FIELD(WF_TX_DESCRIPTOR_TID_MGMT_TYPE, txd[1]));
1440+ info_or_seq_printf(s, "OM = %d\n",
1441+ GET_FIELD(WF_TX_DESCRIPTOR_OM, txd[1]));
1442+ info_or_seq_printf(s, "FR = %d\n",
1443+ GET_FIELD(WF_TX_DESCRIPTOR_FR, txd[1]));
1444+
1445+ /* dw2 */
1446+ info_or_seq_printf(s, "SUBTYPE = %d%s%s%s%s\n",
1447+ GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]),
1448+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0) &&
1449+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 13) ?
1450+ "(action)" : "",
1451+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1) &&
1452+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 8) ?
1453+ "(bar)" : "",
1454+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) &&
1455+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 4) ?
1456+ "(null)" : "",
1457+ (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) &&
1458+ (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 12) ?
1459+ "(qos null)" : "");
1460+
1461+ info_or_seq_printf(s, "FTYPE = %d%s%s%s\n",
1462+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]),
1463+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0 ? "(mgmt)" : "",
1464+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1 ? "(ctl)" : "",
1465+ GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2 ? "(data)" : "");
1466+ info_or_seq_printf(s, "BF_TYPE = %d\n",
1467+ GET_FIELD(WF_TX_DESCRIPTOR_BF_TYPE, txd[2]));
1468+ info_or_seq_printf(s, "OM_MAP = %d\n",
1469+ GET_FIELD(WF_TX_DESCRIPTOR_OM_MAP, txd[2]));
1470+ info_or_seq_printf(s, "RTS = %d\n",
1471+ GET_FIELD(WF_TX_DESCRIPTOR_RTS, txd[2]));
1472+ info_or_seq_printf(s, "HEADER_PADDING = %d\n",
1473+ GET_FIELD(WF_TX_DESCRIPTOR_HEADER_PADDING, txd[2]));
1474+ info_or_seq_printf(s, "DU = %d\n",
1475+ GET_FIELD(WF_TX_DESCRIPTOR_DU, txd[2]));
1476+ info_or_seq_printf(s, "HE = %d\n",
1477+ GET_FIELD(WF_TX_DESCRIPTOR_HE, txd[2]));
1478+ info_or_seq_printf(s, "FRAG = %d\n",
1479+ GET_FIELD(WF_TX_DESCRIPTOR_FRAG, txd[2]));
1480+ info_or_seq_printf(s, "REMAINING_TX_TIME = %d\n",
1481+ GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_TIME, txd[2]));
1482+ info_or_seq_printf(s, "POWER_OFFSET = %d\n",
1483+ GET_FIELD(WF_TX_DESCRIPTOR_POWER_OFFSET, txd[2]));
1484+
1485+ /* dw3 */
1486+ info_or_seq_printf(s, "NA = %d\n",
1487+ GET_FIELD(WF_TX_DESCRIPTOR_NA, txd[3]));
1488+ info_or_seq_printf(s, "PF = %d\n",
1489+ GET_FIELD(WF_TX_DESCRIPTOR_PF, txd[3]));
1490+ info_or_seq_printf(s, "EMRD = %d\n",
1491+ GET_FIELD(WF_TX_DESCRIPTOR_EMRD, txd[3]));
1492+ info_or_seq_printf(s, "EEOSP = %d\n",
1493+ GET_FIELD(WF_TX_DESCRIPTOR_EEOSP, txd[3]));
1494+ info_or_seq_printf(s, "BM = %d\n",
1495+ GET_FIELD(WF_TX_DESCRIPTOR_BM, txd[3]));
1496+ info_or_seq_printf(s, "HW_AMSDU_CAP = %d\n",
1497+ GET_FIELD(WF_TX_DESCRIPTOR_HW_AMSDU_CAP, txd[3]));
1498+ info_or_seq_printf(s, "TX_COUNT = %d\n",
1499+ GET_FIELD(WF_TX_DESCRIPTOR_TX_COUNT, txd[3]));
1500+ info_or_seq_printf(s, "REMAINING_TX_COUNT = %d\n",
1501+ GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_COUNT, txd[3]));
1502+ info_or_seq_printf(s, "SN = %d\n",
1503+ GET_FIELD(WF_TX_DESCRIPTOR_SN, txd[3]));
1504+ info_or_seq_printf(s, "BA_DIS = %d\n",
1505+ GET_FIELD(WF_TX_DESCRIPTOR_BA_DIS, txd[3]));
1506+ info_or_seq_printf(s, "PM = %d\n",
1507+ GET_FIELD(WF_TX_DESCRIPTOR_PM, txd[3]));
1508+ info_or_seq_printf(s, "PN_VLD = %d\n",
1509+ GET_FIELD(WF_TX_DESCRIPTOR_PN_VLD, txd[3]));
1510+ info_or_seq_printf(s, "SN_VLD = %d\n",
1511+ GET_FIELD(WF_TX_DESCRIPTOR_SN_VLD, txd[3]));
1512+
1513+ /* dw4 */
1514+ info_or_seq_printf(s, "PN_31_0 = 0x%x\n",
1515+ GET_FIELD(WF_TX_DESCRIPTOR_PN_31_0_, txd[4]));
1516+
1517+ /* dw5 */
1518+ info_or_seq_printf(s, "PID = %d\n",
1519+ GET_FIELD(WF_TX_DESCRIPTOR_PID, txd[5]));
1520+ info_or_seq_printf(s, "TXSFM = %d\n",
1521+ GET_FIELD(WF_TX_DESCRIPTOR_TXSFM, txd[5]));
1522+ info_or_seq_printf(s, "TXS2M = %d\n",
1523+ GET_FIELD(WF_TX_DESCRIPTOR_TXS2M, txd[5]));
1524+ info_or_seq_printf(s, "TXS2H = %d\n",
1525+ GET_FIELD(WF_TX_DESCRIPTOR_TXS2H, txd[5]));
1526+ info_or_seq_printf(s, "FBCZ = %d\n",
1527+ GET_FIELD(WF_TX_DESCRIPTOR_FBCZ, txd[5]));
1528+ info_or_seq_printf(s, "BYPASS_RBB = %d\n",
1529+ GET_FIELD(WF_TX_DESCRIPTOR_BYPASS_RBB, txd[5]));
1530+
1531+ info_or_seq_printf(s, "FL = %d\n",
1532+ GET_FIELD(WF_TX_DESCRIPTOR_FL, txd[5]));
1533+ info_or_seq_printf(s, "PN_47_32 = 0x%x\n",
1534+ GET_FIELD(WF_TX_DESCRIPTOR_PN_47_32_, txd[5]));
1535+
1536+ /* dw6 */
1537+ info_or_seq_printf(s, "AMSDU_CAP_UTXB = %d\n",
1538+ GET_FIELD(WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB, txd[6]));
1539+ info_or_seq_printf(s, "DAS = %d\n",
1540+ GET_FIELD(WF_TX_DESCRIPTOR_DAS, txd[6]));
1541+ info_or_seq_printf(s, "DIS_MAT = %d\n",
1542+ GET_FIELD(WF_TX_DESCRIPTOR_DIS_MAT, txd[6]));
1543+ info_or_seq_printf(s, "MSDU_COUNT = %d\n",
1544+ GET_FIELD(WF_TX_DESCRIPTOR_MSDU_COUNT, txd[6]));
1545+ info_or_seq_printf(s, "TIMESTAMP_OFFSET = %d\n",
1546+ GET_FIELD(WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX, txd[6]));
1547+ info_or_seq_printf(s, "FIXED_RATE_IDX = %d\n",
1548+ GET_FIELD(WF_TX_DESCRIPTOR_FIXED_RATE_IDX, txd[6]));
1549+ info_or_seq_printf(s, "BW = %d\n",
1550+ GET_FIELD(WF_TX_DESCRIPTOR_BW, txd[6]));
1551+ info_or_seq_printf(s, "VTA = %d\n",
1552+ GET_FIELD(WF_TX_DESCRIPTOR_VTA, txd[6]));
1553+ info_or_seq_printf(s, "SRC = %d\n",
1554+ GET_FIELD(WF_TX_DESCRIPTOR_SRC, txd[6]));
1555+
1556+ /* dw7 */
1557+ info_or_seq_printf(s, "SW_TX_TIME(unit:65536ns) = %d\n",
1558+ GET_FIELD(WF_TX_DESCRIPTOR_SW_TX_TIME , txd[7]));
1559+ info_or_seq_printf(s, "UT = %d\n",
1560+ GET_FIELD(WF_TX_DESCRIPTOR_UT, txd[7]));
1561+ info_or_seq_printf(s, "CTXD_CNT = %d\n",
1562+ GET_FIELD(WF_TX_DESCRIPTOR_CTXD_CNT, txd[7]));
1563+ info_or_seq_printf(s, "HM = %d\n",
1564+ GET_FIELD(WF_TX_DESCRIPTOR_HM, txd[7]));
1565+ info_or_seq_printf(s, "DP = %d\n",
1566+ GET_FIELD(WF_TX_DESCRIPTOR_DP, txd[7]));
1567+ info_or_seq_printf(s, "IP = %d\n",
1568+ GET_FIELD(WF_TX_DESCRIPTOR_IP, txd[7]));
1569+ info_or_seq_printf(s, "TXD_LEN = %d\n",
1570+ GET_FIELD(WF_TX_DESCRIPTOR_TXD_LEN, txd[7]));
1571+
1572+ if (dump_txp) {
1573+ __le32 *txp = txd + 8;
1574+
1575+ if (is_hif_txd)
1576+ mt7996_dump_bmac_hif_txp_info(s, dev, txp, hif_txp_ver);
1577+ else
1578+ mt7996_dump_bmac_mac_txp_info(s, dev, txp);
1579+ }
1580+}
1581+
1582+static void
1583+mt7996_dump_mac_fid(struct seq_file *s, struct mt7996_dev *dev, u32 fid, bool is_ple)
1584+{
1585+#define PLE_MEM_SIZE 128
1586+#define PSE_MEM_SIZE 256
1587+ u8 data[PSE_MEM_SIZE] = {0};
1588+ u32 addr = 0;
1589+ int i = 0, cr_cnt = PSE_MEM_SIZE;
1590+ u32 *ptr = (u32 *) data;
1591+
1592+ if (is_ple) {
1593+ cr_cnt = PLE_MEM_SIZE;
1594+ seq_printf(s, "dump ple: fid = 0x%08x\n", fid);
1595+ } else {
1596+ seq_printf(s, "dump pse: fid = 0x%08x\n", fid);
1597+ }
1598+
1599+ for (i = 0; i < cr_cnt; i = i + 4) {
1600+ if (is_ple)
1601+ addr = (0xa << 28 | fid << 15) + i;
1602+ else
1603+ addr = (0xb << 28 | fid << 15) + i;
1604+ *ptr = mt76_rr(dev, addr);
1605+ ptr++;
1606+ }
1607+
1608+ seq_printf(s, "raw data: size=%d\n", cr_cnt);
1609+
1610+ seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)data, cr_cnt, false);
1611+ /* dump one txd info */
1612+ if (is_ple) {
1613+ dev->dbg.txd_read_cnt = 1;
1614+ mt7996_dump_bmac_txd_info(s, dev, (__le32 *)&data[0], false, true);
1615+ }
1616+}
1617+
1618+static int
1619+mt7996_ple_fid_read(struct seq_file *s, void *data) {
1620+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1621+
1622+ mt7996_dump_mac_fid(s, dev, dev->dbg.fid_idx, true);
1623+ return 0;
1624+}
1625+
1626+static int
1627+mt7996_pse_fid_read(struct seq_file *s, void *data) {
1628+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1629+
1630+ mt7996_dump_mac_fid(s, dev, dev->dbg.fid_idx, false);
1631+ return 0;
1632+}
1633+
1634+void mt7996_dump_bmac_rxd_info(struct mt7996_dev *dev, __le32 *rxd)
1635+{
1636+ /* dump stop */
1637+ if (!dev->dbg.rxd_read_cnt)
1638+ return;
1639+
1640+ /* force dump */
1641+ if (dev->dbg.rxd_read_cnt > 8)
1642+ dev->dbg.rxd_read_cnt = 8;
1643+
1644+ /* dump txd_read_cnt times */
1645+ if (dev->dbg.rxd_read_cnt != 8)
1646+ dev->dbg.rxd_read_cnt--;
1647+
1648+ printk("rxd raw data: size=%d\n", MT_TXD_SIZE);
1649+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)rxd, 96, false);
1650+
1651+ printk("BMAC_RXD Fields:\n");
1652+
1653+ /* group0 */
1654+ /* dw0 */
1655+ printk("RX_BYTE_COUNT = %d\n",
1656+ GET_FIELD(WF_RX_DESCRIPTOR_RX_BYTE_COUNT, le32_to_cpu(rxd[0])));
1657+ printk("PACKET_TYPE = %d\n",
1658+ GET_FIELD(WF_RX_DESCRIPTOR_PACKET_TYPE, le32_to_cpu(rxd[0])));
1659+
1660+ /* dw1 */
1661+ printk("MLD_ID = %d\n",
1662+ GET_FIELD(WF_RX_DESCRIPTOR_MLD_ID, le32_to_cpu(rxd[1])));
1663+ printk("GROUP_VLD = 0x%x%s%s%s%s%s\n",
1664+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])),
1665+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1666+ & BMAC_GROUP_VLD_1 ? "[group1]" : "",
1667+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1668+ & BMAC_GROUP_VLD_2 ? "[group2]" : "",
1669+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1670+ & BMAC_GROUP_VLD_3 ? "[group3]" : "",
1671+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1672+ & BMAC_GROUP_VLD_4 ? "[group4]" : "",
1673+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1674+ & BMAC_GROUP_VLD_5 ? "[group5]" : "");
1675+ printk("KID = %d\n",
1676+ GET_FIELD(WF_RX_DESCRIPTOR_KID, le32_to_cpu(rxd[1])));
1677+ printk("CM = %d\n",
1678+ GET_FIELD(WF_RX_DESCRIPTOR_CM, le32_to_cpu(rxd[1])));
1679+ printk("CLM = %d\n",
1680+ GET_FIELD(WF_RX_DESCRIPTOR_CLM, le32_to_cpu(rxd[1])));
1681+ printk("I = %d\n",
1682+ GET_FIELD(WF_RX_DESCRIPTOR_I, le32_to_cpu(rxd[1])));
1683+ printk("T = %d\n",
1684+ GET_FIELD(WF_RX_DESCRIPTOR_T, le32_to_cpu(rxd[1])));
1685+ printk("BN = %d\n",
1686+ GET_FIELD(WF_RX_DESCRIPTOR_BN, le32_to_cpu(rxd[1])));
1687+ printk("BIPN_FAIL = %d\n",
1688+ GET_FIELD(WF_RX_DESCRIPTOR_BIPN_FAIL, le32_to_cpu(rxd[1])));
1689+
1690+ /* dw2 */
1691+ printk("BSSID = %d\n",
1692+ GET_FIELD(WF_RX_DESCRIPTOR_BSSID, le32_to_cpu(rxd[2])));
1693+ printk("H = %d%s\n",
1694+ GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])),
1695+ GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])) == 0 ?
1696+ "802.11 frame" : "eth/802.3 frame");
1697+ printk("HEADER_LENGTH(word) = %d\n",
1698+ GET_FIELD(WF_RX_DESCRIPTOR_HEADER_LENGTH, le32_to_cpu(rxd[2])));
1699+ printk("HO(word) = %d\n",
1700+ GET_FIELD(WF_RX_DESCRIPTOR_HO, le32_to_cpu(rxd[2])));
1701+ printk("SEC_MODE = %d\n",
1702+ GET_FIELD(WF_RX_DESCRIPTOR_SEC_MODE, le32_to_cpu(rxd[2])));
1703+ printk("MUBAR = %d\n",
1704+ GET_FIELD(WF_RX_DESCRIPTOR_MUBAR, le32_to_cpu(rxd[2])));
1705+ printk("SWBIT = %d\n",
1706+ GET_FIELD(WF_RX_DESCRIPTOR_SWBIT, le32_to_cpu(rxd[2])));
1707+ printk("DAF = %d\n",
1708+ GET_FIELD(WF_RX_DESCRIPTOR_DAF, le32_to_cpu(rxd[2])));
1709+ printk("EL = %d\n",
1710+ GET_FIELD(WF_RX_DESCRIPTOR_EL, le32_to_cpu(rxd[2])));
1711+ printk("HTF = %d\n",
1712+ GET_FIELD(WF_RX_DESCRIPTOR_HTF, le32_to_cpu(rxd[2])));
1713+ printk("INTF = %d\n",
1714+ GET_FIELD(WF_RX_DESCRIPTOR_INTF, le32_to_cpu(rxd[2])));
1715+ printk("FRAG = %d\n",
1716+ GET_FIELD(WF_RX_DESCRIPTOR_FRAG, le32_to_cpu(rxd[2])));
1717+ printk("NUL = %d\n",
1718+ GET_FIELD(WF_RX_DESCRIPTOR_NUL, le32_to_cpu(rxd[2])));
1719+ printk("NDATA = %d%s\n",
1720+ GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])),
1721+ GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])) == 0 ?
1722+ "[data frame]" : "[mgmt/ctl frame]");
1723+ printk("NAMP = %d%s\n",
1724+ GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])),
1725+ GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])) == 0 ?
1726+ "[ampdu frame]" : "[mpdu frame]");
1727+ printk("BF_RPT = %d\n",
1728+ GET_FIELD(WF_RX_DESCRIPTOR_BF_RPT, le32_to_cpu(rxd[2])));
1729+
1730+ /* dw3 */
1731+ printk("RXV_SN = %d\n",
1732+ GET_FIELD(WF_RX_DESCRIPTOR_RXV_SN, le32_to_cpu(rxd[3])));
1733+ printk("CH_FREQUENCY = %d\n",
1734+ GET_FIELD(WF_RX_DESCRIPTOR_CH_FREQUENCY, le32_to_cpu(rxd[3])));
1735+ printk("A1_TYPE = %d%s%s%s%s\n",
1736+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])),
1737+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 0 ?
1738+ "[reserved]" : "",
1739+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 1 ?
1740+ "[uc2me]" : "",
1741+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 2 ?
1742+ "[mc]" : "",
1743+ GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 3 ?
1744+ "[bc]" : "");
1745+ printk("HTC = %d\n",
1746+ GET_FIELD(WF_RX_DESCRIPTOR_HTC, le32_to_cpu(rxd[3])));
1747+ printk("TCL = %d\n",
1748+ GET_FIELD(WF_RX_DESCRIPTOR_TCL, le32_to_cpu(rxd[3])));
1749+ printk("BBM = %d\n",
1750+ GET_FIELD(WF_RX_DESCRIPTOR_BBM, le32_to_cpu(rxd[3])));
1751+ printk("BU = %d\n",
1752+ GET_FIELD(WF_RX_DESCRIPTOR_BU, le32_to_cpu(rxd[3])));
1753+ printk("CO_ANT = %d\n",
1754+ GET_FIELD(WF_RX_DESCRIPTOR_CO_ANT, le32_to_cpu(rxd[3])));
1755+ printk("BF_CQI = %d\n",
1756+ GET_FIELD(WF_RX_DESCRIPTOR_BF_CQI, le32_to_cpu(rxd[3])));
1757+ printk("FC = %d\n",
1758+ GET_FIELD(WF_RX_DESCRIPTOR_FC, le32_to_cpu(rxd[3])));
1759+ printk("VLAN = %d\n",
1760+ GET_FIELD(WF_RX_DESCRIPTOR_VLAN, le32_to_cpu(rxd[3])));
1761+
1762+ /* dw4 */
1763+ printk("PF = %d%s%s%s%s\n",
1764+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])),
1765+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 0 ?
1766+ "[msdu]" : "",
1767+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 1 ?
1768+ "[final amsdu]" : "",
1769+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 2 ?
1770+ "[middle amsdu]" : "",
1771+ GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 3 ?
1772+ "[first amsdu]" : "");
1773+ printk("MAC = %d\n",
1774+ GET_FIELD(WF_RX_DESCRIPTOR_MAC, le32_to_cpu(rxd[4])));
1775+ printk("TID = %d\n",
1776+ GET_FIELD(WF_RX_DESCRIPTOR_TID, le32_to_cpu(rxd[4])));
1777+ printk("ETHER_TYPE_OFFSET = %d\n",
1778+ GET_FIELD(WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET, le32_to_cpu(rxd[4])));
1779+ printk("IP = %d\n",
1780+ GET_FIELD(WF_RX_DESCRIPTOR_IP, le32_to_cpu(rxd[4])));
1781+ printk("UT = %d\n",
1782+ GET_FIELD(WF_RX_DESCRIPTOR_UT, le32_to_cpu(rxd[4])));
1783+ printk("PSE_FID = %d\n",
1784+ GET_FIELD(WF_RX_DESCRIPTOR_PSE_FID, le32_to_cpu(rxd[4])));
1785+
1786+ /* group4 */
1787+ /* dw0 */
1788+ printk("FRAME_CONTROL_FIELD = 0x%x\n",
1789+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1790+ & BMAC_GROUP_VLD_4 ?
1791+ GET_FIELD(WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD, le32_to_cpu(rxd[8])) : 0);
1792+ printk("PEER_MLD_ADDRESS_15_0 = 0x%x\n",
1793+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1794+ & BMAC_GROUP_VLD_4 ?
1795+ GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0_,
1796+ le32_to_cpu(rxd[8])) : 0);
1797+
1798+ /* dw1 */
1799+ printk("PEER_MLD_ADDRESS_47_16 = 0x%x\n",
1800+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1801+ & BMAC_GROUP_VLD_4 ?
1802+ GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16_,
1803+ le32_to_cpu(rxd[9])) : 0);
1804+
1805+ /* dw2 */
1806+ printk("FRAGMENT_NUMBER = %d\n",
1807+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1808+ & BMAC_GROUP_VLD_4 ?
1809+ GET_FIELD(WF_RX_DESCRIPTOR_FRAGMENT_NUMBER,
1810+ le32_to_cpu(rxd[10])) : 0);
1811+ printk("SEQUENCE_NUMBER = %d\n",
1812+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1813+ & BMAC_GROUP_VLD_4 ?
1814+ GET_FIELD(WF_RX_DESCRIPTOR_SEQUENCE_NUMBER,
1815+ le32_to_cpu(rxd[10])) : 0);
1816+ printk("QOS_CONTROL_FIELD = 0x%x\n",
1817+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1818+ & BMAC_GROUP_VLD_4 ?
1819+ GET_FIELD(WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD,
1820+ le32_to_cpu(rxd[10])) : 0);
1821+
1822+ /* dw3 */
1823+ printk("HT_CONTROL_FIELD = 0x%x\n",
1824+ GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1]))
1825+ & BMAC_GROUP_VLD_4 ?
1826+ GET_FIELD(WF_RX_DESCRIPTOR_HT_CONTROL_FIELD,
1827+ le32_to_cpu(rxd[11])) : 0);
1828+}
1829+
1830+static int mt7996_token_txd_read(struct seq_file *s, void *data)
1831+{
1832+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1833+ struct mt76_txwi_cache *t;
1834+ u8* txwi;
1835+
1836+ seq_printf(s, "\n");
1837+ spin_lock_bh(&dev->mt76.token_lock);
1838+
1839+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
1840+ if (t != NULL) {
1841+ struct mt76_dev *mdev = &dev->mt76;
1842+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
1843+ /* dump one txd info */
1844+ dev->dbg.txd_read_cnt = 1;
1845+ mt7996_dump_bmac_txd_info(s, dev, (__le32 *)txwi, true, true);
1846+ seq_printf(s, "\n");
1847+ seq_printf(s, "[SKB]\n");
1848+ seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
1849+ seq_printf(s, "\n");
1850+ }
1851+ spin_unlock_bh(&dev->mt76.token_lock);
1852+ return 0;
1853+}
1854+
1855+static int mt7996_rx_msdu_pg_read(struct seq_file *s, void *data)
1856+{
1857+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
1858+ struct list_head *p;
1859+ int i, count = 0, total = 0;
1860+
1861+ seq_printf(s, "Rx Msdu page:\n");
1862+ spin_lock(&dev->wed_rro.lock);
1863+ for (i = 0; i < MT7996_RRO_MSDU_PG_HASH_SIZE; i++) {
1864+ list_for_each(p, &dev->wed_rro.pg_hash_head[i]) {
1865+ count++;
1866+ }
1867+ }
1868+
1869+ total = count;
1870+ list_for_each(p, &dev->wed_rro.pg_addr_cache) {
1871+ total++;
1872+ }
1873+ seq_printf(s, "\ttotal:%8d used:%8d\n", total, count);
1874+ spin_unlock(&dev->wed_rro.lock);
1875+
1876+ return 0;
1877+}
1878+
1879+int mt7996_mtk_init_debugfs_internal(struct mt7996_phy *phy, struct dentry *dir)
1880+{
1881+ struct mt7996_dev *dev = phy->dev;
1882+
1883+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
1884+ mt7996_token_txd_read);
1885+ debugfs_create_u32("txd_dump", 0600, dir, &dev->dbg.txd_read_cnt);
1886+ debugfs_create_u32("rxd_dump", 0600, dir, &dev->dbg.rxd_read_cnt);
1887+ debugfs_create_devm_seqfile(dev->mt76.dev, "rx_msdu_pg", dir,
1888+ mt7996_rx_msdu_pg_read);
1889+
1890+ /* ple/pse fid raw data dump */
1891+ debugfs_create_u32("fid_idx", 0600, dir, &dev->dbg.fid_idx);
1892+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_fid", dir,
1893+ mt7996_ple_fid_read);
1894+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_fid", dir,
1895+ mt7996_pse_fid_read);
1896+
1897+ debugfs_create_u8("dump_ple_txd", 0600, dir, &dev->dbg.dump_ple_txd);
1898+ return 0;
1899+}
1900+
1901+#endif
1902--
19032.18.0
1904