developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 8 | #include <dt-bindings/gpio/gpio.h> |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 9 | #include "mt7988.dtsi" |
| 10 | |
| 11 | / { |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 12 | model = "MediaTek MT7988D DSA 10G SPIM-NOR RFB"; |
| 13 | compatible = "mediatek,mt7988d-dsa-10g-spim-nor", |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 14 | /* Reserve this for DVFS if creating new dts */ |
| 15 | "mediatek,mt7988"; |
| 16 | |
| 17 | chosen { |
| 18 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 19 | earlycon=uart8250,mmio32,0x11000000 \ |
| 20 | pci=pcie_bus_perf"; |
| 21 | }; |
| 22 | |
developer | 8c0bd0c | 2023-07-17 10:45:20 +0800 | [diff] [blame] | 23 | cpus { |
| 24 | /delete-node/ cpu@3; |
| 25 | }; |
| 26 | |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 27 | memory { |
| 28 | reg = <0 0x40000000 0 0x10000000>; |
| 29 | }; |
| 30 | |
| 31 | wsys_adie: wsys_adie@0 { |
| 32 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 33 | compatible = "mediatek,rebb-mt7988-adie"; |
| 34 | adie_id = <7976>; |
| 35 | sku_type = <3000>; |
| 36 | }; |
| 37 | }; |
| 38 | |
| 39 | &fan { |
developer | fce0d15 | 2024-01-11 13:37:13 +0800 | [diff] [blame] | 40 | pwms = <&pwm 0 50000>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 41 | status = "okay"; |
| 42 | }; |
| 43 | |
| 44 | &pwm { |
| 45 | status = "okay"; |
| 46 | }; |
| 47 | |
| 48 | &uart0 { |
| 49 | status = "okay"; |
| 50 | }; |
| 51 | |
| 52 | &spi1 { |
| 53 | pinctrl-names = "default"; |
| 54 | /* pin shared with snfi */ |
| 55 | pinctrl-0 = <&spic_pins>; |
| 56 | status = "disabled"; |
| 57 | }; |
| 58 | |
| 59 | &spi2 { |
| 60 | pinctrl-names = "default"; |
| 61 | pinctrl-0 = <&spi2_flash_pins>; |
| 62 | status = "okay"; |
| 63 | spi_nor@0 { |
| 64 | #address-cells = <1>; |
| 65 | #size-cells = <1>; |
| 66 | compatible = "jedec,spi-nor"; |
| 67 | spi-cal-enable; |
| 68 | spi-cal-mode = "read-data"; |
| 69 | spi-cal-datalen = <7>; |
| 70 | spi-cal-data = /bits/ 8 < |
| 71 | 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ |
| 72 | spi-cal-addrlen = <1>; |
| 73 | spi-cal-addr = /bits/ 32 <0x0>; |
| 74 | reg = <0>; |
| 75 | spi-max-frequency = <52000000>; |
developer | 0508550 | 2023-04-06 13:04:13 +0800 | [diff] [blame] | 76 | spi-tx-bus-width = <4>; |
| 77 | spi-rx-bus-width = <4>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 78 | |
| 79 | partition@00000 { |
| 80 | label = "BL2"; |
| 81 | reg = <0x00000 0x0040000>; |
| 82 | }; |
| 83 | partition@40000 { |
| 84 | label = "u-boot-env"; |
| 85 | reg = <0x40000 0x0010000>; |
| 86 | }; |
| 87 | factory: partition@50000 { |
| 88 | label = "Factory"; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 89 | reg = <0x50000 0x0200000>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 90 | }; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 91 | partition@250000 { |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 92 | label = "FIP"; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 93 | reg = <0x250000 0x0080000>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 94 | }; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 95 | partition@2D0000 { |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 96 | label = "firmware"; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 97 | reg = <0x2D0000 0x1D30000>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 98 | }; |
| 99 | }; |
| 100 | }; |
| 101 | |
| 102 | &pcie0 { |
| 103 | pinctrl-names = "default"; |
| 104 | pinctrl-0 = <&pcie0_pins>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 105 | wifi-reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; |
| 106 | wifi-reset-msleep = <100>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 107 | status = "okay"; |
| 108 | }; |
| 109 | |
| 110 | &pcie1 { |
| 111 | pinctrl-names = "default"; |
| 112 | pinctrl-0 = <&pcie1_pins>; |
| 113 | status = "disabled"; |
| 114 | }; |
| 115 | |
| 116 | &pcie2 { |
| 117 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&pcie2_pins>; |
| 119 | status = "disabled"; |
| 120 | }; |
| 121 | |
| 122 | &pcie3 { |
| 123 | pinctrl-names = "default"; |
| 124 | pinctrl-0 = <&pcie3_pins>; |
| 125 | status = "okay"; |
| 126 | }; |
| 127 | |
| 128 | &pio { |
| 129 | mdio0_pins: mdio0-pins { |
| 130 | mux { |
| 131 | function = "mdio"; |
| 132 | groups = "mdc_mdio0"; |
| 133 | }; |
| 134 | |
| 135 | conf { |
| 136 | groups = "mdc_mdio0"; |
developer | edbe69e | 2023-06-08 11:08:46 +0800 | [diff] [blame] | 137 | drive-strength = <MTK_DRIVE_10mA>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 138 | }; |
| 139 | }; |
| 140 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 141 | gbe0_led0_pins: gbe0-pins { |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 142 | mux { |
| 143 | function = "led"; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 144 | groups = "gbe0_led0"; |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 145 | }; |
| 146 | }; |
| 147 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 148 | gbe1_led0_pins: gbe1-pins { |
| 149 | mux { |
| 150 | function = "led"; |
| 151 | groups = "gbe1_led0"; |
| 152 | }; |
| 153 | }; |
| 154 | |
| 155 | gbe2_led0_pins: gbe2-pins { |
| 156 | mux { |
| 157 | function = "led"; |
| 158 | groups = "gbe2_led0"; |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | gbe3_led0_pins: gbe3-pins { |
| 163 | mux { |
| 164 | function = "led"; |
| 165 | groups = "gbe3_led0"; |
| 166 | }; |
| 167 | }; |
| 168 | |
developer | 1643130 | 2023-05-05 13:02:37 +0800 | [diff] [blame] | 169 | i2p5gbe_led0_pins: 2p5gbe-pins { |
| 170 | mux { |
| 171 | function = "led"; |
| 172 | groups = "2p5gbe_led0"; |
| 173 | }; |
| 174 | }; |
| 175 | |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 176 | pcie0_pins: pcie0-pins { |
| 177 | mux { |
| 178 | function = "pcie"; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 179 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0"; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 180 | }; |
| 181 | }; |
| 182 | |
| 183 | pcie1_pins: pcie1-pins { |
| 184 | mux { |
| 185 | function = "pcie"; |
| 186 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 187 | "pcie_wake_n1_0"; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | pcie2_pins: pcie2-pins { |
| 192 | mux { |
| 193 | function = "pcie"; |
| 194 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 195 | "pcie_wake_n2_0"; |
| 196 | }; |
| 197 | }; |
| 198 | |
| 199 | pcie3_pins: pcie3-pins { |
| 200 | mux { |
| 201 | function = "pcie"; |
| 202 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 203 | "pcie_wake_n3_0"; |
| 204 | }; |
| 205 | }; |
| 206 | |
| 207 | spic_pins: spi1-pins { |
| 208 | mux { |
| 209 | function = "spi"; |
developer | d516958 | 2023-02-17 10:32:38 +0800 | [diff] [blame] | 210 | groups = "spi1"; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 211 | }; |
| 212 | }; |
| 213 | |
| 214 | spi2_flash_pins: spi2-pins { |
| 215 | mux { |
| 216 | function = "spi"; |
| 217 | groups = "spi2", "spi2_wp_hold"; |
| 218 | }; |
| 219 | }; |
| 220 | }; |
| 221 | |
| 222 | &watchdog { |
| 223 | status = "disabled"; |
| 224 | }; |
| 225 | |
| 226 | ð { |
| 227 | pinctrl-names = "default"; |
| 228 | pinctrl-0 = <&mdio0_pins>; |
| 229 | status = "okay"; |
| 230 | |
| 231 | gmac0: mac@0 { |
| 232 | compatible = "mediatek,eth-mac"; |
| 233 | reg = <0>; |
| 234 | mac-type = "xgdm"; |
| 235 | phy-mode = "10gbase-kr"; |
| 236 | |
| 237 | fixed-link { |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 238 | speed = <10000>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 239 | full-duplex; |
| 240 | pause; |
| 241 | }; |
| 242 | }; |
| 243 | |
| 244 | gmac1: mac@1 { |
| 245 | compatible = "mediatek,eth-mac"; |
| 246 | reg = <1>; |
| 247 | mac-type = "xgdm"; |
developer | 1643130 | 2023-05-05 13:02:37 +0800 | [diff] [blame] | 248 | phy-mode = "xgmii"; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 249 | phy-handle = <&phy0>; |
| 250 | }; |
| 251 | |
developer | 1643130 | 2023-05-05 13:02:37 +0800 | [diff] [blame] | 252 | gmac2: mac@2 { |
| 253 | compatible = "mediatek,eth-mac"; |
| 254 | reg = <2>; |
| 255 | mac-type = "xgdm"; |
| 256 | phy-mode = "usxgmii"; |
| 257 | phy-handle = <&phy1>; |
| 258 | }; |
| 259 | |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 260 | mdio: mdio-bus { |
| 261 | #address-cells = <1>; |
| 262 | #size-cells = <0>; |
developer | 9faf1ef | 2023-03-21 16:49:51 +0800 | [diff] [blame] | 263 | clock-frequency = <10500000>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 264 | |
| 265 | phy0: ethernet-phy@0 { |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 266 | pinctrl-names = "i2p5gbe-led"; |
developer | 1643130 | 2023-05-05 13:02:37 +0800 | [diff] [blame] | 267 | pinctrl-0 = <&i2p5gbe_led0_pins>; |
| 268 | reg = <15>; |
| 269 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 270 | phy-mode = "xgmii"; |
| 271 | }; |
| 272 | |
| 273 | phy1: ethernet-phy@8 { |
| 274 | reg = <8>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 275 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1643130 | 2023-05-05 13:02:37 +0800 | [diff] [blame] | 276 | reset-gpios = <&pio 3 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 277 | reset-assert-us = <100000>; |
| 278 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 279 | mdi-reversal = /bits/ 16 <1>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | switch@0 { |
| 283 | compatible = "mediatek,mt7988"; |
| 284 | reg = <31>; |
| 285 | ports { |
| 286 | #address-cells = <1>; |
| 287 | #size-cells = <0>; |
| 288 | |
| 289 | port@0 { |
| 290 | reg = <0>; |
| 291 | label = "lan0"; |
| 292 | phy-mode = "gmii"; |
| 293 | phy-handle = <&sphy0>; |
| 294 | }; |
| 295 | |
| 296 | port@1 { |
| 297 | reg = <1>; |
| 298 | label = "lan1"; |
| 299 | phy-mode = "gmii"; |
| 300 | phy-handle = <&sphy1>; |
| 301 | }; |
| 302 | |
| 303 | port@2 { |
| 304 | reg = <2>; |
| 305 | label = "lan2"; |
| 306 | phy-mode = "gmii"; |
| 307 | phy-handle = <&sphy2>; |
| 308 | }; |
| 309 | |
| 310 | port@3 { |
| 311 | reg = <3>; |
| 312 | label = "lan3"; |
| 313 | phy-mode = "gmii"; |
| 314 | phy-handle = <&sphy3>; |
| 315 | }; |
| 316 | |
| 317 | port@6 { |
| 318 | reg = <6>; |
| 319 | label = "cpu"; |
| 320 | ethernet = <&gmac0>; |
| 321 | phy-mode = "10gbase-kr"; |
| 322 | |
| 323 | fixed-link { |
| 324 | speed = <10000>; |
| 325 | full-duplex; |
| 326 | pause; |
| 327 | }; |
| 328 | }; |
| 329 | }; |
| 330 | |
| 331 | mdio { |
| 332 | compatible = "mediatek,dsa-slave-mdio"; |
| 333 | #address-cells = <1>; |
| 334 | #size-cells = <0>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 335 | |
| 336 | sphy0: switch_phy0@0 { |
| 337 | compatible = "ethernet-phy-id03a2.9481"; |
| 338 | reg = <0>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 339 | pinctrl-names = "gbe-led"; |
| 340 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 341 | nvmem-cells = <&phy_calibration_p0>; |
| 342 | nvmem-cell-names = "phy-cal-data"; |
| 343 | }; |
| 344 | |
| 345 | sphy1: switch_phy1@1 { |
| 346 | compatible = "ethernet-phy-id03a2.9481"; |
| 347 | reg = <1>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 348 | pinctrl-names = "gbe-led"; |
| 349 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 350 | nvmem-cells = <&phy_calibration_p1>; |
| 351 | nvmem-cell-names = "phy-cal-data"; |
| 352 | }; |
| 353 | |
| 354 | sphy2: switch_phy2@2 { |
| 355 | compatible = "ethernet-phy-id03a2.9481"; |
| 356 | reg = <2>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 357 | pinctrl-names = "gbe-led"; |
| 358 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 359 | nvmem-cells = <&phy_calibration_p2>; |
| 360 | nvmem-cell-names = "phy-cal-data"; |
| 361 | }; |
| 362 | |
| 363 | sphy3: switch_phy3@3 { |
| 364 | compatible = "ethernet-phy-id03a2.9481"; |
| 365 | reg = <3>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 366 | pinctrl-names = "gbe-led"; |
| 367 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 368 | nvmem-cells = <&phy_calibration_p3>; |
| 369 | nvmem-cell-names = "phy-cal-data"; |
| 370 | }; |
| 371 | }; |
| 372 | }; |
| 373 | }; |
| 374 | }; |
| 375 | |
| 376 | &hnat { |
| 377 | mtketh-wan = "eth1"; |
| 378 | mtketh-lan = "lan"; |
| 379 | mtketh-lan2 = "eth2"; |
| 380 | mtketh-max-gmac = <3>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 381 | mtketh-ppe-num = <3>; |
developer | 79a21a2 | 2023-01-09 13:57:39 +0800 | [diff] [blame] | 382 | status = "okay"; |
| 383 | }; |
| 384 | |
| 385 | &wed { |
| 386 | dy_txbm_enable = "true"; |
| 387 | dy_txbm_budge = <8>; |
| 388 | txbm_init_sz = <10>; |
| 389 | status = "okay"; |
| 390 | }; |