commit c98d48d7c16eebe416ea2f0e1e7edc3ee4a20d81
author developer <developer@mediatek.com> Thu Mar 02 19:44:01 2023 +0800
committer developer <developer@mediatek.com> Thu Mar 02 19:44:01 2023 +0800
tree 7f5dfd602c5f762cff698143632826738da9a64a
parent 79918552c955dbc3ffe1bc2fc56f89d93732dc73

[rdkb][common][bsp][Refactor and sync kernel from openwrt]

[Description]
d0d3e95 [kernel][mt7988][bsp][Enlarge reserved memory size for ATF BL31]
2ea52cf [kernel][mt7988][Change config-5.4 and dtsi files to support pstore]
1400d38 [Kernel][mt7988][eth][Adjust 10G PHY reset assert time]
b5eb811 [kernel][common][eth][Fix Aquantia link speed mismatch issue for downshift evnent]
bff3dc9 [mac80211][app][Change mt76 wifi interfaces rps to 3]
200898b [kernel][common][clk][set rtc clock enable default]

[Release-log]

Change-Id: Ia0d522d9bd17249ccb278675ec11892f08cd63c7