developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 8 | #include <dt-bindings/gpio/gpio.h> |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 9 | #include "mt7988.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; |
| 13 | compatible = "mediatek,mt7988a-dsa-10g-spim-snand", |
| 14 | /* Reserve this for DVFS if creating new dts */ |
| 15 | "mediatek,mt7988"; |
| 16 | |
| 17 | chosen { |
| 18 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 19 | earlycon=uart8250,mmio32,0x11000000 \ |
| 20 | pci=pcie_bus_perf"; |
| 21 | }; |
| 22 | |
| 23 | memory { |
| 24 | reg = <0 0x40000000 0 0x10000000>; |
| 25 | }; |
| 26 | |
| 27 | nmbm_spim_nand { |
| 28 | compatible = "generic,nmbm"; |
| 29 | |
| 30 | #address-cells = <1>; |
| 31 | #size-cells = <1>; |
| 32 | |
| 33 | lower-mtd-device = <&spi_nand>; |
| 34 | forced-create; |
| 35 | |
| 36 | partitions { |
| 37 | compatible = "fixed-partitions"; |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <1>; |
| 40 | |
| 41 | partition@0 { |
| 42 | label = "BL2"; |
| 43 | reg = <0x00000 0x0100000>; |
| 44 | read-only; |
| 45 | }; |
| 46 | |
| 47 | partition@100000 { |
| 48 | label = "u-boot-env"; |
| 49 | reg = <0x0100000 0x0080000>; |
| 50 | }; |
| 51 | |
| 52 | factory: partition@180000 { |
| 53 | label = "Factory"; |
| 54 | reg = <0x180000 0x0400000>; |
| 55 | }; |
| 56 | |
| 57 | partition@580000 { |
| 58 | label = "FIP"; |
| 59 | reg = <0x580000 0x0200000>; |
| 60 | }; |
| 61 | |
| 62 | partition@780000 { |
| 63 | label = "ubi"; |
developer | 780b915 | 2022-12-15 14:09:45 +0800 | [diff] [blame] | 64 | reg = <0x780000 0x7080000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 65 | }; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | wsys_adie: wsys_adie@0 { |
| 70 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 71 | compatible = "mediatek,rebb-mt7988-adie"; |
| 72 | adie_id = <7976>; |
| 73 | sku_type = <3000>; |
| 74 | }; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 75 | |
| 76 | sound_wm8960 { |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 77 | compatible = "mediatek,mt7986-wm8960-sound"; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 78 | audio-routing = "Headphone", "HP_L", |
| 79 | "Headphone", "HP_R", |
| 80 | "LINPUT1", "AMIC", |
| 81 | "RINPUT1", "AMIC"; |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 82 | |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 83 | status = "disabled"; |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 84 | |
| 85 | platform { |
| 86 | sound-dai = <&afe>; |
| 87 | }; |
| 88 | |
| 89 | codec { |
| 90 | sound-dai = <&wm8960>; |
| 91 | }; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | sound_si3218x { |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 95 | compatible = "mediatek,mt7986-si3218x-sound"; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 96 | status = "disabled"; |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 97 | |
| 98 | platform { |
| 99 | sound-dai = <&afe>; |
| 100 | }; |
| 101 | |
| 102 | codec { |
| 103 | sound-dai = <&proslic_spi>; |
| 104 | }; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 105 | }; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | &fan { |
developer | fce0d15 | 2024-01-11 13:37:13 +0800 | [diff] [blame] | 109 | pwms = <&pwm 0 50000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 110 | status = "okay"; |
| 111 | }; |
| 112 | |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 113 | &afe { |
| 114 | pinctrl-names = "default"; |
| 115 | pinctrl-0 = <&pcm_pins>; |
| 116 | status = "okay"; |
| 117 | }; |
| 118 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 119 | &pwm { |
| 120 | status = "okay"; |
| 121 | }; |
| 122 | |
| 123 | &uart0 { |
| 124 | status = "okay"; |
| 125 | }; |
| 126 | |
developer | 58a4fa0 | 2023-04-21 11:02:05 +0800 | [diff] [blame] | 127 | &uart1 { |
| 128 | pinctrl-names = "default"; |
| 129 | pinctrl-0 = <&uart1_pins>; |
| 130 | status = "okay"; |
| 131 | }; |
| 132 | |
developer | afda357 | 2022-12-28 16:28:30 +0800 | [diff] [blame] | 133 | &i2c0 { |
| 134 | pinctrl-names = "default"; |
| 135 | pinctrl-0 = <&i2c0_pins>; |
| 136 | status = "okay"; |
| 137 | |
| 138 | rt5190a_64: rt5190a@64 { |
| 139 | compatible = "richtek,rt5190a"; |
| 140 | reg = <0x64>; |
| 141 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 142 | vin2-supply = <&rt5190_buck1>; |
| 143 | vin3-supply = <&rt5190_buck1>; |
| 144 | vin4-supply = <&rt5190_buck1>; |
| 145 | |
| 146 | regulators { |
| 147 | rt5190_buck1: buck1 { |
| 148 | regulator-name = "rt5190a-buck1"; |
| 149 | regulator-min-microvolt = <5090000>; |
| 150 | regulator-max-microvolt = <5090000>; |
| 151 | regulator-allowed-modes = |
| 152 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 153 | regulator-boot-on; |
| 154 | }; |
| 155 | buck2 { |
| 156 | regulator-name = "vcore"; |
| 157 | regulator-min-microvolt = <600000>; |
| 158 | regulator-max-microvolt = <1400000>; |
| 159 | regulator-boot-on; |
| 160 | }; |
| 161 | buck3 { |
| 162 | regulator-name = "proc"; |
| 163 | regulator-min-microvolt = <600000>; |
| 164 | regulator-max-microvolt = <1400000>; |
| 165 | regulator-boot-on; |
| 166 | }; |
| 167 | buck4 { |
| 168 | regulator-name = "rt5190a-buck4"; |
| 169 | regulator-min-microvolt = <850000>; |
| 170 | regulator-max-microvolt = <850000>; |
| 171 | regulator-allowed-modes = |
| 172 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 173 | regulator-boot-on; |
| 174 | }; |
| 175 | ldo { |
| 176 | regulator-name = "rt5190a-ldo"; |
| 177 | regulator-min-microvolt = <1200000>; |
| 178 | regulator-max-microvolt = <1200000>; |
| 179 | regulator-boot-on; |
| 180 | }; |
| 181 | }; |
| 182 | }; |
| 183 | }; |
| 184 | |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 185 | &i2c1 { |
| 186 | pinctrl-names = "default"; |
| 187 | pinctrl-0 = <&i2c1_pins>; |
| 188 | status = "okay"; |
| 189 | |
| 190 | wm8960: wm8960@1a { |
| 191 | compatible = "wlf,wm8960"; |
| 192 | reg = <0x1a>; |
| 193 | }; |
developer | b69ecef | 2023-03-08 15:40:24 +0800 | [diff] [blame] | 194 | |
developer | a05cf4c | 2023-10-27 14:35:41 +0800 | [diff] [blame] | 195 | zts8032: zts8032@77 { |
| 196 | compatible = "zilltek,zts8032"; |
| 197 | reg = <0x76>; |
| 198 | }; |
| 199 | |
developer | b69ecef | 2023-03-08 15:40:24 +0800 | [diff] [blame] | 200 | dps368: dps368@77 { |
| 201 | compatible = "infineon,dps310"; |
| 202 | reg = <0x77>; |
| 203 | }; |
developer | 1490648 | 2023-06-27 11:33:16 +0800 | [diff] [blame] | 204 | |
| 205 | rtq6056: rtq6056@40 { |
| 206 | compatible = "richtek,rtq6056"; |
| 207 | reg = <0x40>; |
| 208 | shunt-resistor-micro-ohms = <10000>; |
| 209 | #io-channel-cells = <1>; |
| 210 | }; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 211 | }; |
| 212 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 213 | &spi0 { |
| 214 | pinctrl-names = "default"; |
| 215 | pinctrl-0 = <&spi0_flash_pins>; |
| 216 | status = "okay"; |
| 217 | |
| 218 | spi_nand: spi_nand@0 { |
| 219 | #address-cells = <1>; |
| 220 | #size-cells = <1>; |
| 221 | compatible = "spi-nand"; |
| 222 | spi-cal-enable; |
| 223 | spi-cal-mode = "read-data"; |
| 224 | spi-cal-datalen = <7>; |
| 225 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 226 | spi-cal-addrlen = <5>; |
| 227 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 228 | reg = <0>; |
| 229 | spi-max-frequency = <52000000>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 230 | spi-tx-bus-width = <4>; |
| 231 | spi-rx-bus-width = <4>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 232 | }; |
| 233 | }; |
| 234 | |
| 235 | &spi1 { |
| 236 | pinctrl-names = "default"; |
| 237 | /* pin shared with snfi */ |
| 238 | pinctrl-0 = <&spic_pins>; |
| 239 | status = "disabled"; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 240 | |
| 241 | proslic_spi: proslic_spi@0 { |
| 242 | compatible = "silabs,proslic_spi"; |
| 243 | reg = <0>; |
| 244 | spi-max-frequency = <10000000>; |
| 245 | spi-cpha = <1>; |
| 246 | spi-cpol = <1>; |
| 247 | channel_count = <1>; |
| 248 | debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ |
| 249 | reset_gpio = <&pio 54 0>; |
| 250 | ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ |
| 251 | }; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | &pcie0 { |
| 255 | pinctrl-names = "default"; |
| 256 | pinctrl-0 = <&pcie0_pins>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 257 | wifi-reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; |
| 258 | wifi-reset-msleep = <100>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 259 | status = "okay"; |
| 260 | }; |
| 261 | |
| 262 | &pcie1 { |
| 263 | pinctrl-names = "default"; |
| 264 | pinctrl-0 = <&pcie1_pins>; |
| 265 | status = "okay"; |
| 266 | }; |
| 267 | |
| 268 | &pcie2 { |
| 269 | pinctrl-names = "default"; |
| 270 | pinctrl-0 = <&pcie2_pins>; |
| 271 | status = "disabled"; |
| 272 | }; |
| 273 | |
| 274 | &pcie3 { |
| 275 | pinctrl-names = "default"; |
| 276 | pinctrl-0 = <&pcie3_pins>; |
| 277 | status = "okay"; |
| 278 | }; |
| 279 | |
| 280 | &pio { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 281 | mdio0_pins: mdio0-pins { |
| 282 | mux { |
| 283 | function = "mdio"; |
| 284 | groups = "mdc_mdio0"; |
| 285 | }; |
| 286 | |
| 287 | conf { |
| 288 | groups = "mdc_mdio0"; |
developer | edbe69e | 2023-06-08 11:08:46 +0800 | [diff] [blame] | 289 | drive-strength = <MTK_DRIVE_10mA>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 290 | }; |
| 291 | }; |
| 292 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 293 | gbe0_led0_pins: gbe0-pins { |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 294 | mux { |
| 295 | function = "led"; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 296 | groups = "gbe0_led0"; |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 297 | }; |
| 298 | }; |
| 299 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 300 | gbe1_led0_pins: gbe1-pins { |
| 301 | mux { |
| 302 | function = "led"; |
| 303 | groups = "gbe1_led0"; |
| 304 | }; |
| 305 | }; |
| 306 | |
| 307 | gbe2_led0_pins: gbe2-pins { |
| 308 | mux { |
| 309 | function = "led"; |
| 310 | groups = "gbe2_led0"; |
| 311 | }; |
| 312 | }; |
| 313 | |
| 314 | gbe3_led0_pins: gbe3-pins { |
| 315 | mux { |
| 316 | function = "led"; |
| 317 | groups = "gbe3_led0"; |
| 318 | }; |
| 319 | }; |
| 320 | |
developer | afda357 | 2022-12-28 16:28:30 +0800 | [diff] [blame] | 321 | i2c0_pins: i2c0-pins-g0 { |
| 322 | mux { |
| 323 | function = "i2c"; |
| 324 | groups = "i2c0_1"; |
| 325 | }; |
| 326 | }; |
| 327 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 328 | pcie0_pins: pcie0-pins { |
| 329 | mux { |
| 330 | function = "pcie"; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 331 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 332 | }; |
| 333 | }; |
| 334 | |
| 335 | pcie1_pins: pcie1-pins { |
| 336 | mux { |
| 337 | function = "pcie"; |
| 338 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 339 | "pcie_wake_n1_0"; |
| 340 | }; |
| 341 | }; |
| 342 | |
| 343 | pcie2_pins: pcie2-pins { |
| 344 | mux { |
| 345 | function = "pcie"; |
| 346 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 347 | "pcie_wake_n2_0"; |
| 348 | }; |
| 349 | }; |
| 350 | |
| 351 | pcie3_pins: pcie3-pins { |
| 352 | mux { |
| 353 | function = "pcie"; |
| 354 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 355 | "pcie_wake_n3_0"; |
| 356 | }; |
| 357 | }; |
| 358 | |
| 359 | spi0_flash_pins: spi0-pins { |
| 360 | mux { |
| 361 | function = "spi"; |
| 362 | groups = "spi0", "spi0_wp_hold"; |
| 363 | }; |
| 364 | }; |
| 365 | |
| 366 | spic_pins: spi1-pins { |
| 367 | mux { |
| 368 | function = "spi"; |
developer | c859294 | 2022-10-31 14:07:50 +0800 | [diff] [blame] | 369 | groups = "spi1"; |
| 370 | }; |
| 371 | }; |
| 372 | |
| 373 | i2c1_pins: i2c1-pins { |
| 374 | mux { |
| 375 | function = "i2c"; |
| 376 | groups = "i2c1_0"; |
| 377 | }; |
| 378 | }; |
| 379 | |
| 380 | i2s_pins: i2s-pins { |
| 381 | mux { |
| 382 | function = "audio"; |
| 383 | groups = "i2s"; |
| 384 | }; |
| 385 | }; |
| 386 | |
| 387 | pcm_pins: pcm-pins { |
| 388 | mux { |
| 389 | function = "audio"; |
| 390 | groups = "pcm"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 391 | }; |
| 392 | }; |
developer | 58a4fa0 | 2023-04-21 11:02:05 +0800 | [diff] [blame] | 393 | |
| 394 | uart1_pins: uart1-pins { |
| 395 | mux { |
| 396 | function = "uart"; |
| 397 | groups = "uart1_2"; |
| 398 | }; |
| 399 | }; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 400 | }; |
| 401 | |
| 402 | &watchdog { |
| 403 | status = "disabled"; |
| 404 | }; |
| 405 | |
| 406 | ð { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 407 | pinctrl-names = "default"; |
| 408 | pinctrl-0 = <&mdio0_pins>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 409 | status = "okay"; |
| 410 | |
| 411 | gmac0: mac@0 { |
| 412 | compatible = "mediatek,eth-mac"; |
| 413 | reg = <0>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 414 | mac-type = "xgdm"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 415 | phy-mode = "10gbase-kr"; |
| 416 | |
| 417 | fixed-link { |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 418 | speed = <10000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 419 | full-duplex; |
| 420 | pause; |
| 421 | }; |
| 422 | }; |
| 423 | |
| 424 | gmac1: mac@1 { |
| 425 | compatible = "mediatek,eth-mac"; |
| 426 | reg = <1>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 427 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 428 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 429 | phy-handle = <&phy0>; |
| 430 | }; |
| 431 | |
| 432 | gmac2: mac@2 { |
| 433 | compatible = "mediatek,eth-mac"; |
| 434 | reg = <2>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 435 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 436 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 437 | phy-handle = <&phy1>; |
| 438 | }; |
| 439 | |
| 440 | mdio: mdio-bus { |
| 441 | #address-cells = <1>; |
| 442 | #size-cells = <0>; |
developer | 9faf1ef | 2023-03-21 16:49:51 +0800 | [diff] [blame] | 443 | clock-frequency = <10500000>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 444 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 445 | phy0: ethernet-phy@0 { |
| 446 | reg = <0>; |
| 447 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 448 | reset-gpios = <&pio 72 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 449 | reset-assert-us = <100000>; |
| 450 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 451 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 452 | }; |
| 453 | |
| 454 | phy1: ethernet-phy@8 { |
| 455 | reg = <8>; |
| 456 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 457 | reset-gpios = <&pio 71 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 458 | reset-assert-us = <100000>; |
| 459 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 460 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 461 | }; |
| 462 | |
| 463 | switch@0 { |
| 464 | compatible = "mediatek,mt7988"; |
| 465 | reg = <31>; |
| 466 | ports { |
| 467 | #address-cells = <1>; |
| 468 | #size-cells = <0>; |
| 469 | |
| 470 | port@0 { |
| 471 | reg = <0>; |
| 472 | label = "lan0"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 473 | phy-mode = "gmii"; |
| 474 | phy-handle = <&sphy0>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 475 | }; |
| 476 | |
| 477 | port@1 { |
| 478 | reg = <1>; |
| 479 | label = "lan1"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 480 | phy-mode = "gmii"; |
| 481 | phy-handle = <&sphy1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 482 | }; |
| 483 | |
| 484 | port@2 { |
| 485 | reg = <2>; |
| 486 | label = "lan2"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 487 | phy-mode = "gmii"; |
| 488 | phy-handle = <&sphy2>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 489 | }; |
| 490 | |
| 491 | port@3 { |
| 492 | reg = <3>; |
| 493 | label = "lan3"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 494 | phy-mode = "gmii"; |
| 495 | phy-handle = <&sphy3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 496 | }; |
| 497 | |
| 498 | port@6 { |
| 499 | reg = <6>; |
| 500 | label = "cpu"; |
| 501 | ethernet = <&gmac0>; |
| 502 | phy-mode = "10gbase-kr"; |
| 503 | |
| 504 | fixed-link { |
| 505 | speed = <10000>; |
| 506 | full-duplex; |
| 507 | pause; |
| 508 | }; |
| 509 | }; |
| 510 | }; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 511 | |
| 512 | mdio { |
| 513 | compatible = "mediatek,dsa-slave-mdio"; |
| 514 | #address-cells = <1>; |
| 515 | #size-cells = <0>; |
| 516 | |
| 517 | sphy0: switch_phy0@0 { |
| 518 | compatible = "ethernet-phy-id03a2.9481"; |
| 519 | reg = <0>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 520 | pinctrl-names = "gbe-led"; |
| 521 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 522 | nvmem-cells = <&phy_calibration_p0>; |
| 523 | nvmem-cell-names = "phy-cal-data"; |
| 524 | }; |
| 525 | |
| 526 | sphy1: switch_phy1@1 { |
| 527 | compatible = "ethernet-phy-id03a2.9481"; |
| 528 | reg = <1>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 529 | pinctrl-names = "gbe-led"; |
| 530 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 531 | nvmem-cells = <&phy_calibration_p1>; |
| 532 | nvmem-cell-names = "phy-cal-data"; |
| 533 | }; |
| 534 | |
| 535 | sphy2: switch_phy2@2 { |
| 536 | compatible = "ethernet-phy-id03a2.9481"; |
| 537 | reg = <2>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 538 | pinctrl-names = "gbe-led"; |
| 539 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 540 | nvmem-cells = <&phy_calibration_p2>; |
| 541 | nvmem-cell-names = "phy-cal-data"; |
| 542 | }; |
| 543 | |
| 544 | sphy3: switch_phy3@3 { |
| 545 | compatible = "ethernet-phy-id03a2.9481"; |
| 546 | reg = <3>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 547 | pinctrl-names = "gbe-led"; |
| 548 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 549 | nvmem-cells = <&phy_calibration_p3>; |
| 550 | nvmem-cell-names = "phy-cal-data"; |
| 551 | }; |
| 552 | }; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 553 | }; |
| 554 | }; |
| 555 | }; |
| 556 | |
| 557 | &hnat { |
| 558 | mtketh-wan = "eth1"; |
| 559 | mtketh-lan = "lan"; |
| 560 | mtketh-lan2 = "eth2"; |
| 561 | mtketh-max-gmac = <3>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame^] | 562 | mtketh-ppe-num = <3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 563 | status = "okay"; |
| 564 | }; |
developer | 02f89f7 | 2023-02-02 15:26:12 +0800 | [diff] [blame] | 565 | |
| 566 | &slot0 { |
| 567 | mt7996@0,0 { |
| 568 | reg = <0x0000 0 0 0 0>; |
| 569 | device_type = "pci"; |
| 570 | mediatek,mtd-eeprom = <&factory 0x0>; |
| 571 | }; |
| 572 | }; |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 573 | |
| 574 | &slot1 { |
| 575 | mt7992@0,0 { |
| 576 | reg = <0x0000 0 0 0 0>; |
| 577 | device_type = "pci"; |
| 578 | mediatek,mtd-eeprom = <&factory 0x0>; |
| 579 | }; |
| 580 | }; |