blob: d112dc72d7ecc08a6637ef049a062a7fe4991697 [file] [log] [blame]
developerb9b4cd12022-10-11 13:18:59 +08001#define _GNU_SOURCE
2#include <fcntl.h>
3#include <sys/mman.h>
4#include <sys/stat.h>
5#include <sys/wait.h>
6
7#include "atenl.h"
8
developer963a66b2023-04-11 13:34:56 +08009#define EEPROM_PART_SIZE 0xFF000
developerb9b4cd12022-10-11 13:18:59 +080010char *eeprom_file;
11
developer42126682022-11-04 16:03:09 +080012static int
13atenl_create_file(struct atenl *an, bool flash_mode)
developerb9b4cd12022-10-11 13:18:59 +080014{
developer42126682022-11-04 16:03:09 +080015 char fname[64], buf[1024];
16 ssize_t w, len, max_len, total_len = 0;
17 int fd_ori, fd, ret;
developerb9b4cd12022-10-11 13:18:59 +080018
developer42126682022-11-04 16:03:09 +080019 /* reserve space for pre-cal data in flash mode */
20 if (flash_mode) {
developer70180b02023-11-14 17:01:47 +080021 atenl_dbg("%s: init eeprom with flash / binfile mode\n", __func__);
developer42126682022-11-04 16:03:09 +080022 max_len = EEPROM_PART_SIZE;
23 } else {
developer70180b02023-11-14 17:01:47 +080024 atenl_dbg("%s: init eeprom with efuse / default bin mode\n", __func__);
developer13655da2023-01-10 19:53:25 +080025 max_len = 0x1e00;
developerb9b4cd12022-10-11 13:18:59 +080026 }
developerb9b4cd12022-10-11 13:18:59 +080027
developer42126682022-11-04 16:03:09 +080028 snprintf(fname, sizeof(fname),
29 "/sys/kernel/debug/ieee80211/phy%d/mt76/eeprom",
30 get_band_val(an, 0, phy_idx));
31 fd_ori = open(fname, O_RDONLY);
32 if (fd_ori < 0)
developerb9b4cd12022-10-11 13:18:59 +080033 return -1;
developerb9b4cd12022-10-11 13:18:59 +080034
35 fd = open(eeprom_file, O_RDWR | O_CREAT | O_EXCL, 00644);
36 if (fd < 0)
37 goto out;
38
developer42126682022-11-04 16:03:09 +080039 while ((len = read(fd_ori, buf, sizeof(buf))) > 0) {
developerb9b4cd12022-10-11 13:18:59 +080040retry:
41 w = write(fd, buf, len);
42 if (w > 0) {
developer42126682022-11-04 16:03:09 +080043 total_len += len;
developerb9b4cd12022-10-11 13:18:59 +080044 continue;
45 }
46
47 if (errno == EINTR)
48 goto retry;
49
50 perror("write");
51 unlink(eeprom_file);
52 close(fd);
53 fd = -1;
54 goto out;
55 }
56
developer42126682022-11-04 16:03:09 +080057 /* reserve space for pre-cal data in flash mode */
58 len = sizeof(buf);
59 memset(buf, 0, len);
60 while (total_len < max_len) {
developerb9b4cd12022-10-11 13:18:59 +080061 w = write(fd, buf, len);
developerb9b4cd12022-10-11 13:18:59 +080062
developer42126682022-11-04 16:03:09 +080063 if (w > 0) {
64 total_len += len;
65 continue;
66 }
developerb9b4cd12022-10-11 13:18:59 +080067
developer42126682022-11-04 16:03:09 +080068 if (errno != EINTR) {
69 perror("write");
70 unlink(eeprom_file);
71 close(fd);
72 fd = -1;
73 goto out;
74 }
developerb9b4cd12022-10-11 13:18:59 +080075 }
76
developer42126682022-11-04 16:03:09 +080077
developerb9b4cd12022-10-11 13:18:59 +080078 ret = lseek(fd, 0, SEEK_SET);
79 if (ret) {
80 close(fd_ori);
81 close(fd);
82 return ret;
83 }
84
85out:
86 close(fd_ori);
87 return fd;
88}
89
90static bool
91atenl_eeprom_file_exists(void)
92{
93 struct stat st;
94
95 return stat(eeprom_file, &st) == 0;
96}
97
98static int
99atenl_eeprom_init_file(struct atenl *an, bool flash_mode)
100{
101 int fd;
102
developer42126682022-11-04 16:03:09 +0800103 if (!atenl_eeprom_file_exists())
104 return atenl_create_file(an, flash_mode);
developerb9b4cd12022-10-11 13:18:59 +0800105
106 fd = open(eeprom_file, O_RDWR);
107 if (fd < 0)
108 perror("open");
109
110 return fd;
111}
112
113static void
114atenl_eeprom_init_chip_id(struct atenl *an)
115{
116 an->chip_id = *(u16 *)an->eeprom_data;
117
118 if (is_mt7915(an)) {
119 an->adie_id = 0x7975;
developer70180b02023-11-14 17:01:47 +0800120 } else if (is_mt7916(an) || is_mt7981(an)) {
developerb9b4cd12022-10-11 13:18:59 +0800121 an->adie_id = 0x7976;
122 } else if (is_mt7986(an)) {
123 bool is_7975 = false;
124 u32 val;
125 u8 sub_id;
126
127 atenl_reg_read(an, 0x18050000, &val);
128
129 switch (val & 0xf) {
130 case MT7975_ONE_ADIE_SINGLE_BAND:
131 is_7975 = true;
132 /* fallthrough */
133 case MT7976_ONE_ADIE_SINGLE_BAND:
134 sub_id = 0xa;
135 break;
136 case MT7976_ONE_ADIE_DBDC:
137 sub_id = 0x7;
138 break;
139 case MT7975_DUAL_ADIE_DBDC:
140 is_7975 = true;
141 /* fallthrough */
142 case MT7976_DUAL_ADIE_DBDC:
143 default:
144 sub_id = 0xf;
145 break;
146 }
147
148 an->sub_chip_id = sub_id;
149 an->adie_id = is_7975 ? 0x7975 : 0x7976;
developer13655da2023-01-10 19:53:25 +0800150 } else if (is_mt7996(an)) {
151 /* TODO: parse info if required */
developer2299de92023-10-27 15:40:47 +0800152 } else if (is_mt7992(an)) {
153 /* TODO: parse info if required */
developerb9b4cd12022-10-11 13:18:59 +0800154 }
155}
156
157static void
158atenl_eeprom_init_max_size(struct atenl *an)
159{
160 switch (an->chip_id) {
161 case 0x7915:
162 an->eeprom_size = 3584;
163 an->eeprom_prek_offs = 0x62;
164 break;
165 case 0x7906:
166 case 0x7916:
developer70180b02023-11-14 17:01:47 +0800167 case 0x7981:
developerb9b4cd12022-10-11 13:18:59 +0800168 case 0x7986:
169 an->eeprom_size = 4096;
170 an->eeprom_prek_offs = 0x19a;
171 break;
developer13655da2023-01-10 19:53:25 +0800172 case 0x7990:
developer2299de92023-10-27 15:40:47 +0800173 case 0x7992:
developer13655da2023-01-10 19:53:25 +0800174 an->eeprom_size = 7680;
175 an->eeprom_prek_offs = 0x1a5;
developerb9b4cd12022-10-11 13:18:59 +0800176 default:
177 break;
178 }
179}
180
181static void
182atenl_eeprom_init_band_cap(struct atenl *an)
183{
developer13655da2023-01-10 19:53:25 +0800184#define EAGLE_BAND_SEL(index) MT_EE_WIFI_EAGLE_CONF##index##_BAND_SEL
developerb9b4cd12022-10-11 13:18:59 +0800185 u8 *eeprom = an->eeprom_data;
186
187 if (is_mt7915(an)) {
188 u8 val = eeprom[MT_EE_WIFI_CONF];
189 u8 band_sel = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val);
190 struct atenl_band *anb = &an->anb[0];
191
192 /* MT7915A */
193 if (band_sel == MT_EE_BAND_SEL_DEFAULT) {
194 anb->valid = true;
195 anb->cap = BAND_TYPE_2G_5G;
196 return;
197 }
198
199 /* MT7915D */
200 if (band_sel == MT_EE_BAND_SEL_2GHZ) {
201 anb->valid = true;
202 anb->cap = BAND_TYPE_2G;
203 }
204
205 val = eeprom[MT_EE_WIFI_CONF + 1];
206 band_sel = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val);
207 anb++;
208
209 if (band_sel == MT_EE_BAND_SEL_5GHZ) {
210 anb->valid = true;
211 anb->cap = BAND_TYPE_5G;
212 }
developer70180b02023-11-14 17:01:47 +0800213 } else if (is_mt7916(an) || is_mt7981(an) || is_mt7986(an)) {
developerb9b4cd12022-10-11 13:18:59 +0800214 struct atenl_band *anb;
215 u8 val, band_sel;
216 int i;
217
218 for (i = 0; i < 2; i++) {
219 val = eeprom[MT_EE_WIFI_CONF + i];
220 band_sel = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val);
221 anb = &an->anb[i];
222
223 anb->valid = true;
224 switch (band_sel) {
225 case MT_EE_BAND_SEL_2G:
226 anb->cap = BAND_TYPE_2G;
227 break;
228 case MT_EE_BAND_SEL_5G:
229 anb->cap = BAND_TYPE_5G;
230 break;
231 case MT_EE_BAND_SEL_6G:
232 anb->cap = BAND_TYPE_6G;
233 break;
234 case MT_EE_BAND_SEL_5G_6G:
235 anb->cap = BAND_TYPE_5G_6G;
236 break;
237 default:
238 break;
239 }
240 }
developer13655da2023-01-10 19:53:25 +0800241 } else if (is_mt7996(an)) {
242 struct atenl_band *anb;
243 u8 val, band_sel;
244 u8 band_sel_mask[3] = {EAGLE_BAND_SEL(0), EAGLE_BAND_SEL(1),
245 EAGLE_BAND_SEL(2)};
246 int i;
247
248 for (i = 0; i < 3; i++) {
249 val = eeprom[MT_EE_WIFI_CONF + i];
250 band_sel = FIELD_GET(band_sel_mask[i], val);
251 anb = &an->anb[i];
252
253 anb->valid = true;
254 switch (band_sel) {
255 case MT_EE_EAGLE_BAND_SEL_2GHZ:
256 anb->cap = BAND_TYPE_2G;
257 break;
258 case MT_EE_EAGLE_BAND_SEL_5GHZ:
259 anb->cap = BAND_TYPE_5G;
260 break;
261 case MT_EE_EAGLE_BAND_SEL_6GHZ:
262 anb->cap = BAND_TYPE_6G;
263 break;
264 case MT_EE_EAGLE_BAND_SEL_5GHZ_6GHZ:
265 anb->cap = BAND_TYPE_5G_6G;
266 break;
267 default:
268 break;
269 }
270 }
developer2299de92023-10-27 15:40:47 +0800271 } else if (is_mt7992(an)) {
272 struct atenl_band *anb;
273 u8 val, band_sel;
274 u8 band_sel_mask[2] = {EAGLE_BAND_SEL(0), EAGLE_BAND_SEL(1)};
275 int i;
276
277 for (i = 0; i < 2; i++) {
278 val = eeprom[MT_EE_WIFI_CONF + i];
279 band_sel = FIELD_GET(band_sel_mask[i], val);
280 anb = &an->anb[i];
281
282 anb->valid = true;
283 switch (band_sel) {
284 case MT_EE_EAGLE_BAND_SEL_2GHZ:
285 anb->cap = BAND_TYPE_2G;
286 break;
287 case MT_EE_EAGLE_BAND_SEL_5GHZ:
288 anb->cap = BAND_TYPE_5G;
289 break;
290 case MT_EE_EAGLE_BAND_SEL_6GHZ:
291 anb->cap = BAND_TYPE_6G;
292 break;
293 case MT_EE_EAGLE_BAND_SEL_5GHZ_6GHZ:
294 anb->cap = BAND_TYPE_5G_6G;
295 break;
296 default:
297 break;
298 }
299 }
developerb9b4cd12022-10-11 13:18:59 +0800300 }
301}
302
303static void
304atenl_eeprom_init_antenna_cap(struct atenl *an)
305{
developer2299de92023-10-27 15:40:47 +0800306 switch (an->chip_id) {
307 case 0x7915:
developerb9b4cd12022-10-11 13:18:59 +0800308 if (an->anb[0].cap == BAND_TYPE_2G_5G)
309 an->anb[0].chainmask = 0xf;
310 else {
311 an->anb[0].chainmask = 0x3;
312 an->anb[1].chainmask = 0xc;
313 }
developer2299de92023-10-27 15:40:47 +0800314 break;
315 case 0x7906:
316 case 0x7916:
developerb9b4cd12022-10-11 13:18:59 +0800317 an->anb[0].chainmask = 0x3;
318 an->anb[1].chainmask = 0x3;
developer2299de92023-10-27 15:40:47 +0800319 break;
developer70180b02023-11-14 17:01:47 +0800320 case 0x7981:
321 an->anb[0].chainmask = 0x3;
322 an->anb[1].chainmask = 0x7;
323 break;
developer2299de92023-10-27 15:40:47 +0800324 case 0x7986:
developerb9b4cd12022-10-11 13:18:59 +0800325 an->anb[0].chainmask = 0xf;
326 an->anb[1].chainmask = 0xf;
developer2299de92023-10-27 15:40:47 +0800327 break;
328 case 0x7990:
developer13655da2023-01-10 19:53:25 +0800329 an->anb[0].chainmask = 0xf;
330 an->anb[1].chainmask = 0xf;
331 an->anb[2].chainmask = 0xf;
developer2299de92023-10-27 15:40:47 +0800332 break;
333 case 0x7992:
334 an->anb[0].chainmask = 0xf;
335 an->anb[1].chainmask = 0xf;
336 break;
337 default:
338 break;
developerb9b4cd12022-10-11 13:18:59 +0800339 }
340}
341
342int atenl_eeprom_init(struct atenl *an, u8 phy_idx)
343{
344 bool flash_mode;
345 int eeprom_fd;
346 char buf[30];
347 u8 main_phy_idx = phy_idx;
348
349 set_band_val(an, 0, phy_idx, phy_idx);
350 atenl_nl_check_mtd(an);
351 flash_mode = an->mtd_part != NULL;
352
developer13655da2023-01-10 19:53:25 +0800353 // Get the first main phy index for this chip
developerb9b4cd12022-10-11 13:18:59 +0800354 if (flash_mode)
developer13655da2023-01-10 19:53:25 +0800355 main_phy_idx -= an->band_idx;
developerb9b4cd12022-10-11 13:18:59 +0800356
357 snprintf(buf, sizeof(buf), "/tmp/atenl-eeprom-phy%u", main_phy_idx);
358 eeprom_file = strdup(buf);
359
360 eeprom_fd = atenl_eeprom_init_file(an, flash_mode);
361 if (eeprom_fd < 0)
362 return -1;
363
364 an->eeprom_data = mmap(NULL, EEPROM_PART_SIZE, PROT_READ | PROT_WRITE,
365 MAP_SHARED, eeprom_fd, 0);
366 if (!an->eeprom_data) {
367 perror("mmap");
368 close(eeprom_fd);
369 return -1;
370 }
371
372 an->eeprom_fd = eeprom_fd;
373 atenl_eeprom_init_chip_id(an);
374 atenl_eeprom_init_max_size(an);
375 atenl_eeprom_init_band_cap(an);
376 atenl_eeprom_init_antenna_cap(an);
377
378 if (get_band_val(an, 1, valid))
379 set_band_val(an, 1, phy_idx, phy_idx + 1);
380
developer7af0f762023-05-22 15:16:16 +0800381 if (get_band_val(an, 2, valid))
382 set_band_val(an, 2, phy_idx, phy_idx + 2);
383
developerb9b4cd12022-10-11 13:18:59 +0800384 return 0;
385}
386
387void atenl_eeprom_close(struct atenl *an)
388{
389 msync(an->eeprom_data, EEPROM_PART_SIZE, MS_SYNC);
390 munmap(an->eeprom_data, EEPROM_PART_SIZE);
391 close(an->eeprom_fd);
392
393 if (!an->cmd_mode) {
394 if (remove(eeprom_file))
395 perror("remove");
396 }
397
398 free(eeprom_file);
399}
400
401int atenl_eeprom_update_precal(struct atenl *an, int write_offs, int size)
402{
403 u32 offs = an->eeprom_prek_offs;
404 u8 cal_indicator, *eeprom, *pre_cal;
405
406 if (!an->cal && !an->cal_info)
407 return 0;
408
409 eeprom = an->eeprom_data;
410 pre_cal = eeprom + an->eeprom_size;
411 cal_indicator = an->cal_info[4];
412
413 memcpy(eeprom + offs, &cal_indicator, sizeof(u8));
414 memcpy(pre_cal, an->cal_info, PRE_CAL_INFO);
415 pre_cal += (PRE_CAL_INFO + write_offs);
416
417 if (an->cal)
418 memcpy(pre_cal, an->cal, size);
419 else
420 memset(pre_cal, 0, size);
421
422 return 0;
423}
424
425int atenl_eeprom_write_mtd(struct atenl *an)
426{
developer70180b02023-11-14 17:01:47 +0800427#define TMP_FILE "/tmp/tmp_eeprom.bin"
developerb9b4cd12022-10-11 13:18:59 +0800428 pid_t pid;
developer70180b02023-11-14 17:01:47 +0800429 u32 size = an->eeprom_size;
430 u32 *precal_info = an->eeprom_data + an->eeprom_size;
431 u32 precal_size = precal_info[0] + precal_info[1];
432 char cmd[100];
developerb9b4cd12022-10-11 13:18:59 +0800433
developer70180b02023-11-14 17:01:47 +0800434 if (an->mtd_part == NULL || !(~an->mtd_offset))
developerb9b4cd12022-10-11 13:18:59 +0800435 return 0;
436
developer70180b02023-11-14 17:01:47 +0800437 if (precal_size)
438 size += PRE_CAL_INFO + precal_size;
developerb9b4cd12022-10-11 13:18:59 +0800439
developer70180b02023-11-14 17:01:47 +0800440 sprintf(cmd, "dd if=%s of=%s bs=1 count=%d", eeprom_file, TMP_FILE, size);
441 system(cmd);
442
443 sprintf(cmd, "mtd -p %d write %s %s", an->mtd_offset, TMP_FILE, an->mtd_part);
444 system(cmd);
445
446 sprintf(cmd, "rm %s", TMP_FILE);
447 system(cmd);
developerb9b4cd12022-10-11 13:18:59 +0800448
449 return 0;
450}
451
452/* Directly read values from driver's eeprom.
453 * It's usally used to get calibrated data from driver.
454 */
455int atenl_eeprom_read_from_driver(struct atenl *an, u32 offset, int len)
456{
457 u8 *eeprom_data = an->eeprom_data + offset;
458 char fname[64], buf[1024];
459 int fd_ori, ret;
460 ssize_t rd;
461
462 snprintf(fname, sizeof(fname),
463 "/sys/kernel/debug/ieee80211/phy%d/mt76/eeprom",
464 get_band_val(an, 0, phy_idx));
465 fd_ori = open(fname, O_RDONLY);
466 if (fd_ori < 0)
467 return -1;
468
469 ret = lseek(fd_ori, offset, SEEK_SET);
470 if (ret < 0)
471 goto out;
472
473 while ((rd = read(fd_ori, buf, sizeof(buf))) > 0 && len) {
474 if (len < rd) {
475 memcpy(eeprom_data, buf, len);
476 break;
477 } else {
478 memcpy(eeprom_data, buf, rd);
479 eeprom_data += rd;
480 len -= rd;
481 }
482 }
483
484 ret = 0;
485out:
486 close(fd_ori);
487 return ret;
488}
489
490/* Update all eeprom values to driver before writing efuse */
491static void
492atenl_eeprom_sync_to_driver(struct atenl *an)
493{
494 int i;
495
496 for (i = 0; i < an->eeprom_size; i += 16)
497 atenl_nl_write_eeprom(an, i, &an->eeprom_data[i], 16);
498}
499
500void atenl_eeprom_cmd_handler(struct atenl *an, u8 phy_idx, char *cmd)
501{
developerb9b4cd12022-10-11 13:18:59 +0800502 an->cmd_mode = true;
503
504 atenl_eeprom_init(an, phy_idx);
developerb9b4cd12022-10-11 13:18:59 +0800505
506 if (!strncmp(cmd, "sync eeprom all", 15)) {
507 atenl_eeprom_write_mtd(an);
508 } else if (!strncmp(cmd, "eeprom", 6)) {
509 char *s = strchr(cmd, ' ');
510
511 if (!s) {
512 atenl_err("eeprom: please type a correct command\n");
513 return;
514 }
515
516 s++;
517 if (!strncmp(s, "reset", 5)) {
518 unlink(eeprom_file);
519 } else if (!strncmp(s, "file", 4)) {
520 atenl_info("%s\n", eeprom_file);
developer70180b02023-11-14 17:01:47 +0800521 if (an->mtd_part != NULL)
522 atenl_info("%s mode\n",
523 ~an->mtd_offset == 0 ? "Binfile" : "Flash");
524 else
525 atenl_info("Efuse / Default bin mode\n");
developerb9b4cd12022-10-11 13:18:59 +0800526 } else if (!strncmp(s, "set", 3)) {
527 u32 offset, val;
528
529 s = strchr(s, ' ');
530 if (!s)
531 return;
532 s++;
533
534 if (!sscanf(s, "%x=%x", &offset, &val) ||
535 offset > EEPROM_PART_SIZE)
536 return;
537
538 an->eeprom_data[offset] = val;
539 atenl_info("set offset 0x%x to 0x%x\n", offset, val);
540 } else if (!strncmp(s, "update buffermode", 17)) {
541 atenl_eeprom_sync_to_driver(an);
542 atenl_nl_update_buffer_mode(an);
543 } else if (!strncmp(s, "write", 5)) {
544 s = strchr(s, ' ');
545 if (!s)
546 return;
547 s++;
548
549 if (!strncmp(s, "flash", 5)) {
550 atenl_eeprom_write_mtd(an);
developer2299de92023-10-27 15:40:47 +0800551 } else if (!strncmp(s, "to efuse", 8)) {
552 atenl_eeprom_sync_to_driver(an);
553 atenl_nl_write_efuse_all(an);
554 }
developerb9b4cd12022-10-11 13:18:59 +0800555 } else if (!strncmp(s, "read", 4)) {
556 u32 offset;
557
558 s = strchr(s, ' ');
559 if (!s)
560 return;
561 s++;
562
563 if (!sscanf(s, "%x", &offset) ||
564 offset > EEPROM_PART_SIZE)
565 return;
566
567 atenl_info("val = 0x%x (%u)\n", an->eeprom_data[offset],
568 an->eeprom_data[offset]);
569 } else if (!strncmp(s, "precal", 6)) {
570 s = strchr(s, ' ');
571 if (!s)
572 return;
573 s++;
574
575 if (!strncmp(s, "sync group", 10)) {
576 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_GROUP);
577 } else if (!strncmp(s, "sync dpd 2g", 11)) {
578 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_DPD_2G);
579 } else if (!strncmp(s, "sync dpd 5g", 11)) {
580 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_DPD_5G);
581 } else if (!strncmp(s, "sync dpd 6g", 11)) {
582 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_DPD_6G);
583 } else if (!strncmp(s, "group clean", 11)) {
584 atenl_nl_precal_sync_from_driver(an, PREK_CLEAN_GROUP);
585 } else if (!strncmp(s, "dpd clean", 9)) {
586 atenl_nl_precal_sync_from_driver(an, PREK_CLEAN_DPD);
587 } else if (!strncmp(s, "sync", 4)) {
588 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_ALL);
589 }
developerf9b00212023-07-31 12:27:06 +0800590 } else if (!strncmp(s, "ibf sync", 8)) {
591 atenl_get_ibf_cal_result(an);
developerb9b4cd12022-10-11 13:18:59 +0800592 } else {
developerf9b00212023-07-31 12:27:06 +0800593 atenl_err("Unknown eeprom command: %s\n", cmd);
594 }
developerb9b4cd12022-10-11 13:18:59 +0800595 } else {
596 atenl_err("Unknown command: %s\n", cmd);
597 }
598}