developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1 | From 56e9bf306919ffb33d45951541d908cd7d21c081 Mon Sep 17 00:00:00 2001 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 2 | From: Bo Jiao <Bo.Jiao@mediatek.com> |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 3 | Date: Mon, 18 Sep 2023 11:01:55 +0800 |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 4 | Subject: [PATCH 06/24] add-wed-tx-support-for-netsys2 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 7 | arch/arm64/boot/dts/mediatek/mt7981.dtsi | 1 + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 8 | arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 6 +- |
| 9 | arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 6 +- |
| 10 | drivers/net/ethernet/mediatek/mtk_eth_soc.c | 41 +- |
| 11 | drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 - |
| 12 | drivers/net/ethernet/mediatek/mtk_wed.c | 525 +++++++++++++----- |
| 13 | drivers/net/ethernet/mediatek/mtk_wed.h | 21 +- |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 14 | .../net/ethernet/mediatek/mtk_wed_debugfs.c | 3 + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 15 | drivers/net/ethernet/mediatek/mtk_wed_regs.h | 111 +++- |
| 16 | include/linux/soc/mediatek/mtk_wed.h | 21 +- |
| 17 | 10 files changed, 575 insertions(+), 163 deletions(-) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 18 | |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 19 | diff --git a/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 20 | index 283421a..cb8f4e1 100644 |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 21 | --- a/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 22 | +++ b/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 23 | @@ -96,6 +96,7 @@ |
| 24 | reg = <0 0x15010000 0 0x1000>; |
| 25 | interrupt-parent = <&gic>; |
| 26 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 27 | + mediatek,wed_pcie = <&wed_pcie>; |
| 28 | }; |
| 29 | |
| 30 | ap2woccif: ap2woccif@151A5000 { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 31 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 32 | index d70151b..9c288fc 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 33 | --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 34 | +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 35 | @@ -64,6 +64,7 @@ |
| 36 | reg = <0 0x15010000 0 0x1000>; |
| 37 | interrupt-parent = <&gic>; |
| 38 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 39 | + mediatek,wed_pcie = <&wed_pcie>; |
| 40 | }; |
| 41 | |
| 42 | wed1: wed@15011000 { |
| 43 | @@ -72,6 +73,7 @@ |
| 44 | reg = <0 0x15011000 0 0x1000>; |
| 45 | interrupt-parent = <&gic>; |
| 46 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 47 | + mediatek,wed_pcie = <&wed_pcie>; |
| 48 | }; |
| 49 | |
| 50 | ap2woccif: ap2woccif@151A5000 { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 51 | @@ -482,6 +484,7 @@ |
| 52 | <&topckgen CK_TOP_CB_SGM_325M>; |
| 53 | mediatek,ethsys = <ðsys>; |
| 54 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 55 | + mediatek,wed-pcie = <&wed_pcie>; |
| 56 | mediatek,wed = <&wed0>, <&wed1>; |
| 57 | mtketh-ppe-num = <2>; |
| 58 | #reset-cells = <1>; |
| 59 | @@ -549,7 +552,8 @@ |
| 60 | }; |
| 61 | |
| 62 | wed_pcie: wed_pcie@10003000 { |
| 63 | - compatible = "mediatek,wed_pcie"; |
| 64 | + compatible = "mediatek,wed_pcie", |
| 65 | + "syscon"; |
| 66 | reg = <0 0x10003000 0 0x10>; |
| 67 | }; |
| 68 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 69 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 70 | index ce884f0..02feaa9 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 71 | --- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 72 | +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 73 | @@ -64,6 +64,7 @@ |
| 74 | reg = <0 0x15010000 0 0x1000>; |
| 75 | interrupt-parent = <&gic>; |
| 76 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 77 | + mediatek,wed_pcie = <&wed_pcie>; |
| 78 | }; |
| 79 | |
| 80 | wed1: wed@15011000 { |
| 81 | @@ -72,6 +73,7 @@ |
| 82 | reg = <0 0x15011000 0 0x1000>; |
| 83 | interrupt-parent = <&gic>; |
| 84 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 85 | + mediatek,wed_pcie = <&wed_pcie>; |
| 86 | }; |
| 87 | |
| 88 | ap2woccif: ap2woccif@151A5000 { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 89 | @@ -396,6 +398,7 @@ |
| 90 | <&topckgen CK_TOP_CB_SGM_325M>; |
| 91 | mediatek,ethsys = <ðsys>; |
| 92 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 93 | + mediatek,wed-pcie = <&wed_pcie>; |
| 94 | mediatek,wed = <&wed0>, <&wed1>; |
| 95 | #reset-cells = <1>; |
| 96 | #address-cells = <1>; |
| 97 | @@ -462,7 +465,8 @@ |
| 98 | }; |
| 99 | |
| 100 | wed_pcie: wed_pcie@10003000 { |
| 101 | - compatible = "mediatek,wed_pcie"; |
| 102 | + compatible = "mediatek,wed_pcie", |
| 103 | + "syscon"; |
| 104 | reg = <0 0x10003000 0 0x10>; |
| 105 | }; |
| 106 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 107 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 108 | index 07209f0..268c9e7 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 109 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 110 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 111 | @@ -5476,6 +5476,7 @@ static int mtk_probe(struct platform_device *pdev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 112 | { |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 113 | struct device_node *mac_np, *mux_np; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 114 | struct mtk_eth *eth; |
| 115 | + struct resource *res = NULL; |
| 116 | int err, i; |
| 117 | |
| 118 | eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 119 | @@ -5498,13 +5499,12 @@ static int mtk_probe(struct platform_device *pdev) |
| 120 | eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; |
developer | 3c9c74d | 2023-09-11 11:36:12 +0800 | [diff] [blame] | 121 | } |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 122 | |
developer | 3c9c74d | 2023-09-11 11:36:12 +0800 | [diff] [blame] | 123 | - if(eth->soc->has_sram) { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 124 | - struct resource *res; |
developer | 3c9c74d | 2023-09-11 11:36:12 +0800 | [diff] [blame] | 125 | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 126 | - if (unlikely(!res)) |
| 127 | - return -EINVAL; |
| 128 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 129 | + if (unlikely(!res)) |
| 130 | + return -EINVAL; |
| 131 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 132 | + if (eth->soc->has_sram) |
developer | 3c9c74d | 2023-09-11 11:36:12 +0800 | [diff] [blame] | 133 | eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; |
| 134 | - } |
| 135 | |
| 136 | mtk_get_hwver(eth); |
| 137 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 138 | @@ -5593,20 +5593,25 @@ static int mtk_probe(struct platform_device *pdev) |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | - for (i = 0;; i++) { |
| 143 | - struct device_node *np = of_parse_phandle(pdev->dev.of_node, |
| 144 | - "mediatek,wed", i); |
| 145 | - static const u32 wdma_regs[] = { |
| 146 | - MTK_WDMA0_BASE, |
| 147 | - MTK_WDMA1_BASE |
| 148 | - }; |
| 149 | - void __iomem *wdma; |
| 150 | + if (eth->soc->offload_version) { |
| 151 | + for (i = 0;; i++) { |
| 152 | + struct device_node *np; |
| 153 | + phys_addr_t wdma_phy; |
| 154 | + u32 wdma_base; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 155 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 156 | - if (!np || i >= ARRAY_SIZE(wdma_regs)) |
| 157 | - break; |
| 158 | + if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) |
| 159 | + break; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 160 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 161 | - wdma = eth->base + wdma_regs[i]; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 162 | - mtk_wed_add_hw(np, eth, wdma, i); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 163 | + np = of_parse_phandle(pdev->dev.of_node, |
| 164 | + "mediatek,wed", i); |
| 165 | + if (!np) |
| 166 | + break; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 167 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 168 | + wdma_base = eth->soc->reg_map->wdma_base[i]; |
| 169 | + wdma_phy = res ? res->start + wdma_base : 0; |
| 170 | + mtk_wed_add_hw(np, eth, eth->base + wdma_base, |
| 171 | + wdma_phy, i); |
| 172 | + } |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 173 | } |
| 174 | |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 175 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_PDMA_INT)) { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 176 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 177 | index a00583f..9099dea 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 178 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 179 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 180 | @@ -620,9 +620,6 @@ |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 181 | #define RX_DMA_SPORT_MASK 0x7 |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 182 | #define RX_DMA_SPORT_MASK_V2 0xf |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 183 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 184 | -#define MTK_WDMA0_BASE 0x2800 |
| 185 | -#define MTK_WDMA1_BASE 0x2c00 |
| 186 | - |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 187 | /* QDMA descriptor txd4 */ |
| 188 | #define TX_DMA_CHKSUM (0x7 << 29) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 189 | #define TX_DMA_TSO BIT(28) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 190 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 191 | index affa704..02e06a8 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 192 | --- a/drivers/net/ethernet/mediatek/mtk_wed.c |
| 193 | +++ b/drivers/net/ethernet/mediatek/mtk_wed.c |
| 194 | @@ -18,15 +18,6 @@ |
| 195 | #include "mtk_wed.h" |
| 196 | #include "mtk_ppe.h" |
| 197 | |
| 198 | -#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) |
| 199 | - |
| 200 | -#define MTK_WED_PKT_SIZE 1900 |
| 201 | -#define MTK_WED_BUF_SIZE 2048 |
| 202 | -#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) |
| 203 | - |
| 204 | -#define MTK_WED_TX_RING_SIZE 2048 |
| 205 | -#define MTK_WED_WDMA_RING_SIZE 1024 |
| 206 | - |
| 207 | static struct mtk_wed_hw *hw_list[2]; |
| 208 | static DEFINE_MUTEX(hw_lock); |
| 209 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 210 | @@ -81,11 +72,31 @@ static struct mtk_wed_hw * |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 211 | mtk_wed_assign(struct mtk_wed_device *dev) |
| 212 | { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 213 | struct mtk_wed_hw *hw; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 214 | + int i; |
| 215 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 216 | + if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) { |
| 217 | + hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; |
| 218 | + if (!hw) |
| 219 | + return NULL; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 220 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 221 | + if (!hw->wed_dev) |
| 222 | + goto out; |
| 223 | + |
| 224 | + if (hw->version == 1) |
| 225 | + return NULL; |
| 226 | + |
| 227 | + /* MT7986 WED devices do not have any pcie slot restrictions */ |
| 228 | + } |
| 229 | + /* MT7986 PCIE or AXI */ |
| 230 | + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { |
| 231 | + hw = hw_list[i]; |
| 232 | + if (hw && !hw->wed_dev) |
| 233 | + goto out; |
| 234 | + } |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 235 | |
| 236 | - hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; |
| 237 | - if (!hw || hw->wed_dev) |
| 238 | - return NULL; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 239 | + return NULL; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 240 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 241 | +out: |
| 242 | hw->wed_dev = dev; |
| 243 | return hw; |
| 244 | } |
| 245 | @@ -97,11 +108,16 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 246 | dma_addr_t desc_phys; |
| 247 | void **page_list; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 248 | int token = dev->wlan.token_start; |
| 249 | - int ring_size; |
| 250 | - int n_pages; |
| 251 | - int i, page_idx; |
| 252 | + int ring_size, n_pages, page_idx; |
| 253 | + int i; |
| 254 | + |
| 255 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 256 | + if (dev->hw->version == 1) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 257 | + ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 258 | + else |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 259 | + ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT + |
| 260 | + MTK_WED_WDMA_RING_SIZE * 2; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 261 | |
| 262 | - ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
| 263 | n_pages = ring_size / MTK_WED_BUF_PER_PAGE; |
| 264 | |
| 265 | page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 266 | @@ -151,10 +167,17 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 267 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 268 | desc->buf0 = cpu_to_le32(buf_phys); |
| 269 | desc->buf1 = cpu_to_le32(buf_phys + txd_size); |
| 270 | - ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) | |
| 271 | - FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1, |
| 272 | - MTK_WED_BUF_SIZE - txd_size) | |
| 273 | - MTK_WDMA_DESC_CTRL_LAST_SEG1; |
| 274 | + |
| 275 | + if (dev->hw->version == 1) |
| 276 | + ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) | |
| 277 | + FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1, |
| 278 | + MTK_WED_BUF_SIZE - txd_size) | |
| 279 | + MTK_WDMA_DESC_CTRL_LAST_SEG1; |
| 280 | + else |
| 281 | + ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) | |
| 282 | + FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2, |
| 283 | + MTK_WED_BUF_SIZE - txd_size) | |
| 284 | + MTK_WDMA_DESC_CTRL_LAST_SEG0; |
| 285 | desc->ctrl = cpu_to_le32(ctrl); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 286 | desc->info = 0; |
| 287 | desc++; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 288 | @@ -210,7 +233,7 @@ mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 289 | if (!ring->desc) |
| 290 | return; |
| 291 | |
| 292 | - dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc), |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 293 | + dma_free_coherent(dev->hw->dev, ring->size * ring->desc_size, |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 294 | ring->desc, ring->desc_phys); |
| 295 | } |
| 296 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 297 | @@ -230,6 +253,9 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en) |
| 298 | { |
| 299 | u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 300 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 301 | + if (dev->hw->version == 1) |
| 302 | + mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 303 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 304 | if (!dev->hw->num_flows) |
| 305 | mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 306 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 307 | @@ -237,10 +263,57 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 308 | wed_r32(dev, MTK_WED_EXT_INT_MASK); |
| 309 | } |
| 310 | |
| 311 | +static void |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 312 | +mtk_wed_set_512_support(struct mtk_wed_device *dev, bool enable) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 313 | +{ |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 314 | + if (enable) { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 315 | + wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); |
| 316 | + wed_w32(dev, MTK_WED_TXP_DW1, |
| 317 | + FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103)); |
| 318 | + } else { |
| 319 | + wed_w32(dev, MTK_WED_TXP_DW1, |
| 320 | + FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100)); |
| 321 | + wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); |
| 322 | + } |
| 323 | +} |
| 324 | + |
| 325 | +static void |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 326 | +mtk_wed_dma_disable(struct mtk_wed_device *dev) |
| 327 | +{ |
| 328 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 329 | + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 330 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 331 | + |
| 332 | + wed_clr(dev, MTK_WED_WDMA_GLO_CFG, |
| 333 | + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 334 | + |
| 335 | + wed_clr(dev, MTK_WED_GLO_CFG, |
| 336 | + MTK_WED_GLO_CFG_TX_DMA_EN | |
| 337 | + MTK_WED_GLO_CFG_RX_DMA_EN); |
| 338 | + |
| 339 | + wdma_m32(dev, MTK_WDMA_GLO_CFG, |
| 340 | + MTK_WDMA_GLO_CFG_TX_DMA_EN | |
| 341 | + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | |
| 342 | + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES, 0); |
| 343 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 344 | + if (dev->hw->version == 1) { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 345 | + regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); |
| 346 | + wdma_m32(dev, MTK_WDMA_GLO_CFG, |
| 347 | + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES, 0); |
| 348 | + } else { |
| 349 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 350 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | |
| 351 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 352 | + |
| 353 | + mtk_wed_set_512_support (dev, false) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 354 | + } |
| 355 | +} |
| 356 | + |
| 357 | static void |
| 358 | mtk_wed_stop(struct mtk_wed_device *dev) |
| 359 | { |
| 360 | - regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); |
| 361 | + mtk_wed_dma_disable(dev); |
| 362 | + |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 363 | mtk_wed_set_ext_int(dev, false); |
| 364 | |
| 365 | wed_clr(dev, MTK_WED_CTRL, |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 366 | @@ -248,26 +321,18 @@ mtk_wed_stop(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 367 | MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 368 | MTK_WED_CTRL_WED_TX_BM_EN | |
| 369 | MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 370 | + |
| 371 | wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); |
| 372 | wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); |
| 373 | wdma_w32(dev, MTK_WDMA_INT_MASK, 0); |
| 374 | wdma_w32(dev, MTK_WDMA_INT_GRP2, 0); |
| 375 | wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0); |
| 376 | - |
| 377 | - wed_clr(dev, MTK_WED_GLO_CFG, |
| 378 | - MTK_WED_GLO_CFG_TX_DMA_EN | |
| 379 | - MTK_WED_GLO_CFG_RX_DMA_EN); |
| 380 | - wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 381 | - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 382 | - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 383 | - wed_clr(dev, MTK_WED_WDMA_GLO_CFG, |
| 384 | - MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 385 | } |
| 386 | |
| 387 | static void |
| 388 | mtk_wed_detach(struct mtk_wed_device *dev) |
| 389 | { |
| 390 | - struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node; |
| 391 | + struct device_node *wlan_node; |
| 392 | struct mtk_wed_hw *hw = dev->hw; |
| 393 | |
| 394 | mutex_lock(&hw_lock); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 395 | @@ -282,11 +347,14 @@ mtk_wed_detach(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 396 | mtk_wed_free_buffer(dev); |
| 397 | mtk_wed_free_tx_rings(dev); |
| 398 | |
| 399 | - if (of_dma_is_coherent(wlan_node)) |
| 400 | - regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 401 | - BIT(hw->index), BIT(hw->index)); |
| 402 | + if (dev->wlan.bus_type == MTK_BUS_TYPE_PCIE) { |
| 403 | + wlan_node = dev->wlan.pci_dev->dev.of_node; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 404 | + if (of_dma_is_coherent(wlan_node) && hw->hifsys) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 405 | + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 406 | + BIT(hw->index), BIT(hw->index)); |
| 407 | + } |
| 408 | |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 409 | - if (!hw_list[!hw->index]->wed_dev && |
| 410 | + if ((!hw_list[!hw->index] || !hw_list[!hw->index]->wed_dev) && |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 411 | hw->eth->dma_dev != hw->eth->dev) |
developer | 7cf584b | 2023-12-21 13:04:36 +0800 | [diff] [blame] | 412 | mtk_eth_set_dma_device(hw->eth, hw->eth->dev); |
| 413 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 414 | @@ -297,14 +365,76 @@ mtk_wed_detach(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 415 | mutex_unlock(&hw_lock); |
| 416 | } |
| 417 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 418 | +#define PCIE_BASE_ADDR0 0x11280000 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 419 | +static void |
| 420 | +mtk_wed_bus_init(struct mtk_wed_device *dev) |
| 421 | +{ |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 422 | + switch (dev->wlan.bus_type) { |
| 423 | + case MTK_BUS_TYPE_PCIE: { |
| 424 | + struct device_node *np = dev->hw->eth->dev->of_node; |
| 425 | + struct regmap *regs; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 426 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 427 | + regs = syscon_regmap_lookup_by_phandle(np, |
| 428 | + "mediatek,wed-pcie"); |
| 429 | + if (IS_ERR(regs)) |
| 430 | + break; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 431 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 432 | + regmap_update_bits(regs, 0, BIT(0), BIT(0)); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 433 | + |
| 434 | + wed_w32(dev, MTK_WED_PCIE_INT_CTRL, |
| 435 | + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2)); |
| 436 | + |
| 437 | + /* pcie interrupt control: pola/source selection */ |
| 438 | + wed_set(dev, MTK_WED_PCIE_INT_CTRL, |
| 439 | + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA | |
| 440 | + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1)); |
| 441 | + wed_r32(dev, MTK_WED_PCIE_INT_CTRL); |
| 442 | + |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 443 | + wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180); |
| 444 | + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184); |
| 445 | + |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 446 | + /* pcie interrupt status trigger register */ |
| 447 | + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24)); |
| 448 | + wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER); |
| 449 | + |
| 450 | + /* pola setting */ |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 451 | + wed_set(dev, MTK_WED_PCIE_INT_CTRL, |
| 452 | + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 453 | + break; |
| 454 | + } |
| 455 | + case MTK_BUS_TYPE_AXI: |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 456 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 457 | + MTK_WED_WPDMA_INT_CTRL_SIG_SRC | |
| 458 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0)); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 459 | + break; |
| 460 | + default: |
| 461 | + break; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 462 | + } |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 463 | +} |
| 464 | + |
| 465 | +static void |
| 466 | +mtk_wed_set_wpdma(struct mtk_wed_device *dev) |
| 467 | +{ |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 468 | + if (dev->hw->version == 1) { |
| 469 | + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); |
| 470 | + } else { |
| 471 | + mtk_wed_bus_init(dev); |
| 472 | + |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 473 | + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int); |
| 474 | + wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask); |
| 475 | + wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx); |
| 476 | + wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 477 | + } |
| 478 | +} |
| 479 | + |
| 480 | static void |
| 481 | mtk_wed_hw_init_early(struct mtk_wed_device *dev) |
| 482 | { |
| 483 | u32 mask, set; |
| 484 | - u32 offset; |
| 485 | |
| 486 | mtk_wed_stop(dev); |
| 487 | mtk_wed_reset(dev, MTK_WED_RESET_WED); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 488 | + mtk_wed_set_wpdma(dev); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 489 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 490 | mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE | |
| 491 | MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 492 | @@ -314,14 +444,30 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 493 | MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY; |
| 494 | wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set); |
| 495 | |
| 496 | - wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 497 | + if (dev->hw->version == 1) { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 498 | + u32 offset; |
| 499 | + offset = dev->hw->index ? 0x04000400 : 0; |
| 500 | + wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); |
| 501 | + wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); |
| 502 | |
| 503 | - offset = dev->hw->index ? 0x04000400 : 0; |
| 504 | - wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); |
| 505 | - wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 506 | + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, |
| 507 | + MTK_PCIE_BASE(dev->hw->index)); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 508 | + } else { |
| 509 | + wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy); |
| 510 | + wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT); |
| 511 | + wed_w32(dev, MTK_WED_WDMA_OFFSET0, |
| 512 | + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS, |
| 513 | + MTK_WDMA_INT_STATUS) | |
| 514 | + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG, |
| 515 | + MTK_WDMA_GLO_CFG)); |
| 516 | + |
| 517 | + wed_w32(dev, MTK_WED_WDMA_OFFSET1, |
| 518 | + FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL, |
| 519 | + MTK_WDMA_RING_TX(0)) | |
| 520 | + FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL, |
| 521 | + MTK_WDMA_RING_RX(0))); |
| 522 | + } |
| 523 | |
| 524 | - wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index)); |
| 525 | - wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); |
| 526 | } |
| 527 | |
| 528 | static void |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 529 | @@ -332,46 +478,79 @@ mtk_wed_hw_init(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 530 | |
| 531 | dev->init_done = true; |
| 532 | mtk_wed_set_ext_int(dev, false); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 533 | - wed_w32(dev, MTK_WED_TX_BM_CTRL, |
| 534 | - MTK_WED_TX_BM_CTRL_PAUSE | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 535 | - FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, |
| 536 | - dev->buf_ring.size / 128) | |
| 537 | - FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, |
| 538 | - MTK_WED_TX_RING_SIZE / 256)); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 539 | |
| 540 | wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys); |
| 541 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 542 | - wed_w32(dev, MTK_WED_TX_BM_TKID, |
| 543 | - FIELD_PREP(MTK_WED_TX_BM_TKID_START, |
| 544 | - dev->wlan.token_start) | |
| 545 | - FIELD_PREP(MTK_WED_TX_BM_TKID_END, |
| 546 | - dev->wlan.token_start + dev->wlan.nbuf - 1)); |
| 547 | - |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 548 | wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE); |
| 549 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 550 | - wed_w32(dev, MTK_WED_TX_BM_DYN_THR, |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 551 | - FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 552 | - MTK_WED_TX_BM_DYN_THR_HI); |
| 553 | + if (dev->hw->version == 1) { |
| 554 | + wed_w32(dev, MTK_WED_TX_BM_CTRL, |
| 555 | + MTK_WED_TX_BM_CTRL_PAUSE | |
| 556 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, |
| 557 | + dev->buf_ring.size / 128) | |
| 558 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, |
| 559 | + MTK_WED_TX_RING_SIZE / 256)); |
| 560 | + wed_w32(dev, MTK_WED_TX_BM_TKID, |
| 561 | + FIELD_PREP(MTK_WED_TX_BM_TKID_START, |
| 562 | + dev->wlan.token_start) | |
| 563 | + FIELD_PREP(MTK_WED_TX_BM_TKID_END, |
| 564 | + dev->wlan.token_start + |
| 565 | + dev->wlan.nbuf - 1)); |
| 566 | + wed_w32(dev, MTK_WED_TX_BM_DYN_THR, |
| 567 | + FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) | |
| 568 | + MTK_WED_TX_BM_DYN_THR_HI); |
| 569 | + } else { |
| 570 | + wed_w32(dev, MTK_WED_TX_BM_CTRL, |
| 571 | + MTK_WED_TX_BM_CTRL_PAUSE | |
| 572 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, |
| 573 | + dev->buf_ring.size / 128) | |
| 574 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, |
| 575 | + dev->buf_ring.size / 128)); |
| 576 | + wed_w32(dev, MTK_WED_TX_BM_TKID_V2, |
| 577 | + FIELD_PREP(MTK_WED_TX_BM_TKID_START, |
| 578 | + dev->wlan.token_start) | |
| 579 | + FIELD_PREP(MTK_WED_TX_BM_TKID_END, |
| 580 | + dev->wlan.token_start + |
| 581 | + dev->wlan.nbuf - 1)); |
| 582 | + wed_w32(dev, MTK_WED_TX_BM_DYN_THR, |
| 583 | + FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) | |
| 584 | + MTK_WED_TX_BM_DYN_THR_HI_V2); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 585 | + wed_w32(dev, MTK_WED_TX_TKID_CTRL, |
| 586 | + MTK_WED_TX_TKID_CTRL_PAUSE | |
| 587 | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM, |
| 588 | + dev->buf_ring.size / 128) | |
| 589 | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM, |
| 590 | + dev->buf_ring.size / 128)); |
| 591 | + wed_w32(dev, MTK_WED_TX_TKID_DYN_THR, |
| 592 | + FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) | |
| 593 | + MTK_WED_TX_TKID_DYN_THR_HI); |
| 594 | + } |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 595 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 596 | mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); |
| 597 | |
| 598 | - wed_set(dev, MTK_WED_CTRL, |
| 599 | - MTK_WED_CTRL_WED_TX_BM_EN | |
| 600 | - MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 601 | + if (dev->hw->version == 1) |
| 602 | + wed_set(dev, MTK_WED_CTRL, |
| 603 | + MTK_WED_CTRL_WED_TX_BM_EN | |
| 604 | + MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 605 | + else |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 606 | + wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 607 | |
| 608 | wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | static void |
| 612 | -mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 613 | +mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 614 | { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 615 | + void *head = (void *)ring->desc; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 616 | int i; |
| 617 | |
| 618 | for (i = 0; i < size; i++) { |
| 619 | - desc[i].buf0 = 0; |
| 620 | - desc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); |
| 621 | - desc[i].buf1 = 0; |
| 622 | - desc[i].info = 0; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 623 | + struct mtk_wdma_desc *desc; |
| 624 | + desc = (struct mtk_wdma_desc *)(head + i * ring->desc_size); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 625 | + desc->buf0 = 0; |
| 626 | + desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); |
| 627 | + desc->buf1 = 0; |
| 628 | + desc->info = 0; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 629 | } |
| 630 | } |
| 631 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 632 | @@ -422,12 +601,10 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev) |
| 633 | int i; |
| 634 | |
| 635 | for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) { |
| 636 | - struct mtk_wdma_desc *desc = dev->tx_ring[i].desc; |
| 637 | - |
| 638 | - if (!desc) |
| 639 | + if (!dev->tx_ring[i].desc) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 640 | continue; |
| 641 | |
| 642 | - mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 643 | + mtk_wed_ring_reset(&dev->tx_ring[i], MTK_WED_TX_RING_SIZE); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 644 | } |
| 645 | |
| 646 | if (mtk_wed_poll_busy(dev)) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 647 | @@ -484,16 +661,16 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 648 | |
| 649 | static int |
| 650 | mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, |
| 651 | - int size) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 652 | + int size, u32 desc_size) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 653 | { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 654 | - ring->desc = dma_alloc_coherent(dev->hw->dev, |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 655 | - size * sizeof(*ring->desc), |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 656 | + ring->desc = dma_alloc_coherent(dev->hw->dev, size * desc_size, |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 657 | &ring->desc_phys, GFP_KERNEL); |
| 658 | if (!ring->desc) |
| 659 | return -ENOMEM; |
| 660 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 661 | + ring->desc_size = desc_size; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 662 | ring->size = size; |
| 663 | - mtk_wed_ring_reset(ring->desc, size); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 664 | + mtk_wed_ring_reset(ring, size); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 665 | |
| 666 | return 0; |
| 667 | } |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 668 | @@ -501,9 +678,10 @@ mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, |
| 669 | static int |
| 670 | mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 671 | { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 672 | + u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 673 | struct mtk_wed_ring *wdma = &dev->tx_wdma[idx]; |
| 674 | |
| 675 | - if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE)) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 676 | + if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, desc_size)) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 677 | return -ENOMEM; |
| 678 | |
| 679 | wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 680 | @@ -521,43 +699,63 @@ mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size) |
| 681 | } |
| 682 | |
| 683 | static void |
| 684 | -mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) |
| 685 | +mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 686 | { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 687 | - u32 wdma_mask; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 688 | - u32 val; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 689 | - int i; |
| 690 | - |
| 691 | - for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) |
| 692 | - if (!dev->tx_wdma[i].desc) |
| 693 | - mtk_wed_wdma_ring_setup(dev, i, 16); |
| 694 | - |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 695 | - wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 696 | - |
| 697 | - mtk_wed_hw_init(dev); |
| 698 | + u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 699 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 700 | + /* wed control cr set */ |
| 701 | wed_set(dev, MTK_WED_CTRL, |
| 702 | MTK_WED_CTRL_WDMA_INT_AGENT_EN | |
| 703 | MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 704 | MTK_WED_CTRL_WED_TX_BM_EN | |
| 705 | MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 706 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 707 | - wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 708 | + if (dev->hw->version == 1) { |
| 709 | + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, |
| 710 | + MTK_WED_PCIE_INT_TRIGGER_STATUS); |
| 711 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 712 | - wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, |
| 713 | - MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | |
| 714 | - MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 715 | - |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 716 | - wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 717 | - MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 718 | + wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, |
| 719 | + MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | |
| 720 | + MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); |
| 721 | |
| 722 | + wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); |
| 723 | + } else { |
| 724 | + /* initail tx interrupt trigger */ |
| 725 | + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX, |
| 726 | + MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN | |
| 727 | + MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR | |
| 728 | + MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN | |
| 729 | + MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR | |
| 730 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG, |
| 731 | + dev->wlan.tx_tbit[0]) | |
| 732 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG, |
| 733 | + dev->wlan.tx_tbit[1])); |
| 734 | + |
| 735 | + /* initail txfree interrupt trigger */ |
| 736 | + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE, |
| 737 | + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN | |
| 738 | + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR | |
| 739 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG, |
| 740 | + dev->wlan.txfree_tbit)); |
| 741 | + |
| 742 | + wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask); |
| 743 | + wed_set(dev, MTK_WED_WDMA_INT_CTRL, |
| 744 | + FIELD_PREP(MTK_WED_WDMA_INT_POLL_SRC_SEL,dev->wdma_idx)); |
| 745 | + } |
| 746 | + /* initail wdma interrupt agent */ |
| 747 | wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 748 | - wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 749 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 750 | wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); |
| 751 | wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); |
| 752 | - |
| 753 | wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); |
| 754 | wed_w32(dev, MTK_WED_INT_MASK, irq_mask); |
| 755 | +} |
| 756 | + |
| 757 | +static void |
| 758 | +mtk_wed_dma_enable(struct mtk_wed_device *dev) |
| 759 | +{ |
| 760 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 761 | + MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 762 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 763 | wed_set(dev, MTK_WED_GLO_CFG, |
| 764 | MTK_WED_GLO_CFG_TX_DMA_EN | |
| 765 | @@ -568,16 +766,57 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) |
| 766 | wed_set(dev, MTK_WED_WDMA_GLO_CFG, |
| 767 | MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 768 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 769 | + wdma_set(dev, MTK_WDMA_GLO_CFG, |
| 770 | + MTK_WDMA_GLO_CFG_TX_DMA_EN | |
| 771 | + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | |
| 772 | + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES); |
| 773 | + |
| 774 | + if (dev->hw->version == 1) { |
| 775 | + wdma_set(dev, MTK_WDMA_GLO_CFG, |
| 776 | + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES); |
| 777 | + } else { |
| 778 | + wed_set(dev, MTK_WED_WPDMA_CTRL, |
| 779 | + MTK_WED_WPDMA_CTRL_SDL1_FIXED); |
| 780 | + |
| 781 | + wed_set(dev, MTK_WED_WPDMA_GLO_CFG, |
| 782 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | |
| 783 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); |
| 784 | + |
| 785 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 786 | + MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP | |
| 787 | + MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV); |
| 788 | + } |
| 789 | +} |
| 790 | + |
| 791 | +static void |
| 792 | +mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) |
| 793 | +{ |
| 794 | + u32 wdma_mask; |
| 795 | + int i; |
| 796 | + |
| 797 | + for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) |
| 798 | + if (!dev->tx_wdma[i].desc) |
| 799 | + mtk_wed_wdma_ring_setup(dev, i, 16); |
| 800 | + |
| 801 | + |
| 802 | + mtk_wed_hw_init(dev); |
| 803 | + mtk_wed_configure_irq(dev, irq_mask); |
| 804 | + |
| 805 | mtk_wed_set_ext_int(dev, true); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 806 | - val = dev->wlan.wpdma_phys | |
| 807 | - MTK_PCIE_MIRROR_MAP_EN | |
| 808 | - FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 809 | |
| 810 | - if (dev->hw->index) |
| 811 | - val |= BIT(1); |
| 812 | - val |= BIT(0); |
| 813 | - regmap_write(dev->hw->mirror, dev->hw->index * 4, val); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 814 | + if (dev->hw->version == 1) { |
| 815 | + u32 val; |
| 816 | + |
| 817 | + val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN | |
| 818 | + FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); |
| 819 | |
| 820 | + val |= BIT(0) | (BIT(1) * !!dev->hw->index); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 821 | + regmap_write(dev->hw->mirror, dev->hw->index * 4, val); |
| 822 | + } else { |
| 823 | + mtk_wed_set_512_support(dev, true); |
| 824 | + } |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 825 | + |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 826 | + mtk_wed_dma_enable(dev); |
| 827 | dev->running = true; |
| 828 | } |
| 829 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 830 | @@ -586,20 +825,19 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 831 | __releases(RCU) |
| 832 | { |
| 833 | struct mtk_wed_hw *hw; |
| 834 | + struct device *device; |
| 835 | int ret = 0; |
| 836 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 837 | RCU_LOCKDEP_WARN(!rcu_read_lock_held(), |
| 838 | "mtk_wed_attach without holding the RCU read lock"); |
| 839 | |
| 840 | - if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 || |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 841 | + if ((dev->wlan.bus_type == MTK_WED_BUS_PCIE && |
| 842 | + pci_domain_nr(dev->wlan.pci_dev->bus) > 1) || |
| 843 | !try_module_get(THIS_MODULE)) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 844 | - ret = -ENODEV; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 845 | + return -ENODEV; |
| 846 | |
| 847 | rcu_read_unlock(); |
| 848 | |
| 849 | - if (ret) |
| 850 | - return ret; |
| 851 | - |
| 852 | mutex_lock(&hw_lock); |
| 853 | |
| 854 | hw = mtk_wed_assign(dev); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 855 | @@ -609,8 +847,11 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 856 | goto out; |
| 857 | } |
| 858 | |
| 859 | - dev_info(&dev->wlan.pci_dev->dev, "attaching wed device %d\n", hw->index); |
| 860 | - |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 861 | + device = dev->wlan.bus_type == MTK_WED_BUS_PCIE ? |
| 862 | + &dev->wlan.pci_dev->dev |
| 863 | + : &dev->wlan.platform_dev->dev; |
| 864 | + dev_info(device, "attaching wed device %d version %d\n", |
| 865 | + hw->index, hw->version); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 866 | dev->hw = hw; |
| 867 | dev->dev = hw->dev; |
| 868 | dev->irq = hw->irq; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 869 | @@ -627,7 +868,10 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 870 | } |
| 871 | |
| 872 | mtk_wed_hw_init_early(dev); |
| 873 | - regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0); |
| 874 | + |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 875 | + if (hw->hifsys) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 876 | + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 877 | + BIT(hw->index), 0); |
| 878 | |
| 879 | out: |
| 880 | mutex_unlock(&hw_lock); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 881 | @@ -654,7 +898,8 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 882 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 883 | BUG_ON(idx >= ARRAY_SIZE(dev->tx_ring)); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 884 | |
| 885 | - if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE)) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 886 | + if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE, |
| 887 | + sizeof(*ring->desc))) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 888 | return -ENOMEM; |
| 889 | |
| 890 | if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE)) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 891 | @@ -681,21 +926,21 @@ static int |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 892 | mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs) |
| 893 | { |
| 894 | struct mtk_wed_ring *ring = &dev->txfree_ring; |
| 895 | - int i; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 896 | + int i, index = dev->hw->version == 1; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 897 | |
| 898 | /* |
| 899 | * For txfree event handling, the same DMA ring is shared between WED |
| 900 | * and WLAN. The WLAN driver accesses the ring index registers through |
| 901 | * WED |
| 902 | */ |
| 903 | - ring->reg_base = MTK_WED_RING_RX(1); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 904 | + ring->reg_base = MTK_WED_RING_RX(index); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 905 | ring->wpdma = regs; |
| 906 | |
| 907 | for (i = 0; i < 12; i += 4) { |
| 908 | u32 val = readl(regs + i); |
| 909 | |
| 910 | - wed_w32(dev, MTK_WED_RING_RX(1) + i, val); |
| 911 | - wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 912 | + wed_w32(dev, MTK_WED_RING_RX(index) + i, val); |
| 913 | + wed_w32(dev, MTK_WED_WPDMA_RING_RX(index) + i, val); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | return 0; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 917 | @@ -783,7 +1028,9 @@ void mtk_wed_flow_remove(int index) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 918 | } |
| 919 | |
| 920 | void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 921 | - void __iomem *wdma, int index) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 922 | + void __iomem *wdma, phys_addr_t wdma_phy, |
| 923 | + int index) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 924 | + |
| 925 | { |
| 926 | static const struct mtk_wed_ops wed_ops = { |
| 927 | .attach = mtk_wed_attach, |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 928 | @@ -809,16 +1056,16 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 929 | |
| 930 | pdev = of_find_device_by_node(np); |
| 931 | if (!pdev) |
| 932 | - return; |
| 933 | + goto err_of_node_put; |
| 934 | |
| 935 | get_device(&pdev->dev); |
| 936 | irq = platform_get_irq(pdev, 0); |
| 937 | if (irq < 0) |
| 938 | - return; |
| 939 | + goto err_put_device; |
| 940 | |
| 941 | regs = syscon_regmap_lookup_by_phandle(np, NULL); |
| 942 | if (IS_ERR(regs)) |
| 943 | - return; |
| 944 | + goto err_put_device; |
| 945 | |
| 946 | rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops); |
| 947 | |
| 948 | @@ -835,27 +1082,42 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 949 | hw->eth = eth; |
| 950 | hw->dev = &pdev->dev; |
| 951 | hw->wdma = wdma; |
| 952 | + hw->wdma_phy = wdma_phy; |
| 953 | hw->index = index; |
| 954 | hw->irq = irq; |
| 955 | - hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, |
| 956 | - "mediatek,pcie-mirror"); |
| 957 | - hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, |
| 958 | - "mediatek,hifsys"); |
| 959 | - if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { |
| 960 | - kfree(hw); |
| 961 | - goto unlock; |
| 962 | - } |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 963 | + hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; |
| 964 | + |
| 965 | + if (hw->version == 1) { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 966 | + hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, |
| 967 | + "mediatek,pcie-mirror"); |
| 968 | + hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, |
| 969 | + "mediatek,hifsys"); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 970 | |
| 971 | - if (!index) { |
| 972 | - regmap_write(hw->mirror, 0, 0); |
| 973 | - regmap_write(hw->mirror, 4, 0); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 974 | + if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { |
| 975 | + kfree(hw); |
| 976 | + goto unlock; |
| 977 | + } |
| 978 | + |
| 979 | + if (!index) { |
| 980 | + regmap_write(hw->mirror, 0, 0); |
| 981 | + regmap_write(hw->mirror, 4, 0); |
| 982 | + } |
| 983 | } |
| 984 | + |
| 985 | mtk_wed_hw_add_debugfs(hw); |
| 986 | |
| 987 | hw_list[index] = hw; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 988 | |
| 989 | + mutex_unlock(&hw_lock); |
| 990 | + |
| 991 | + return; |
| 992 | + |
| 993 | unlock: |
| 994 | mutex_unlock(&hw_lock); |
| 995 | +err_put_device: |
| 996 | + put_device(&pdev->dev); |
| 997 | +err_of_node_put: |
| 998 | + of_node_put(np); |
| 999 | } |
| 1000 | |
| 1001 | void mtk_wed_exit(void) |
| 1002 | @@ -876,6 +1138,7 @@ void mtk_wed_exit(void) |
| 1003 | hw_list[i] = NULL; |
| 1004 | debugfs_remove(hw->debugfs_dir); |
| 1005 | put_device(hw->dev); |
| 1006 | + of_node_put(hw->node); |
| 1007 | kfree(hw); |
| 1008 | } |
| 1009 | } |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1010 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1011 | index 981ec61..c9a20e4 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1012 | --- a/drivers/net/ethernet/mediatek/mtk_wed.h |
| 1013 | +++ b/drivers/net/ethernet/mediatek/mtk_wed.h |
| 1014 | @@ -8,6 +8,19 @@ |
| 1015 | #include <linux/debugfs.h> |
| 1016 | #include <linux/regmap.h> |
| 1017 | #include <linux/netdevice.h> |
| 1018 | +#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) |
| 1019 | + |
| 1020 | +#define MTK_WED_PKT_SIZE 1900 |
| 1021 | +#define MTK_WED_BUF_SIZE 2048 |
| 1022 | +#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) |
| 1023 | + |
| 1024 | +#define MTK_WED_TX_RING_SIZE 2048 |
| 1025 | +#define MTK_WED_WDMA_RING_SIZE 512 |
| 1026 | +#define MTK_WED_MAX_GROUP_SIZE 0x100 |
| 1027 | +#define MTK_WED_VLD_GROUP_SIZE 0x40 |
| 1028 | +#define MTK_WED_PER_GROUP_PKT 128 |
| 1029 | + |
| 1030 | +#define MTK_WED_FBUF_SIZE 128 |
| 1031 | |
| 1032 | struct mtk_eth; |
| 1033 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1034 | @@ -18,11 +31,13 @@ struct mtk_wed_hw { |
| 1035 | struct regmap *hifsys; |
| 1036 | struct device *dev; |
| 1037 | void __iomem *wdma; |
| 1038 | + phys_addr_t wdma_phy; |
| 1039 | struct regmap *mirror; |
| 1040 | struct dentry *debugfs_dir; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1041 | struct mtk_wed_device *wed_dev; |
| 1042 | u32 debugfs_reg; |
| 1043 | u32 num_flows; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1044 | + u8 version; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1045 | char dirname[5]; |
| 1046 | int irq; |
| 1047 | int index; |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1048 | @@ -101,14 +116,16 @@ wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1049 | } |
| 1050 | |
| 1051 | void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 1052 | - void __iomem *wdma, int index); |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1053 | + void __iomem *wdma, phys_addr_t wdma_phy, |
| 1054 | + int index); |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1055 | void mtk_wed_exit(void); |
| 1056 | int mtk_wed_flow_add(int index); |
| 1057 | void mtk_wed_flow_remove(int index); |
| 1058 | #else |
| 1059 | static inline void |
| 1060 | mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 1061 | - void __iomem *wdma, int index) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1062 | + void __iomem *wdma, phys_addr_t wdma_phy, |
| 1063 | + int index) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1064 | { |
| 1065 | } |
| 1066 | static inline void |
| 1067 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
developer | 740bee8 | 2023-10-16 10:58:43 +0800 | [diff] [blame] | 1068 | index a81d3fd..f420f18 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1069 | --- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
| 1070 | +++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
| 1071 | @@ -116,6 +116,9 @@ wed_txinfo_show(struct seq_file *s, void *data) |
| 1072 | DUMP_WDMA(WDMA_GLO_CFG), |
| 1073 | DUMP_WDMA_RING(WDMA_RING_RX(0)), |
| 1074 | DUMP_WDMA_RING(WDMA_RING_RX(1)), |
| 1075 | + |
| 1076 | + DUMP_STR("TX FREE"), |
| 1077 | + DUMP_WED(WED_RX_MIB(0)), |
| 1078 | }; |
| 1079 | struct mtk_wed_hw *hw = s->private; |
| 1080 | struct mtk_wed_device *dev = hw->wed_dev; |
| 1081 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1082 | index 0a0465e..e66acda 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1083 | --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
| 1084 | +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1085 | @@ -5,6 +5,7 @@ |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1086 | #define __MTK_WED_REGS_H |
| 1087 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1088 | #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1089 | +#define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1090 | #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) |
| 1091 | #define MTK_WDMA_DESC_CTRL_BURST BIT(16) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1092 | #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1093 | @@ -18,6 +19,14 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1094 | __le32 info; |
| 1095 | } __packed __aligned(4); |
| 1096 | |
| 1097 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1098 | +#define MTK_WED_REV_ID 0x004 |
| 1099 | +#define MTK_WED_REV_ID_MAJOR GENMASK(31, 28) |
| 1100 | +#else |
| 1101 | +#define MTK_WED_REV_ID 0x000 |
| 1102 | +#define MTK_WED_REV_ID_MAJOR GENMASK(7, 0) |
| 1103 | +#endif |
| 1104 | + |
| 1105 | #define MTK_WED_RESET 0x008 |
| 1106 | #define MTK_WED_RESET_TX_BM BIT(0) |
| 1107 | #define MTK_WED_RESET_TX_FREE_AGENT BIT(4) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1108 | @@ -41,6 +50,7 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1109 | #define MTK_WED_CTRL_RESERVE_EN BIT(12) |
| 1110 | #define MTK_WED_CTRL_RESERVE_BUSY BIT(13) |
| 1111 | #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24) |
| 1112 | +#define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25) |
| 1113 | #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28) |
| 1114 | |
| 1115 | #define MTK_WED_EXT_INT_STATUS 0x020 |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1116 | @@ -49,6 +59,10 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1117 | #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4) |
| 1118 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8) |
| 1119 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9) |
| 1120 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1121 | +#define MTK_WED_EXT_INT_STATUS_TX_TKID_LO_TH BIT(10) |
| 1122 | +#define MTK_WED_EXT_INT_STATUS_TX_TKID_HI_TH BIT(11) |
| 1123 | +#endif |
| 1124 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12) |
| 1125 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13) |
| 1126 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1127 | @@ -57,16 +71,23 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1128 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19) |
| 1129 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20) |
| 1130 | #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21) |
| 1131 | -#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR BIT(22) |
| 1132 | +#define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22) |
| 1133 | +#define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23) |
| 1134 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24) |
| 1135 | +#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25) |
| 1136 | +#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26) |
| 1137 | +#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27) |
| 1138 | + |
| 1139 | #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \ |
| 1140 | MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \ |
| 1141 | MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \ |
| 1142 | + MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH | \ |
| 1143 | + MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH | \ |
| 1144 | MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \ |
| 1145 | MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \ |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1146 | MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \ |
| 1147 | - MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \ |
| 1148 | - MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR) |
| 1149 | + MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR | \ |
| 1150 | + MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR) |
| 1151 | |
| 1152 | #define MTK_WED_EXT_INT_MASK 0x028 |
| 1153 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1154 | @@ -81,6 +102,7 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1155 | #define MTK_WED_TX_BM_BASE 0x084 |
| 1156 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1157 | #define MTK_WED_TX_BM_TKID 0x088 |
| 1158 | +#define MTK_WED_TX_BM_TKID_V2 0x0c8 |
| 1159 | #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
| 1160 | #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1161 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1162 | @@ -94,7 +116,25 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1163 | |
| 1164 | #define MTK_WED_TX_BM_DYN_THR 0x0a0 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1165 | #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1166 | +#define MTK_WED_TX_BM_DYN_THR_LO_V2 GENMASK(8, 0) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1167 | #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1168 | +#define MTK_WED_TX_BM_DYN_THR_HI_V2 GENMASK(24, 16) |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1169 | + |
| 1170 | +#define MTK_WED_TX_TKID_CTRL 0x0c0 |
| 1171 | +#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0) |
| 1172 | +#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16) |
| 1173 | +#define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28) |
| 1174 | + |
| 1175 | +#define MTK_WED_TX_TKID_DYN_THR 0x0e0 |
| 1176 | +#define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0) |
| 1177 | +#define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16) |
| 1178 | + |
| 1179 | +#define MTK_WED_TXP_DW0 0x120 |
| 1180 | +#define MTK_WED_TXP_DW1 0x124 |
| 1181 | +#define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16) |
| 1182 | +#define MTK_WED_TXDP_CTRL 0x130 |
| 1183 | +#define MTK_WED_TXDP_DW9_OVERWR BIT(9) |
| 1184 | +#define MTK_WED_RX_BM_TKID_MIB 0x1cc |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1185 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1186 | #define MTK_WED_INT_STATUS 0x200 |
| 1187 | #define MTK_WED_INT_MASK 0x204 |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1188 | @@ -125,6 +165,7 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1189 | #define MTK_WED_RESET_IDX_RX GENMASK(17, 16) |
| 1190 | |
| 1191 | #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4) |
| 1192 | +#define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4) |
| 1193 | |
| 1194 | #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10) |
| 1195 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1196 | @@ -139,6 +180,19 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1197 | #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1) |
| 1198 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2) |
| 1199 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3) |
| 1200 | +/* CONFIG_MEDIATEK_NETSYS_V2 */ |
| 1201 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4) |
| 1202 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5) |
| 1203 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6) |
| 1204 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7) |
| 1205 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16) |
| 1206 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19) |
| 1207 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20) |
| 1208 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21) |
| 1209 | +#define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24) |
| 1210 | +#define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28) |
| 1211 | + |
| 1212 | +/* CONFIG_MEDIATEK_NETSYS_V1 */ |
| 1213 | #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) |
| 1214 | #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6) |
| 1215 | #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1216 | @@ -152,24 +206,54 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1217 | #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) |
| 1218 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27) |
| 1219 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) |
| 1220 | + |
| 1221 | #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29) |
| 1222 | +#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30) |
| 1223 | #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) |
| 1224 | |
| 1225 | #define MTK_WED_WPDMA_RESET_IDX 0x50c |
| 1226 | #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0) |
| 1227 | #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1228 | |
| 1229 | +#define MTK_WED_WPDMA_CTRL 0x518 |
| 1230 | +#define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31) |
| 1231 | + |
| 1232 | #define MTK_WED_WPDMA_INT_CTRL 0x520 |
| 1233 | #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21) |
| 1234 | +#define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22) |
| 1235 | +#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16) |
| 1236 | |
| 1237 | #define MTK_WED_WPDMA_INT_MASK 0x524 |
| 1238 | |
| 1239 | -#define MTK_WED_PCIE_CFG_BASE 0x560 |
| 1240 | +#define MTK_WED_WPDMA_INT_CTRL_TX 0x530 |
| 1241 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0) |
| 1242 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1) |
| 1243 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG GENMASK(6, 2) |
| 1244 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8) |
| 1245 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9) |
| 1246 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10) |
| 1247 | + |
| 1248 | +#define MTK_WED_WPDMA_INT_CTRL_RX 0x534 |
| 1249 | + |
| 1250 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538 |
| 1251 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0) |
| 1252 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1) |
| 1253 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG GENMASK(6, 2) |
| 1254 | |
| 1255 | +#define MTK_WED_PCIE_CFG_BASE 0x560 |
| 1256 | +#define MTK_WED_PCIE_CFG_INTM 0x564 |
| 1257 | +#define MTK_WED_PCIE_CFG_MSIS 0x568 |
| 1258 | #define MTK_WED_PCIE_INT_TRIGGER 0x570 |
| 1259 | #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16) |
| 1260 | |
| 1261 | +#define MTK_WED_PCIE_INT_CTRL 0x57c |
| 1262 | +#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20) |
| 1263 | +#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16) |
| 1264 | +#define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12) |
| 1265 | #define MTK_WED_WPDMA_CFG_BASE 0x580 |
| 1266 | +#define MTK_WED_WPDMA_CFG_INT_MASK 0x584 |
| 1267 | +#define MTK_WED_WPDMA_CFG_TX 0x588 |
| 1268 | +#define MTK_WED_WPDMA_CFG_TX_FREE 0x58c |
| 1269 | |
| 1270 | #define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4) |
| 1271 | #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1272 | @@ -203,14 +287,22 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1273 | #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1274 | #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24) |
| 1275 | |
| 1276 | +#define MTK_WED_WDMA_INT_CLR 0xa24 |
| 1277 | +#define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16) |
| 1278 | + |
| 1279 | #define MTK_WED_WDMA_INT_TRIGGER 0xa28 |
| 1280 | #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16) |
| 1281 | |
| 1282 | #define MTK_WED_WDMA_INT_CTRL 0xa2c |
| 1283 | -#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16) |
| 1284 | +#define MTK_WED_WDMA_INT_POLL_SRC_SEL GENMASK(17, 16) |
| 1285 | |
| 1286 | +#define MTK_WED_WDMA_CFG_BASE 0xaa0 |
| 1287 | #define MTK_WED_WDMA_OFFSET0 0xaa4 |
| 1288 | #define MTK_WED_WDMA_OFFSET1 0xaa8 |
| 1289 | +#define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0) |
| 1290 | +#define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16) |
| 1291 | +#define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0) |
| 1292 | +#define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16) |
| 1293 | |
| 1294 | #define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4) |
| 1295 | #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4) |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1296 | @@ -221,14 +313,21 @@ struct mtk_wdma_desc { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1297 | #define MTK_WED_RING_OFS_CPU_IDX 0x08 |
| 1298 | #define MTK_WED_RING_OFS_DMA_IDX 0x0c |
| 1299 | |
| 1300 | +#define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10) |
| 1301 | #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10) |
| 1302 | |
| 1303 | #define MTK_WDMA_GLO_CFG 0x204 |
| 1304 | -#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26) |
| 1305 | +#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0) |
| 1306 | +#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2) |
| 1307 | +#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26) |
| 1308 | +#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27) |
| 1309 | +#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28) |
| 1310 | + |
| 1311 | |
| 1312 | #define MTK_WDMA_RESET_IDX 0x208 |
| 1313 | #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0) |
| 1314 | #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1315 | +#define MTK_WDMA_INT_STATUS 0x220 |
| 1316 | |
| 1317 | #define MTK_WDMA_INT_MASK 0x228 |
| 1318 | #define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0) |
| 1319 | diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1320 | index 7e00cca..4db70b0 100644 |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1321 | --- a/include/linux/soc/mediatek/mtk_wed.h |
| 1322 | +++ b/include/linux/soc/mediatek/mtk_wed.h |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1323 | @@ -8,12 +8,19 @@ |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1324 | |
| 1325 | #define MTK_WED_TX_QUEUES 2 |
| 1326 | |
| 1327 | +enum { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1328 | + MTK_BUS_TYPE_PCIE, |
| 1329 | + MTK_BUS_TYPE_AXI, |
| 1330 | + MTK_BUS_TYPE_MAX |
| 1331 | +}; |
| 1332 | + |
| 1333 | struct mtk_wed_hw; |
| 1334 | struct mtk_wdma_desc; |
| 1335 | |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1336 | struct mtk_wed_ring { |
| 1337 | struct mtk_wdma_desc *desc; |
| 1338 | dma_addr_t desc_phys; |
| 1339 | + u32 desc_size; |
| 1340 | int size; |
| 1341 | |
| 1342 | u32 reg_base; |
| 1343 | @@ -42,9 +49,21 @@ struct mtk_wed_device { |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1344 | |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1345 | /* filled by driver: */ |
| 1346 | struct { |
developer | 69bcd59 | 2024-03-25 14:26:39 +0800 | [diff] [blame^] | 1347 | - struct pci_dev *pci_dev; |
| 1348 | + union { |
| 1349 | + struct platform_device *platform_dev; |
| 1350 | + struct pci_dev *pci_dev; |
| 1351 | + }; |
| 1352 | + enum mtk_wed_bus_tye bus_type; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1353 | + void __iomem *base; |
developer | 29f66b3 | 2022-07-12 15:23:20 +0800 | [diff] [blame] | 1354 | |
| 1355 | u32 wpdma_phys; |
| 1356 | + u32 wpdma_int; |
developer | 3262bf8 | 2022-07-12 11:37:54 +0800 | [diff] [blame] | 1357 | + u32 wpdma_mask; |
| 1358 | + u32 wpdma_tx; |
| 1359 | + u32 wpdma_txfree; |
| 1360 | + |
| 1361 | + u8 tx_tbit[MTK_WED_TX_QUEUES]; |
| 1362 | + u8 txfree_tbit; |
| 1363 | |
| 1364 | u16 token_start; |
| 1365 | unsigned int nbuf; |
| 1366 | -- |
| 1367 | 2.18.0 |
| 1368 | |