developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 8 | #include <dt-bindings/gpio/gpio.h> |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 9 | #include "mt7988.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "MediaTek MT7988A DSA 10G SPIM-NOR RFB"; |
| 13 | compatible = "mediatek,mt7988a-dsa-10g-spim-nor", |
| 14 | /* Reserve this for DVFS if creating new dts */ |
| 15 | "mediatek,mt7988"; |
| 16 | |
| 17 | chosen { |
| 18 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 19 | earlycon=uart8250,mmio32,0x11000000 \ |
| 20 | pci=pcie_bus_perf"; |
| 21 | }; |
| 22 | |
| 23 | memory { |
| 24 | reg = <0 0x40000000 0 0x10000000>; |
| 25 | }; |
| 26 | |
| 27 | wsys_adie: wsys_adie@0 { |
| 28 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 29 | compatible = "mediatek,rebb-mt7988-adie"; |
| 30 | adie_id = <7976>; |
| 31 | sku_type = <3000>; |
| 32 | }; |
| 33 | }; |
| 34 | |
| 35 | &fan { |
developer | fce0d15 | 2024-01-11 13:37:13 +0800 | [diff] [blame] | 36 | pwms = <&pwm 0 50000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 37 | status = "okay"; |
| 38 | }; |
| 39 | |
| 40 | &pwm { |
| 41 | status = "okay"; |
| 42 | }; |
| 43 | |
| 44 | &uart0 { |
| 45 | status = "okay"; |
| 46 | }; |
| 47 | |
developer | 64376db | 2024-04-08 14:04:38 +0800 | [diff] [blame^] | 48 | &i2c0 { |
| 49 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&i2c0_pins>; |
| 51 | status = "okay"; |
| 52 | |
| 53 | rt5190a_64: rt5190a@64 { |
| 54 | compatible = "richtek,rt5190a"; |
| 55 | reg = <0x64>; |
| 56 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 57 | vin2-supply = <&rt5190_buck1>; |
| 58 | vin3-supply = <&rt5190_buck1>; |
| 59 | vin4-supply = <&rt5190_buck1>; |
| 60 | |
| 61 | regulators { |
| 62 | rt5190_buck1: buck1 { |
| 63 | regulator-name = "rt5190a-buck1"; |
| 64 | regulator-min-microvolt = <5090000>; |
| 65 | regulator-max-microvolt = <5090000>; |
| 66 | regulator-allowed-modes = |
| 67 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 68 | regulator-boot-on; |
| 69 | }; |
| 70 | buck2 { |
| 71 | regulator-name = "vcore"; |
| 72 | regulator-min-microvolt = <600000>; |
| 73 | regulator-max-microvolt = <1400000>; |
| 74 | regulator-boot-on; |
| 75 | }; |
| 76 | buck3 { |
| 77 | regulator-name = "proc"; |
| 78 | regulator-min-microvolt = <600000>; |
| 79 | regulator-max-microvolt = <1400000>; |
| 80 | regulator-boot-on; |
| 81 | }; |
| 82 | buck4 { |
| 83 | regulator-name = "rt5190a-buck4"; |
| 84 | regulator-min-microvolt = <850000>; |
| 85 | regulator-max-microvolt = <850000>; |
| 86 | regulator-allowed-modes = |
| 87 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 88 | regulator-boot-on; |
| 89 | }; |
| 90 | ldo { |
| 91 | regulator-name = "rt5190a-ldo"; |
| 92 | regulator-min-microvolt = <1200000>; |
| 93 | regulator-max-microvolt = <1200000>; |
| 94 | regulator-boot-on; |
| 95 | }; |
| 96 | }; |
| 97 | }; |
| 98 | }; |
| 99 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 100 | &spi1 { |
| 101 | pinctrl-names = "default"; |
| 102 | /* pin shared with snfi */ |
| 103 | pinctrl-0 = <&spic_pins>; |
| 104 | status = "disabled"; |
| 105 | }; |
| 106 | |
| 107 | &spi2 { |
| 108 | pinctrl-names = "default"; |
| 109 | pinctrl-0 = <&spi2_flash_pins>; |
| 110 | status = "okay"; |
| 111 | spi_nor@0 { |
| 112 | #address-cells = <1>; |
| 113 | #size-cells = <1>; |
| 114 | compatible = "jedec,spi-nor"; |
| 115 | spi-cal-enable; |
| 116 | spi-cal-mode = "read-data"; |
| 117 | spi-cal-datalen = <7>; |
| 118 | spi-cal-data = /bits/ 8 < |
| 119 | 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ |
| 120 | spi-cal-addrlen = <1>; |
| 121 | spi-cal-addr = /bits/ 32 <0x0>; |
| 122 | reg = <0>; |
| 123 | spi-max-frequency = <52000000>; |
developer | 0508550 | 2023-04-06 13:04:13 +0800 | [diff] [blame] | 124 | spi-tx-bus-width = <4>; |
| 125 | spi-rx-bus-width = <4>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 126 | |
| 127 | partition@00000 { |
| 128 | label = "BL2"; |
| 129 | reg = <0x00000 0x0040000>; |
| 130 | }; |
| 131 | partition@40000 { |
| 132 | label = "u-boot-env"; |
| 133 | reg = <0x40000 0x0010000>; |
| 134 | }; |
| 135 | factory: partition@50000 { |
| 136 | label = "Factory"; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 137 | reg = <0x50000 0x0200000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 138 | }; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 139 | partition@250000 { |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 140 | label = "FIP"; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 141 | reg = <0x250000 0x0080000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 142 | }; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 143 | partition@2D0000 { |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 144 | label = "firmware"; |
developer | 993c84b | 2023-02-15 16:03:22 +0800 | [diff] [blame] | 145 | reg = <0x2D0000 0x1D30000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 146 | }; |
| 147 | }; |
| 148 | }; |
| 149 | |
| 150 | &pcie0 { |
| 151 | pinctrl-names = "default"; |
| 152 | pinctrl-0 = <&pcie0_pins>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 153 | wifi-reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; |
| 154 | wifi-reset-msleep = <100>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 155 | status = "okay"; |
| 156 | }; |
| 157 | |
| 158 | &pcie1 { |
| 159 | pinctrl-names = "default"; |
| 160 | pinctrl-0 = <&pcie1_pins>; |
| 161 | status = "okay"; |
| 162 | }; |
| 163 | |
| 164 | &pcie2 { |
| 165 | pinctrl-names = "default"; |
| 166 | pinctrl-0 = <&pcie2_pins>; |
| 167 | status = "disabled"; |
| 168 | }; |
| 169 | |
| 170 | &pcie3 { |
| 171 | pinctrl-names = "default"; |
| 172 | pinctrl-0 = <&pcie3_pins>; |
| 173 | status = "okay"; |
| 174 | }; |
| 175 | |
| 176 | &pio { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 177 | mdio0_pins: mdio0-pins { |
| 178 | mux { |
| 179 | function = "mdio"; |
| 180 | groups = "mdc_mdio0"; |
| 181 | }; |
| 182 | |
| 183 | conf { |
| 184 | groups = "mdc_mdio0"; |
developer | edbe69e | 2023-06-08 11:08:46 +0800 | [diff] [blame] | 185 | drive-strength = <MTK_DRIVE_10mA>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 186 | }; |
| 187 | }; |
| 188 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 189 | gbe0_led0_pins: gbe0-pins { |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 190 | mux { |
| 191 | function = "led"; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 192 | groups = "gbe0_led0"; |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 193 | }; |
| 194 | }; |
| 195 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 196 | gbe1_led0_pins: gbe1-pins { |
| 197 | mux { |
| 198 | function = "led"; |
| 199 | groups = "gbe1_led0"; |
| 200 | }; |
| 201 | }; |
| 202 | |
| 203 | gbe2_led0_pins: gbe2-pins { |
| 204 | mux { |
| 205 | function = "led"; |
| 206 | groups = "gbe2_led0"; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | gbe3_led0_pins: gbe3-pins { |
| 211 | mux { |
| 212 | function = "led"; |
| 213 | groups = "gbe3_led0"; |
| 214 | }; |
| 215 | }; |
| 216 | |
developer | 64376db | 2024-04-08 14:04:38 +0800 | [diff] [blame^] | 217 | i2c0_pins: i2c0-pins-g0 { |
| 218 | mux { |
| 219 | function = "i2c"; |
| 220 | groups = "i2c0_1"; |
| 221 | }; |
| 222 | }; |
| 223 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 224 | pcie0_pins: pcie0-pins { |
| 225 | mux { |
| 226 | function = "pcie"; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 227 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 228 | }; |
| 229 | }; |
| 230 | |
| 231 | pcie1_pins: pcie1-pins { |
| 232 | mux { |
| 233 | function = "pcie"; |
| 234 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 235 | "pcie_wake_n1_0"; |
| 236 | }; |
| 237 | }; |
| 238 | |
| 239 | pcie2_pins: pcie2-pins { |
| 240 | mux { |
| 241 | function = "pcie"; |
| 242 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 243 | "pcie_wake_n2_0"; |
| 244 | }; |
| 245 | }; |
| 246 | |
| 247 | pcie3_pins: pcie3-pins { |
| 248 | mux { |
| 249 | function = "pcie"; |
| 250 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 251 | "pcie_wake_n3_0"; |
| 252 | }; |
| 253 | }; |
| 254 | |
| 255 | spic_pins: spi1-pins { |
| 256 | mux { |
| 257 | function = "spi"; |
developer | d516958 | 2023-02-17 10:32:38 +0800 | [diff] [blame] | 258 | groups = "spi1"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 259 | }; |
| 260 | }; |
| 261 | |
| 262 | spi2_flash_pins: spi2-pins { |
| 263 | mux { |
| 264 | function = "spi"; |
| 265 | groups = "spi2", "spi2_wp_hold"; |
| 266 | }; |
| 267 | }; |
| 268 | }; |
| 269 | |
| 270 | &watchdog { |
| 271 | status = "disabled"; |
| 272 | }; |
| 273 | |
| 274 | ð { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 275 | pinctrl-names = "default"; |
| 276 | pinctrl-0 = <&mdio0_pins>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 277 | status = "okay"; |
| 278 | |
| 279 | gmac0: mac@0 { |
| 280 | compatible = "mediatek,eth-mac"; |
| 281 | reg = <0>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 282 | mac-type = "xgdm"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 283 | phy-mode = "10gbase-kr"; |
| 284 | |
| 285 | fixed-link { |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 286 | speed = <10000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 287 | full-duplex; |
| 288 | pause; |
| 289 | }; |
| 290 | }; |
| 291 | |
| 292 | gmac1: mac@1 { |
| 293 | compatible = "mediatek,eth-mac"; |
| 294 | reg = <1>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 295 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 296 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 297 | phy-handle = <&phy0>; |
| 298 | }; |
| 299 | |
| 300 | gmac2: mac@2 { |
| 301 | compatible = "mediatek,eth-mac"; |
| 302 | reg = <2>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 303 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 304 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 305 | phy-handle = <&phy1>; |
| 306 | }; |
| 307 | |
| 308 | mdio: mdio-bus { |
| 309 | #address-cells = <1>; |
| 310 | #size-cells = <0>; |
developer | 9faf1ef | 2023-03-21 16:49:51 +0800 | [diff] [blame] | 311 | clock-frequency = <10500000>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 312 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 313 | phy0: ethernet-phy@0 { |
| 314 | reg = <0>; |
| 315 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 316 | reset-gpios = <&pio 72 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 317 | reset-assert-us = <100000>; |
| 318 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 319 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 320 | }; |
| 321 | |
| 322 | phy1: ethernet-phy@8 { |
| 323 | reg = <8>; |
| 324 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 325 | reset-gpios = <&pio 71 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 326 | reset-assert-us = <100000>; |
| 327 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 328 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 329 | }; |
| 330 | |
| 331 | switch@0 { |
| 332 | compatible = "mediatek,mt7988"; |
| 333 | reg = <31>; |
| 334 | ports { |
| 335 | #address-cells = <1>; |
| 336 | #size-cells = <0>; |
| 337 | |
| 338 | port@0 { |
| 339 | reg = <0>; |
| 340 | label = "lan0"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 341 | phy-mode = "gmii"; |
| 342 | phy-handle = <&sphy0>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 343 | }; |
| 344 | |
| 345 | port@1 { |
| 346 | reg = <1>; |
| 347 | label = "lan1"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 348 | phy-mode = "gmii"; |
| 349 | phy-handle = <&sphy1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 350 | }; |
| 351 | |
| 352 | port@2 { |
| 353 | reg = <2>; |
| 354 | label = "lan2"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 355 | phy-mode = "gmii"; |
| 356 | phy-handle = <&sphy2>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | port@3 { |
| 360 | reg = <3>; |
| 361 | label = "lan3"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 362 | phy-mode = "gmii"; |
| 363 | phy-handle = <&sphy3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 364 | }; |
| 365 | |
| 366 | port@6 { |
| 367 | reg = <6>; |
| 368 | label = "cpu"; |
| 369 | ethernet = <&gmac0>; |
| 370 | phy-mode = "10gbase-kr"; |
| 371 | |
| 372 | fixed-link { |
| 373 | speed = <10000>; |
| 374 | full-duplex; |
| 375 | pause; |
| 376 | }; |
| 377 | }; |
| 378 | }; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 379 | |
| 380 | mdio { |
| 381 | compatible = "mediatek,dsa-slave-mdio"; |
| 382 | #address-cells = <1>; |
| 383 | #size-cells = <0>; |
| 384 | |
| 385 | sphy0: switch_phy0@0 { |
| 386 | compatible = "ethernet-phy-id03a2.9481"; |
| 387 | reg = <0>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 388 | pinctrl-names = "gbe-led"; |
| 389 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 390 | nvmem-cells = <&phy_calibration_p0>; |
| 391 | nvmem-cell-names = "phy-cal-data"; |
| 392 | }; |
| 393 | |
| 394 | sphy1: switch_phy1@1 { |
| 395 | compatible = "ethernet-phy-id03a2.9481"; |
| 396 | reg = <1>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 397 | pinctrl-names = "gbe-led"; |
| 398 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 399 | nvmem-cells = <&phy_calibration_p1>; |
| 400 | nvmem-cell-names = "phy-cal-data"; |
| 401 | }; |
| 402 | |
| 403 | sphy2: switch_phy2@2 { |
| 404 | compatible = "ethernet-phy-id03a2.9481"; |
| 405 | reg = <2>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 406 | pinctrl-names = "gbe-led"; |
| 407 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 408 | nvmem-cells = <&phy_calibration_p2>; |
| 409 | nvmem-cell-names = "phy-cal-data"; |
| 410 | }; |
| 411 | |
| 412 | sphy3: switch_phy3@3 { |
| 413 | compatible = "ethernet-phy-id03a2.9481"; |
| 414 | reg = <3>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 415 | pinctrl-names = "gbe-led"; |
| 416 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 417 | nvmem-cells = <&phy_calibration_p3>; |
| 418 | nvmem-cell-names = "phy-cal-data"; |
| 419 | }; |
| 420 | }; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 421 | }; |
| 422 | }; |
| 423 | }; |
| 424 | |
| 425 | &hnat { |
| 426 | mtketh-wan = "eth1"; |
| 427 | mtketh-lan = "lan"; |
| 428 | mtketh-lan2 = "eth2"; |
| 429 | mtketh-max-gmac = <3>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 430 | mtketh-ppe-num = <3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 431 | status = "okay"; |
| 432 | }; |
| 433 | |
| 434 | &wed { |
| 435 | dy_txbm_enable = "true"; |
| 436 | dy_txbm_budge = <8>; |
| 437 | txbm_init_sz = <10>; |
| 438 | status = "okay"; |
| 439 | }; |