developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 8 | #include <dt-bindings/gpio/gpio.h> |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 9 | #include "mt7988.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "MediaTek MT7988A DSA 10G SNFI-NAND RFB"; |
| 13 | compatible = "mediatek,mt7988a-dsa-10g-snfi-snand", |
| 14 | /* Reserve this for DVFS if creating new dts */ |
| 15 | "mediatek,mt7988"; |
| 16 | |
| 17 | chosen { |
| 18 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 19 | earlycon=uart8250,mmio32,0x11000000 \ |
| 20 | pci=pcie_bus_perf"; |
| 21 | }; |
| 22 | |
| 23 | memory { |
| 24 | reg = <0 0x40000000 0 0x10000000>; |
| 25 | }; |
| 26 | |
| 27 | nmbm_snfi { |
| 28 | compatible = "generic,nmbm"; |
| 29 | |
| 30 | #address-cells = <1>; |
| 31 | #size-cells = <1>; |
| 32 | |
| 33 | lower-mtd-device = <&snand>; |
| 34 | forced-create; |
| 35 | empty-page-ecc-protected; |
| 36 | |
| 37 | partitions { |
| 38 | compatible = "fixed-partitions"; |
| 39 | #address-cells = <1>; |
| 40 | #size-cells = <1>; |
| 41 | |
| 42 | partition@0 { |
| 43 | label = "BL2"; |
| 44 | reg = <0x00000 0x0100000>; |
| 45 | read-only; |
| 46 | }; |
| 47 | |
| 48 | partition@100000 { |
| 49 | label = "u-boot-env"; |
| 50 | reg = <0x0100000 0x0080000>; |
| 51 | }; |
| 52 | |
| 53 | factory: partition@180000 { |
| 54 | label = "Factory"; |
| 55 | reg = <0x180000 0x0400000>; |
| 56 | }; |
| 57 | |
| 58 | partition@580000 { |
| 59 | label = "FIP"; |
| 60 | reg = <0x580000 0x0200000>; |
| 61 | }; |
| 62 | |
| 63 | partition@780000 { |
| 64 | label = "ubi"; |
developer | be71868 | 2023-05-12 18:09:06 +0800 | [diff] [blame] | 65 | reg = <0x780000 0x7080000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 66 | }; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | wsys_adie: wsys_adie@0 { |
| 71 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 72 | compatible = "mediatek,rebb-mt7988-adie"; |
| 73 | adie_id = <7976>; |
| 74 | sku_type = <3000>; |
| 75 | }; |
| 76 | }; |
| 77 | |
| 78 | &fan { |
developer | fce0d15 | 2024-01-11 13:37:13 +0800 | [diff] [blame] | 79 | pwms = <&pwm 0 50000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 80 | status = "okay"; |
| 81 | }; |
| 82 | |
| 83 | &pwm { |
| 84 | status = "okay"; |
| 85 | }; |
| 86 | |
| 87 | &uart0 { |
| 88 | status = "okay"; |
| 89 | }; |
| 90 | |
developer | 64376db | 2024-04-08 14:04:38 +0800 | [diff] [blame^] | 91 | &i2c0 { |
| 92 | pinctrl-names = "default"; |
| 93 | pinctrl-0 = <&i2c0_pins>; |
| 94 | status = "okay"; |
| 95 | |
| 96 | rt5190a_64: rt5190a@64 { |
| 97 | compatible = "richtek,rt5190a"; |
| 98 | reg = <0x64>; |
| 99 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 100 | vin2-supply = <&rt5190_buck1>; |
| 101 | vin3-supply = <&rt5190_buck1>; |
| 102 | vin4-supply = <&rt5190_buck1>; |
| 103 | |
| 104 | regulators { |
| 105 | rt5190_buck1: buck1 { |
| 106 | regulator-name = "rt5190a-buck1"; |
| 107 | regulator-min-microvolt = <5090000>; |
| 108 | regulator-max-microvolt = <5090000>; |
| 109 | regulator-allowed-modes = |
| 110 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 111 | regulator-boot-on; |
| 112 | }; |
| 113 | buck2 { |
| 114 | regulator-name = "vcore"; |
| 115 | regulator-min-microvolt = <600000>; |
| 116 | regulator-max-microvolt = <1400000>; |
| 117 | regulator-boot-on; |
| 118 | }; |
| 119 | buck3 { |
| 120 | regulator-name = "proc"; |
| 121 | regulator-min-microvolt = <600000>; |
| 122 | regulator-max-microvolt = <1400000>; |
| 123 | regulator-boot-on; |
| 124 | }; |
| 125 | buck4 { |
| 126 | regulator-name = "rt5190a-buck4"; |
| 127 | regulator-min-microvolt = <850000>; |
| 128 | regulator-max-microvolt = <850000>; |
| 129 | regulator-allowed-modes = |
| 130 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 131 | regulator-boot-on; |
| 132 | }; |
| 133 | ldo { |
| 134 | regulator-name = "rt5190a-ldo"; |
| 135 | regulator-min-microvolt = <1200000>; |
| 136 | regulator-max-microvolt = <1200000>; |
| 137 | regulator-boot-on; |
| 138 | }; |
| 139 | }; |
| 140 | }; |
| 141 | }; |
| 142 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 143 | &spi1 { |
| 144 | pinctrl-names = "default"; |
| 145 | /* pin shared with snfi */ |
| 146 | pinctrl-0 = <&spic_pins>; |
| 147 | status = "disabled"; |
| 148 | }; |
| 149 | |
| 150 | &pcie0 { |
| 151 | pinctrl-names = "default"; |
| 152 | pinctrl-0 = <&pcie0_pins>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 153 | wifi-reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; |
| 154 | wifi-reset-msleep = <100>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 155 | status = "okay"; |
| 156 | }; |
| 157 | |
| 158 | &pcie1 { |
| 159 | pinctrl-names = "default"; |
| 160 | pinctrl-0 = <&pcie1_pins>; |
| 161 | status = "okay"; |
| 162 | }; |
| 163 | |
| 164 | &pcie2 { |
| 165 | pinctrl-names = "default"; |
| 166 | pinctrl-0 = <&pcie2_pins>; |
| 167 | status = "disabled"; |
| 168 | }; |
| 169 | |
| 170 | &pcie3 { |
| 171 | pinctrl-names = "default"; |
| 172 | pinctrl-0 = <&pcie3_pins>; |
| 173 | status = "okay"; |
| 174 | }; |
| 175 | |
| 176 | &pio { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 177 | mdio0_pins: mdio0-pins { |
| 178 | mux { |
| 179 | function = "mdio"; |
| 180 | groups = "mdc_mdio0"; |
| 181 | }; |
| 182 | |
| 183 | conf { |
| 184 | groups = "mdc_mdio0"; |
developer | edbe69e | 2023-06-08 11:08:46 +0800 | [diff] [blame] | 185 | drive-strength = <MTK_DRIVE_10mA>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 186 | }; |
| 187 | }; |
| 188 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 189 | gbe0_led0_pins: gbe0-pins { |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 190 | mux { |
| 191 | function = "led"; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 192 | groups = "gbe0_led0"; |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 193 | }; |
| 194 | }; |
| 195 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 196 | gbe1_led0_pins: gbe1-pins { |
| 197 | mux { |
| 198 | function = "led"; |
| 199 | groups = "gbe1_led0"; |
| 200 | }; |
| 201 | }; |
| 202 | |
| 203 | gbe2_led0_pins: gbe2-pins { |
| 204 | mux { |
| 205 | function = "led"; |
| 206 | groups = "gbe2_led0"; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | gbe3_led0_pins: gbe3-pins { |
| 211 | mux { |
| 212 | function = "led"; |
| 213 | groups = "gbe3_led0"; |
| 214 | }; |
| 215 | }; |
| 216 | |
developer | 64376db | 2024-04-08 14:04:38 +0800 | [diff] [blame^] | 217 | i2c0_pins: i2c0-pins-g0 { |
| 218 | mux { |
| 219 | function = "i2c"; |
| 220 | groups = "i2c0_1"; |
| 221 | }; |
| 222 | }; |
| 223 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 224 | pcie0_pins: pcie0-pins { |
| 225 | mux { |
| 226 | function = "pcie"; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 227 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 228 | }; |
| 229 | }; |
| 230 | |
| 231 | pcie1_pins: pcie1-pins { |
| 232 | mux { |
| 233 | function = "pcie"; |
| 234 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 235 | "pcie_wake_n1_0"; |
| 236 | }; |
| 237 | }; |
| 238 | |
| 239 | pcie2_pins: pcie2-pins { |
| 240 | mux { |
| 241 | function = "pcie"; |
| 242 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 243 | "pcie_wake_n2_0"; |
| 244 | }; |
| 245 | }; |
| 246 | |
| 247 | pcie3_pins: pcie3-pins { |
| 248 | mux { |
| 249 | function = "pcie"; |
| 250 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 251 | "pcie_wake_n3_0"; |
| 252 | }; |
| 253 | }; |
| 254 | |
| 255 | snfi_pins: snfi-pins { |
| 256 | mux { |
| 257 | function = "flash"; |
| 258 | groups = "snfi"; |
| 259 | }; |
| 260 | }; |
| 261 | |
| 262 | spic_pins: spi1-pins { |
| 263 | mux { |
| 264 | function = "spi"; |
developer | d516958 | 2023-02-17 10:32:38 +0800 | [diff] [blame] | 265 | groups = "spi1"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 266 | }; |
| 267 | }; |
| 268 | }; |
| 269 | |
| 270 | &watchdog { |
| 271 | status = "disabled"; |
| 272 | }; |
| 273 | |
| 274 | &snand { |
| 275 | pinctrl-names = "default"; |
| 276 | /* pin shared with spic */ |
| 277 | pinctrl-0 = <&snfi_pins>; |
| 278 | status = "okay"; |
| 279 | mediatek,quad-spi; |
| 280 | }; |
| 281 | |
| 282 | ð { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 283 | pinctrl-names = "default"; |
| 284 | pinctrl-0 = <&mdio0_pins>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 285 | status = "okay"; |
| 286 | |
| 287 | gmac0: mac@0 { |
| 288 | compatible = "mediatek,eth-mac"; |
| 289 | reg = <0>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 290 | mac-type = "xgdm"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 291 | phy-mode = "10gbase-kr"; |
| 292 | |
| 293 | fixed-link { |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 294 | speed = <10000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 295 | full-duplex; |
| 296 | pause; |
| 297 | }; |
| 298 | }; |
| 299 | |
| 300 | gmac1: mac@1 { |
| 301 | compatible = "mediatek,eth-mac"; |
| 302 | reg = <1>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 303 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 304 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 305 | phy-handle = <&phy0>; |
| 306 | }; |
| 307 | |
| 308 | gmac2: mac@2 { |
| 309 | compatible = "mediatek,eth-mac"; |
| 310 | reg = <2>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 311 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 312 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 313 | phy-handle = <&phy1>; |
| 314 | }; |
| 315 | |
| 316 | mdio: mdio-bus { |
| 317 | #address-cells = <1>; |
| 318 | #size-cells = <0>; |
developer | 9faf1ef | 2023-03-21 16:49:51 +0800 | [diff] [blame] | 319 | clock-frequency = <10500000>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 320 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 321 | phy0: ethernet-phy@0 { |
| 322 | reg = <0>; |
| 323 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 324 | reset-gpios = <&pio 72 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 325 | reset-assert-us = <100000>; |
| 326 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 327 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | phy1: ethernet-phy@8 { |
| 331 | reg = <8>; |
| 332 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 333 | reset-gpios = <&pio 71 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 334 | reset-assert-us = <100000>; |
| 335 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 336 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | switch@0 { |
| 340 | compatible = "mediatek,mt7988"; |
| 341 | reg = <31>; |
| 342 | ports { |
| 343 | #address-cells = <1>; |
| 344 | #size-cells = <0>; |
| 345 | |
| 346 | port@0 { |
| 347 | reg = <0>; |
| 348 | label = "lan0"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 349 | phy-mode = "gmii"; |
| 350 | phy-handle = <&sphy0>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 351 | }; |
| 352 | |
| 353 | port@1 { |
| 354 | reg = <1>; |
| 355 | label = "lan1"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 356 | phy-mode = "gmii"; |
| 357 | phy-handle = <&sphy1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 358 | }; |
| 359 | |
| 360 | port@2 { |
| 361 | reg = <2>; |
| 362 | label = "lan2"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 363 | phy-mode = "gmii"; |
| 364 | phy-handle = <&sphy2>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 365 | }; |
| 366 | |
| 367 | port@3 { |
| 368 | reg = <3>; |
| 369 | label = "lan3"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 370 | phy-mode = "gmii"; |
| 371 | phy-handle = <&sphy3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 372 | }; |
| 373 | |
| 374 | port@6 { |
| 375 | reg = <6>; |
| 376 | label = "cpu"; |
| 377 | ethernet = <&gmac0>; |
| 378 | phy-mode = "10gbase-kr"; |
| 379 | |
| 380 | fixed-link { |
| 381 | speed = <10000>; |
| 382 | full-duplex; |
| 383 | pause; |
| 384 | }; |
| 385 | }; |
| 386 | }; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 387 | |
| 388 | mdio { |
| 389 | compatible = "mediatek,dsa-slave-mdio"; |
| 390 | #address-cells = <1>; |
| 391 | #size-cells = <0>; |
| 392 | |
| 393 | sphy0: switch_phy0@0 { |
| 394 | compatible = "ethernet-phy-id03a2.9481"; |
| 395 | reg = <0>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 396 | pinctrl-names = "gbe-led"; |
| 397 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 398 | nvmem-cells = <&phy_calibration_p0>; |
| 399 | nvmem-cell-names = "phy-cal-data"; |
| 400 | }; |
| 401 | |
| 402 | sphy1: switch_phy1@1 { |
| 403 | compatible = "ethernet-phy-id03a2.9481"; |
| 404 | reg = <1>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 405 | pinctrl-names = "gbe-led"; |
| 406 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 407 | nvmem-cells = <&phy_calibration_p1>; |
| 408 | nvmem-cell-names = "phy-cal-data"; |
| 409 | }; |
| 410 | |
| 411 | sphy2: switch_phy2@2 { |
| 412 | compatible = "ethernet-phy-id03a2.9481"; |
| 413 | reg = <2>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 414 | pinctrl-names = "gbe-led"; |
| 415 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 416 | nvmem-cells = <&phy_calibration_p2>; |
| 417 | nvmem-cell-names = "phy-cal-data"; |
| 418 | }; |
| 419 | |
| 420 | sphy3: switch_phy3@3 { |
| 421 | compatible = "ethernet-phy-id03a2.9481"; |
| 422 | reg = <3>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 423 | pinctrl-names = "gbe-led"; |
| 424 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 425 | nvmem-cells = <&phy_calibration_p3>; |
| 426 | nvmem-cell-names = "phy-cal-data"; |
| 427 | }; |
| 428 | }; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 429 | }; |
| 430 | }; |
| 431 | }; |
| 432 | |
| 433 | &hnat { |
| 434 | mtketh-wan = "eth1"; |
| 435 | mtketh-lan = "lan"; |
| 436 | mtketh-lan2 = "eth2"; |
| 437 | mtketh-max-gmac = <3>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 438 | mtketh-ppe-num = <3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 439 | status = "okay"; |
| 440 | }; |