developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 8 | #include <dt-bindings/gpio/gpio.h> |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 9 | #include "mt7988.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "MediaTek MT7988A DSA 10G SD RFB"; |
| 13 | compatible = "mediatek,mt7988a-dsa-10g-sd", |
| 14 | /* Reserve this for DVFS if creating new dts */ |
| 15 | "mediatek,mt7988"; |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | root=PARTLABEL=rootfs rootwait \ |
| 20 | rootfstype=squashfs,f2fs pci=pcie_bus_perf"; |
| 21 | }; |
| 22 | |
| 23 | memory { |
| 24 | reg = <0 0x40000000 0 0x10000000>; |
| 25 | }; |
| 26 | |
| 27 | wsys_adie: wsys_adie@0 { |
| 28 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 29 | compatible = "mediatek,rebb-mt7988-adie"; |
| 30 | adie_id = <7976>; |
| 31 | sku_type = <3000>; |
| 32 | }; |
| 33 | |
| 34 | reg_3p3v: regulator-3p3v { |
| 35 | compatible = "regulator-fixed"; |
| 36 | regulator-name = "fixed-3.3V"; |
| 37 | regulator-min-microvolt = <3300000>; |
| 38 | regulator-max-microvolt = <3300000>; |
| 39 | regulator-boot-on; |
| 40 | regulator-always-on; |
| 41 | }; |
| 42 | }; |
| 43 | |
| 44 | &fan { |
developer | fce0d15 | 2024-01-11 13:37:13 +0800 | [diff] [blame] | 45 | pwms = <&pwm 0 50000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 46 | status = "okay"; |
| 47 | }; |
| 48 | |
| 49 | &pwm { |
| 50 | status = "okay"; |
| 51 | }; |
| 52 | |
| 53 | &uart0 { |
| 54 | status = "okay"; |
| 55 | }; |
| 56 | |
developer | 64376db | 2024-04-08 14:04:38 +0800 | [diff] [blame^] | 57 | &i2c0 { |
| 58 | pinctrl-names = "default"; |
| 59 | pinctrl-0 = <&i2c0_pins>; |
| 60 | status = "okay"; |
| 61 | |
| 62 | rt5190a_64: rt5190a@64 { |
| 63 | compatible = "richtek,rt5190a"; |
| 64 | reg = <0x64>; |
| 65 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 66 | vin2-supply = <&rt5190_buck1>; |
| 67 | vin3-supply = <&rt5190_buck1>; |
| 68 | vin4-supply = <&rt5190_buck1>; |
| 69 | |
| 70 | regulators { |
| 71 | rt5190_buck1: buck1 { |
| 72 | regulator-name = "rt5190a-buck1"; |
| 73 | regulator-min-microvolt = <5090000>; |
| 74 | regulator-max-microvolt = <5090000>; |
| 75 | regulator-allowed-modes = |
| 76 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 77 | regulator-boot-on; |
| 78 | }; |
| 79 | buck2 { |
| 80 | regulator-name = "vcore"; |
| 81 | regulator-min-microvolt = <600000>; |
| 82 | regulator-max-microvolt = <1400000>; |
| 83 | regulator-boot-on; |
| 84 | }; |
| 85 | buck3 { |
| 86 | regulator-name = "proc"; |
| 87 | regulator-min-microvolt = <600000>; |
| 88 | regulator-max-microvolt = <1400000>; |
| 89 | regulator-boot-on; |
| 90 | }; |
| 91 | buck4 { |
| 92 | regulator-name = "rt5190a-buck4"; |
| 93 | regulator-min-microvolt = <850000>; |
| 94 | regulator-max-microvolt = <850000>; |
| 95 | regulator-allowed-modes = |
| 96 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 97 | regulator-boot-on; |
| 98 | }; |
| 99 | ldo { |
| 100 | regulator-name = "rt5190a-ldo"; |
| 101 | regulator-min-microvolt = <1200000>; |
| 102 | regulator-max-microvolt = <1200000>; |
| 103 | regulator-boot-on; |
| 104 | }; |
| 105 | }; |
| 106 | }; |
| 107 | }; |
| 108 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 109 | &spi1 { |
| 110 | pinctrl-names = "default"; |
| 111 | /* pin shared with snfi */ |
| 112 | pinctrl-0 = <&spic_pins>; |
| 113 | status = "disabled"; |
| 114 | }; |
| 115 | |
| 116 | &pcie0 { |
| 117 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&pcie0_pins>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 119 | wifi-reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; |
| 120 | wifi-reset-msleep = <100>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 121 | status = "okay"; |
| 122 | }; |
| 123 | |
| 124 | &pcie1 { |
| 125 | pinctrl-names = "default"; |
| 126 | pinctrl-0 = <&pcie1_pins>; |
| 127 | status = "okay"; |
| 128 | }; |
| 129 | |
| 130 | &pcie2 { |
| 131 | pinctrl-names = "default"; |
| 132 | pinctrl-0 = <&pcie2_pins>; |
| 133 | status = "disabled"; |
| 134 | }; |
| 135 | |
| 136 | &pcie3 { |
| 137 | pinctrl-names = "default"; |
| 138 | pinctrl-0 = <&pcie3_pins>; |
| 139 | status = "okay"; |
| 140 | }; |
| 141 | |
| 142 | &pio { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 143 | mdio0_pins: mdio0-pins { |
| 144 | mux { |
| 145 | function = "mdio"; |
| 146 | groups = "mdc_mdio0"; |
| 147 | }; |
| 148 | |
| 149 | conf { |
| 150 | groups = "mdc_mdio0"; |
developer | edbe69e | 2023-06-08 11:08:46 +0800 | [diff] [blame] | 151 | drive-strength = <MTK_DRIVE_10mA>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 152 | }; |
| 153 | }; |
| 154 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 155 | gbe0_led0_pins: gbe0-pins { |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 156 | mux { |
| 157 | function = "led"; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 158 | groups = "gbe0_led0"; |
developer | 63460d6 | 2023-04-11 10:42:32 +0800 | [diff] [blame] | 159 | }; |
| 160 | }; |
| 161 | |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 162 | gbe1_led0_pins: gbe1-pins { |
| 163 | mux { |
| 164 | function = "led"; |
| 165 | groups = "gbe1_led0"; |
| 166 | }; |
| 167 | }; |
| 168 | |
| 169 | gbe2_led0_pins: gbe2-pins { |
| 170 | mux { |
| 171 | function = "led"; |
| 172 | groups = "gbe2_led0"; |
| 173 | }; |
| 174 | }; |
| 175 | |
| 176 | gbe3_led0_pins: gbe3-pins { |
| 177 | mux { |
| 178 | function = "led"; |
| 179 | groups = "gbe3_led0"; |
| 180 | }; |
| 181 | }; |
| 182 | |
developer | 64376db | 2024-04-08 14:04:38 +0800 | [diff] [blame^] | 183 | i2c0_pins: i2c0-pins-g0 { |
| 184 | mux { |
| 185 | function = "i2c"; |
| 186 | groups = "i2c0_1"; |
| 187 | }; |
| 188 | }; |
| 189 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 190 | pcie0_pins: pcie0-pins { |
| 191 | mux { |
| 192 | function = "pcie"; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 193 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 194 | }; |
| 195 | }; |
| 196 | |
| 197 | pcie1_pins: pcie1-pins { |
| 198 | mux { |
| 199 | function = "pcie"; |
| 200 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 201 | "pcie_wake_n1_0"; |
| 202 | }; |
| 203 | }; |
| 204 | |
| 205 | pcie2_pins: pcie2-pins { |
| 206 | mux { |
| 207 | function = "pcie"; |
| 208 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 209 | "pcie_wake_n2_0"; |
| 210 | }; |
| 211 | }; |
| 212 | |
| 213 | pcie3_pins: pcie3-pins { |
| 214 | mux { |
| 215 | function = "pcie"; |
| 216 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 217 | "pcie_wake_n3_0"; |
| 218 | }; |
| 219 | }; |
| 220 | |
| 221 | spic_pins: spi1-pins { |
| 222 | mux { |
| 223 | function = "spi"; |
developer | d516958 | 2023-02-17 10:32:38 +0800 | [diff] [blame] | 224 | groups = "spi1"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 225 | }; |
| 226 | }; |
| 227 | |
| 228 | mmc0_pins_default: mmc0-pins-default { |
| 229 | mux { |
| 230 | function = "flash"; |
developer | b81e95d | 2022-11-08 10:16:29 +0800 | [diff] [blame] | 231 | groups = "sdcard"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 232 | }; |
| 233 | }; |
| 234 | |
| 235 | mmc0_pins_uhs: mmc0-pins-uhs { |
| 236 | mux { |
| 237 | function = "flash"; |
developer | b81e95d | 2022-11-08 10:16:29 +0800 | [diff] [blame] | 238 | groups = "sdcard"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 239 | }; |
| 240 | }; |
| 241 | }; |
| 242 | |
| 243 | &watchdog { |
| 244 | status = "disabled"; |
| 245 | }; |
| 246 | |
| 247 | ð { |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 248 | pinctrl-names = "default"; |
| 249 | pinctrl-0 = <&mdio0_pins>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 250 | status = "okay"; |
| 251 | |
| 252 | gmac0: mac@0 { |
| 253 | compatible = "mediatek,eth-mac"; |
| 254 | reg = <0>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 255 | mac-type = "xgdm"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 256 | phy-mode = "10gbase-kr"; |
| 257 | |
| 258 | fixed-link { |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 259 | speed = <10000>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 260 | full-duplex; |
| 261 | pause; |
| 262 | }; |
| 263 | }; |
| 264 | |
| 265 | gmac1: mac@1 { |
| 266 | compatible = "mediatek,eth-mac"; |
| 267 | reg = <1>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 268 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 269 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 270 | phy-handle = <&phy0>; |
| 271 | }; |
| 272 | |
| 273 | gmac2: mac@2 { |
| 274 | compatible = "mediatek,eth-mac"; |
| 275 | reg = <2>; |
developer | 2cbf2fb | 2022-11-16 12:20:48 +0800 | [diff] [blame] | 276 | mac-type = "xgdm"; |
developer | 59a6bdc | 2023-03-29 11:55:43 +0800 | [diff] [blame] | 277 | phy-mode = "usxgmii"; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 278 | phy-handle = <&phy1>; |
| 279 | }; |
| 280 | |
| 281 | mdio: mdio-bus { |
| 282 | #address-cells = <1>; |
| 283 | #size-cells = <0>; |
developer | 9faf1ef | 2023-03-21 16:49:51 +0800 | [diff] [blame] | 284 | clock-frequency = <10500000>; |
developer | 1d83bed | 2022-11-16 14:11:04 +0800 | [diff] [blame] | 285 | |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 286 | phy0: ethernet-phy@0 { |
| 287 | reg = <0>; |
| 288 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 289 | reset-gpios = <&pio 72 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 290 | reset-assert-us = <100000>; |
| 291 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 292 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 293 | }; |
| 294 | |
| 295 | phy1: ethernet-phy@8 { |
| 296 | reg = <8>; |
| 297 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1721ef6 | 2022-11-24 14:42:19 +0800 | [diff] [blame] | 298 | reset-gpios = <&pio 71 1>; |
developer | c98d48d | 2023-03-02 19:44:01 +0800 | [diff] [blame] | 299 | reset-assert-us = <100000>; |
| 300 | reset-deassert-us = <221000>; |
developer | 4e17c28 | 2023-05-30 10:57:24 +0800 | [diff] [blame] | 301 | mdi-reversal = /bits/ 16 <1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 302 | }; |
| 303 | |
| 304 | switch@0 { |
| 305 | compatible = "mediatek,mt7988"; |
| 306 | reg = <31>; |
| 307 | ports { |
| 308 | #address-cells = <1>; |
| 309 | #size-cells = <0>; |
| 310 | |
| 311 | port@0 { |
| 312 | reg = <0>; |
| 313 | label = "lan0"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 314 | phy-mode = "gmii"; |
| 315 | phy-handle = <&sphy0>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 316 | }; |
| 317 | |
| 318 | port@1 { |
| 319 | reg = <1>; |
| 320 | label = "lan1"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 321 | phy-mode = "gmii"; |
| 322 | phy-handle = <&sphy1>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 323 | }; |
| 324 | |
| 325 | port@2 { |
| 326 | reg = <2>; |
| 327 | label = "lan2"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 328 | phy-mode = "gmii"; |
| 329 | phy-handle = <&sphy2>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | port@3 { |
| 333 | reg = <3>; |
| 334 | label = "lan3"; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 335 | phy-mode = "gmii"; |
| 336 | phy-handle = <&sphy3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | port@6 { |
| 340 | reg = <6>; |
| 341 | label = "cpu"; |
| 342 | ethernet = <&gmac0>; |
| 343 | phy-mode = "10gbase-kr"; |
| 344 | |
| 345 | fixed-link { |
| 346 | speed = <10000>; |
| 347 | full-duplex; |
| 348 | pause; |
| 349 | }; |
| 350 | }; |
| 351 | }; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 352 | |
| 353 | mdio { |
| 354 | compatible = "mediatek,dsa-slave-mdio"; |
| 355 | #address-cells = <1>; |
| 356 | #size-cells = <0>; |
| 357 | |
| 358 | sphy0: switch_phy0@0 { |
| 359 | compatible = "ethernet-phy-id03a2.9481"; |
| 360 | reg = <0>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 361 | pinctrl-names = "gbe-led"; |
| 362 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 363 | nvmem-cells = <&phy_calibration_p0>; |
| 364 | nvmem-cell-names = "phy-cal-data"; |
| 365 | }; |
| 366 | |
| 367 | sphy1: switch_phy1@1 { |
| 368 | compatible = "ethernet-phy-id03a2.9481"; |
| 369 | reg = <1>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 370 | pinctrl-names = "gbe-led"; |
| 371 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 372 | nvmem-cells = <&phy_calibration_p1>; |
| 373 | nvmem-cell-names = "phy-cal-data"; |
| 374 | }; |
| 375 | |
| 376 | sphy2: switch_phy2@2 { |
| 377 | compatible = "ethernet-phy-id03a2.9481"; |
| 378 | reg = <2>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 379 | pinctrl-names = "gbe-led"; |
| 380 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 381 | nvmem-cells = <&phy_calibration_p2>; |
| 382 | nvmem-cell-names = "phy-cal-data"; |
| 383 | }; |
| 384 | |
| 385 | sphy3: switch_phy3@3 { |
| 386 | compatible = "ethernet-phy-id03a2.9481"; |
| 387 | reg = <3>; |
developer | 4af681c | 2023-05-22 14:34:27 +0800 | [diff] [blame] | 388 | pinctrl-names = "gbe-led"; |
| 389 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | e126222 | 2022-10-25 12:20:54 +0800 | [diff] [blame] | 390 | nvmem-cells = <&phy_calibration_p3>; |
| 391 | nvmem-cell-names = "phy-cal-data"; |
| 392 | }; |
| 393 | }; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 394 | }; |
| 395 | }; |
| 396 | }; |
| 397 | |
| 398 | &hnat { |
| 399 | mtketh-wan = "eth1"; |
| 400 | mtketh-lan = "lan"; |
| 401 | mtketh-lan2 = "eth2"; |
| 402 | mtketh-max-gmac = <3>; |
developer | 722ab5f | 2024-02-22 11:01:46 +0800 | [diff] [blame] | 403 | mtketh-ppe-num = <3>; |
developer | 29344f1 | 2022-10-17 12:01:44 +0800 | [diff] [blame] | 404 | status = "okay"; |
| 405 | }; |
| 406 | |
| 407 | &mmc0 { |
| 408 | pinctrl-names = "default", "state_uhs"; |
| 409 | pinctrl-0 = <&mmc0_pins_default>; |
| 410 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 411 | bus-width = <4>; |
| 412 | max-frequency = <52000000>; |
| 413 | cap-sd-highspeed; |
| 414 | vmmc-supply = <®_3p3v>; |
| 415 | vqmmc-supply = <®_3p3v>; |
| 416 | no-mmc; |
| 417 | no-sdio; |
| 418 | status = "okay"; |
| 419 | }; |