blob: 04ce43cc40d0b7beb79487f109c5078ae9a240d8 [file] [log] [blame]
developer05f3b2b2024-08-19 19:17:34 +08001From 32201406775dc530ae7f62a0f0bdc0af09b69dd8 Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
3Date: Wed, 27 Mar 2024 17:50:16 +0800
developer05f3b2b2024-08-19 19:17:34 +08004Subject: [PATCH 060/199] mtk: mt76: mt7996: add kite part number support
developer66e89bc2024-04-23 14:50:01 +08005
developer66e89bc2024-04-23 14:50:01 +08006Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
developer66e89bc2024-04-23 14:50:01 +08007---
8 mt7996/eeprom.c | 35 +++++++++++++++++++++++------------
9 1 file changed, 23 insertions(+), 12 deletions(-)
10
11diff --git a/mt7996/eeprom.c b/mt7996/eeprom.c
developer05f3b2b2024-08-19 19:17:34 +080012index dffcd09d..c4714982 100644
developer66e89bc2024-04-23 14:50:01 +080013--- a/mt7996/eeprom.c
14+++ b/mt7996/eeprom.c
developer05f3b2b2024-08-19 19:17:34 +080015@@ -319,26 +319,39 @@ out:
developer66e89bc2024-04-23 14:50:01 +080016 return ret;
17 }
18
19-static int mt7996_eeprom_parse_efuse_hw_cap(struct mt7996_dev *dev)
20+static int mt7996_eeprom_parse_efuse_hw_cap(struct mt7996_phy *phy,
21+ u8 *path, u8 *rx_path, u8 *nss)
22 {
23 #define MODE_HE_ONLY BIT(0)
24+#define STREAM_MASK GENMASK(2, 0)
25+#define STREAM_OFFSET 1
26+#define TX_PATH_OFFSET 10
27+#define RX_PATH_OFFSET 19
28 #define WTBL_SIZE_GROUP GENMASK(31, 28)
29+#define GET_STREAM_CAP(offs) ({ \
30+ typeof(offs) _offs = (offs); \
31+ ((cap & (STREAM_MASK << _offs)) >> _offs); \
32+})
33+ struct mt7996_dev *dev = phy->dev;
34 u32 cap = 0;
35 int ret;
36+ u8 band_offs = phy->mt76->band_idx * hweight8(STREAM_MASK);
37
38 ret = mt7996_mcu_get_chip_config(dev, &cap);
39 if (ret)
40 return ret;
41
42- cap = 0x4b249248; /* internal hardcode */
43+ dev->has_eht = true;
44 if (cap) {
45 dev->has_eht = !(cap & MODE_HE_ONLY);
46 dev->wtbl_size_group = u32_get_bits(cap, WTBL_SIZE_GROUP);
47+ *nss = min_t(u8, *nss, GET_STREAM_CAP(STREAM_OFFSET + band_offs));
48+ *path = min_t(u8, *path, GET_STREAM_CAP(TX_PATH_OFFSET + band_offs));
49+ *rx_path = min_t(u8, *rx_path, GET_STREAM_CAP(RX_PATH_OFFSET + band_offs));
50 }
51
52- if (dev->wtbl_size_group < 2 || dev->wtbl_size_group > 4 ||
53- is_mt7992(&dev->mt76))
54- dev->wtbl_size_group = 2; /* set default */
55+ if (dev->wtbl_size_group < 2 || dev->wtbl_size_group > 4)
56+ dev->wtbl_size_group = is_mt7996(&dev->mt76) ? 4 : 2; /* set default */
57
58 return 0;
59 }
developer05f3b2b2024-08-19 19:17:34 +080060@@ -382,13 +395,15 @@ static int mt7996_eeprom_parse_band_config(struct mt7996_phy *phy)
developer66e89bc2024-04-23 14:50:01 +080061
62 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy)
63 {
64+ struct mt76_phy *mphy = phy->mt76;
65 u8 path, rx_path, nss, band_idx = phy->mt76->band_idx;
66 u8 *eeprom = dev->mt76.eeprom.data;
67- struct mt76_phy *mphy = phy->mt76;
68- int max_path = 5, max_nss = 4;
69- int ret;
70+ int ret, max_path = 5, max_nss = 4;
71
72 mt7996_parse_eeprom_stream(eeprom, band_idx, &path, &rx_path, &nss);
73+ ret = mt7996_eeprom_parse_efuse_hw_cap(phy, &path, &rx_path, &nss);
74+ if (ret)
75+ return ret;
76
77 if (!path || path > max_path)
78 path = max_path;
developer05f3b2b2024-08-19 19:17:34 +080079@@ -408,10 +423,6 @@ int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy)
developer66e89bc2024-04-23 14:50:01 +080080 dev->chainshift[band_idx + 1] = dev->chainshift[band_idx] +
81 hweight16(mphy->chainmask);
82
83- ret = mt7996_eeprom_parse_efuse_hw_cap(dev);
84- if (ret)
85- return ret;
86-
87 return mt7996_eeprom_parse_band_config(phy);
88 }
89
90--
developer9237f442024-06-14 17:13:04 +0800912.18.0
developer66e89bc2024-04-23 14:50:01 +080092