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e61ece068f057d9c584beaa45fa9f3fac0f97bec
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drivers
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arm
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gic
d1463bd
GICv3: Allow probe for fewer GICR interfaces than exposed by the frame
by Soby Mathew
· Thu Jan 17 14:57:54 2019 +0000
e0f9063
Sanitise includes across codebase
by Antonio Nino Diaz
· Fri Dec 14 00:18:21 2018 +0000
5eb8837
Standardise header guards across codebase
by Antonio Nino Diaz
· Thu Nov 08 10:20:19 2018 +0000
844b487
Mark GICV3, CCI and CCN boot time code as init
by Daniel Boulby
· Tue Sep 18 13:36:39 2018 +0100
29b9f5b
gic: Remove deprecated driver and interfaces
by Antonio Nino Diaz
· Mon Sep 24 17:23:24 2018 +0100
f5a25ad
Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09
by Soby Mathew
· Tue Sep 04 03:35:54 2018 +0100
dd568dd
gicv2: enable configuring IRQ trigger type
by Marcin Wojtas
· Wed Mar 21 09:55:47 2018 +0100
25a17a2
GIC: Fix build error
by Andrew F. Davis
· Thu Aug 30 14:30:54 2018 -0500
bab39e8
gic v3: Fix width of types of helper functions
by Antonio Nino Diaz
· Tue Aug 21 10:03:07 2018 +0100
ca994e7
gic: Fix types
by Antonio Nino Diaz
· Tue Aug 21 10:02:33 2018 +0100
2e59071
gic: Fix definitions
by Antonio Nino Diaz
· Fri Aug 24 11:46:33 2018 +0100
dd4e59e
gic v3: Turn macros into static inline functions
by Antonio Nino Diaz
· Mon Aug 13 15:29:29 2018 +0100
4d23a64
GIC: Do not flush cache when unneeded
by Andrew F. Davis
· Thu Jul 26 13:50:14 2018 -0500
fef5d2d
Fix MISRA Rule 5.3 Part 2
by Daniel Boulby
· Fri May 04 14:04:07 2018 +0100
4e83abb
Fix MISRA Rule 5.1
by Daniel Boulby
· Tue May 01 15:15:34 2018 +0100
692d7ca
Merge pull request #1340 from Andre-ARM/sec-irqs-fixes
by Dimitris Papastamos
· Thu May 17 14:35:34 2018 +0100
5ac9d96
Fix pointer type mismatch of handlers
by Masahiro Yamada
· Thu Apr 19 01:18:48 2018 +0900
e8e94e8
gicv3: Fix support for systems without secure interrupts
by Andre Przywara
· Thu Nov 09 12:08:00 2017 -0600
694f81f
gicv2: Fix support for systems without secure interrupts
by Samuel Holland
· Thu Nov 09 12:07:53 2017 -0600
2257d6d
Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements
by Dimitris Papastamos
· Thu Mar 29 13:20:05 2018 +0100
39b4221
drivers: fix switch statements to comply with MISRA rules
by Jonathan Wright
· Tue Mar 13 15:24:29 2018 +0000
b6982c0
GIC: Fix setting interrupt configuration
by Jeenu Viswambharan
· Thu Mar 22 08:57:52 2018 +0000
4d408b5
Emit warnings when using deprecated GIC init
by Dan Handley
· Thu Mar 01 16:00:15 2018 +0000
2ca18d9
Fix MISRA rule 8.4 Part 1
by Roberto Vargas
· Mon Feb 12 12:36:17 2018 +0000
0571270
Fix MISRA rule 8.4 in common code
by Roberto Vargas
· Mon Feb 12 12:36:17 2018 +0000
45bcb6e
GICv3: Fix Dist restore for when the GIC is reset
by Derek Basehore
· Tue Jan 23 15:49:17 2018 -0800
42ef554
Merge pull request #1145 from etienne-lms/rfc-armv7-2
by davidcunado-arm
· Thu Nov 23 23:41:24 2017 +0000
88d8f45
GIC: Fix Group 0 enabling
by Jeenu Viswambharan
· Tue Nov 07 08:38:23 2017 +0000
fbf5bda
GICv2: Fix populating PE target data
by Jeenu Viswambharan
· Tue Nov 07 16:10:19 2017 +0000
0a8c353
ARMv7: GICv2 driver can manage GICv1 with security extension
by Etienne Carriere
· Sun Nov 05 22:57:38 2017 +0100
aeb267c
GIC: Allow specifying interrupt properties
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
4684bce
GIC: Add helpers to set interrupt configuration
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
6250507
GIC: Add API to set priority mask
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
eb1c12c
GIC: Add API to set/clear interrupt pending
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
dce70b3
GIC: Add API to set interrupt routing
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
ab14e9b
GIC: Add API to raise secure SGI
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
c06f05c
GIC: Add APIs to set interrupt type and query support
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
447b89d
GIC: Add API to set interrupt priority
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
0fcdfff
GIC: Add APIs to enable and disable interrupt
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
24e7029
GIC: Add API to get interrupt active status
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
393fdd9
GICv2: Add driver API to set PE target mask
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
b1e957e
GIC: Add API to get running priority
by Jeenu Viswambharan
· Fri Sep 22 08:32:09 2017 +0100
b333d89
Fix assertion in GIC ITS helper
by Soby Mathew
· Fri Oct 06 17:59:03 2017 +0100
f6f1a32
GICv3: ITS architectural save and restore helpers
by Soby Mathew
· Tue Jul 18 16:12:45 2017 +0100
327548c
GICv3: add functions for save and restore
by Soby Mathew
· Thu Jul 13 15:19:51 2017 +0100
a1b1da8
GICv3: turn some macros into inline functions
by Douglas Raillard
· Wed Jul 26 13:51:00 2017 +0100
1bd2d74
GICv3: Fix gic600.c indentation
by Douglas Raillard
· Thu Aug 03 15:59:49 2017 +0100
d7a901e
Introduce ARM GIC-600 driver
by Jeenu Viswambharan
· Tue Dec 06 16:15:22 2016 +0000
fa3cf0b
Use SPDX license identifiers
by dp-arm
· Wed May 03 09:38:09 2017 +0100
7264513
Flush the GIC driver data after init
by Soby Mathew
· Tue Feb 14 10:11:52 2017 +0000
76647d5
GICv3: Introduce power management APIs for Redistributor
by Jeenu Viswambharan
· Fri Dec 09 11:03:15 2016 +0000
3f00a89
GICv3: Allow either G1S or G0 interrupts to be configured
by Yatharth Kochar
· Tue Sep 06 11:48:05 2016 +0100
14ce777
Merge pull request #678 from soby-mathew/sm/PSCI_AArch32
by danh-arm
· Thu Aug 18 11:38:19 2016 +0100
869e3db
gicv3: disable Group1 NonSecure interrupts during core powerdown
by Sudeep Holla
· Thu Aug 04 16:14:50 2016 +0100
d645232
AArch32: Enable GIC and TZC support
by Soby Mathew
· Thu May 05 13:59:07 2016 +0100
aaf71c8
GICv3: Fix the GICD_IROUTER offset
by Soby Mathew
· Tue Jul 26 17:46:56 2016 +0100
a0fedc4
Rework type usage in Trusted Firmware
by Soby Mathew
· Thu Jun 16 14:52:04 2016 +0100
4f96838
GIC: Ensure SGIs and PPIs are Group0 before setup
by Soby Mathew
· Tue Jun 07 17:06:27 2016 +0100
b3a0a7b
Add support for %p in tf_printf()
by Antonio Nino Diaz
· Tue Feb 02 12:03:38 2016 +0000
50f6fe4
Move private APIs in gic_common.h to a private header
by Soby Mathew
· Mon Feb 01 17:59:22 2016 +0000
421259e
Fix GIC_IPRIORITYR setting in new drivers
by Soby Mathew
· Fri Jan 15 14:20:57 2016 +0000
73f9299
Fix race in GIC IPRIORITY and ITARGET accessors
by Soby Mathew
· Fri Jan 15 14:05:37 2016 +0000
5c5c36b
Rename GICv3 interrupt group macros
by Soby Mathew
· Thu Dec 03 14:12:54 2015 +0000
e063d3c
Add ARM GICv2 driver
by Soby Mathew
· Wed Oct 07 09:45:27 2015 +0100
92712a5
Add ARM GICv3 driver without support for legacy operation
by Achin Gupta
· Thu Sep 03 14:18:02 2015 +0100
29f7cbc
Remove EL2/EL1 GICv3 register updates
by Vikram Kanigiri
· Fri Jun 26 10:13:22 2015 +0100
7f1f062
Use uintptr_t as base address type in ARM driver APIs
by Juan Castillo
· Tue Sep 09 09:49:23 2014 +0100
966b952
Fix reporting of interrupt ID in ARM GIC driver
by Achin Gupta
· Mon May 18 10:56:47 2015 +0100
897333d
Set group status of PPIs and SGIs correctly on GICv3 systems
by Achin Gupta
· Mon Mar 09 21:54:40 2015 +0000
8231295
Improvements to ARM GIC driver
by Juan Castillo
· Mon Oct 20 12:27:28 2014 +0100
f558cac
Rework incorrect use of assert() and panic() in codebase
by Juan Castillo
· Thu Jun 05 09:45:36 2014 +0100
fb42b12
Refactor fvp gic code to be a generic driver
by Dan Handley
· Fri Jun 20 09:43:15 2014 +0100
3f78dc3
Make system register functions inline assembly
by Andrew Thoelke
· Mon Jun 02 15:44:43 2014 +0100
191e86e
Introduce interrupt registration framework in BL3-1
by Achin Gupta
· Fri May 09 10:03:15 2014 +0100
969bdb2
Fix C accessors to GIC distributor registers with set/clear semantics
by Juan Castillo
· Mon Apr 28 12:48:40 2014 +0100
42e75a7
Correct usage of data and instruction barriers
by Andrew Thoelke
· Mon Apr 28 12:28:39 2014 +0100
2bd4ef2
Reduce deep nesting of header files
by Dan Handley
· Wed Apr 09 13:14:54 2014 +0100
930ee2e
Refactor GIC header files
by Dan Handley
· Thu Apr 17 17:48:52 2014 +0100
a70615f
Move include and source files to logical locations
by Dan Handley
· Wed Apr 09 12:48:25 2014 +0100