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git01.mediatek.com / filogic / atf / bfd9da783f507b0d0f7fcbcab0f20a7c8dde9bd7 / plat / intel / soc / stratix10 / include
  1. b56c078 fix(intel): remove redundant NOC header declarations by Sieu Mun Tang · Fri May 13 11:14:08 2022 +0800
  2. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · Tue May 10 20:17:51 2022 +0200
  3. 1a832bf Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration by Madhukar Pappireddy · Fri May 06 19:33:59 2022 +0200
  4. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · Wed Apr 06 10:19:16 2022 +0800
  5. e026eea feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC by Sieu Mun Tang · Thu May 05 23:42:55 2022 +0800
  6. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · Thu May 05 17:07:21 2022 +0800
  7. 616b5e7 fix(intel): refactor NOC header by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:12:23 2020 +0800
  8. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · Mon Feb 28 15:24:59 2022 +0800
  9. 786db4d intel: Change boot source selection by Hadi Asyrafi · Mon Dec 30 16:00:30 2019 +0800
  10. 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · Mon Dec 23 17:58:04 2019 +0800
  11. 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · Mon Dec 23 13:25:33 2019 +0800
  12. e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · Mon Oct 21 16:35:08 2019 +0800
  13. 3afb87a intel: Modify non secure access function by Hadi Asyrafi · Mon Oct 21 16:27:29 2019 +0800
  14. 1fab9c3 Remove redundant declarations. by Madhukar Pappireddy · Thu Jan 02 16:32:41 2020 -0600
  15. 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · Wed Oct 23 18:34:14 2019 +0800
  16. f0fa807 intel: Refactor common platform code [2/5] by Hadi Asyrafi · Wed Oct 23 17:02:55 2019 +0800
  17. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · Wed Oct 23 16:26:53 2019 +0800
  18. 78fee35 intel: stratix10: Fix reliance on hard coded clock information by Hadi Asyrafi · Tue Jul 30 22:18:17 2019 +0800
  19. 309ac01 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 14:48:39 2019 +0800
  20. c81e4f1 Merge changes from topic "jc/shift-overflow" into integration by Soby Mathew · Tue Jul 16 10:11:27 2019 +0000
  21. 8e5662d Update intel platform to not rely on undefined overflow behaviour by Justin Chadwell · Wed Jul 03 14:12:25 2019 +0100
  22. 2b9a741 plat/intel: Fix SMPLSEL for MMC by Tien Hock, Loh · Tue Jul 09 13:17:04 2019 +0800
  23. c0d4d93 intel: Enable watchdog timer on Intel S10 platform by Muhammad Hadi Asyrafi Abdul Halim · Tue Mar 19 17:59:06 2019 +0800
  24. ab34f74 plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform by Tien Hock, Loh · Tue Feb 26 09:25:14 2019 +0800
  25. 3d1063e plat: intel: Fix faulty DDR calibration value by Loh Tien Hock · Wed Feb 13 14:39:31 2019 +0800
  26. 59400a4 plat: intel: Add BL2 support for Stratix 10 SoC by Loh Tien Hock · Mon Feb 04 16:17:24 2019 +0800