1. b3fd376 feat(ti): set L2 cache ECC and and parity on A72 cores by Andrew Davis · 1 year, 7 months ago
  2. e7d7d11 feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles by Andrew Davis · 1 year, 7 months ago
  3. 39f9eee Don't return error information from console_flush by Jimmy Brisson · 4 years, 1 month ago
  4. 54aaf4e ti: k3: common: Set L2 latency on A72 cores by Andrew F. Davis · 5 years ago
  5. b208ae3 ti: k3: common: Remove MSMC port definitions by Andrew F. Davis · 5 years ago
  6. 1eb64a1 Add plat_crash_console_flush to platforms without it by Antonio Nino Diaz · 6 years ago
  7. ce97604 ti: k3: common: Add console initialization base by Nishanth Menon · 8 years ago
  8. f807a34 ti: k3: common: Add platform core management helpers by Benjamin Fair · 8 years ago