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git01.mediatek.com / filogic / atf / 80f13eef1595e1c3addbd61e007bf6bbc925b325 / bl31 / interrupt_mgmt.c
  1. 1c819c3 Use correct type when reading SCR register by Louis Mayencourt · Fri Jan 24 13:30:28 2020 +0000
  2. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  3. e0b757d Fix MISRA defects in BL31 common code by Antonio Nino Diaz · Fri Aug 24 16:30:29 2018 +0100
  4. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  5. 58e32d1 Enable support for EL3 interrupt in IMF by Soby Mathew · Mon Nov 23 13:58:45 2015 +0000
  6. 53c5184 IMF: postpone SCR_EL3 update if context is not initialized by Juan Castillo · Fri Oct 30 14:53:24 2015 +0000
  7. 47903c0 Demonstrate model for routing IRQs to EL3 by Soby Mathew · Tue Jan 13 15:48:26 2015 +0000
  8. f558cac Rework incorrect use of assert() and panic() in codebase by Juan Castillo · Thu Jun 05 09:45:36 2014 +0100
  9. 191e86e Introduce interrupt registration framework in BL3-1 by Achin Gupta · Fri May 09 10:03:15 2014 +0100