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git01.mediatek.com / filogic / atf / 66b7fdc2cddac41e5718d83b3ed4cbc5e7582c46 / plat / intel / soc / agilex / soc
  1. c5baddf plat: intel: Add FPGAINTF configuration to when configuring pinmux by Tien Hock Loh · 4 years, 6 months ago
  2. fcbc33d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · 4 years, 6 months ago
  3. 7a5f8da plat: intel: Fix clock configuration bugs by Tien Hock Loh · 4 years, 6 months ago
  4. 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · 5 years ago
  5. 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · 5 years ago
  6. e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · 5 years ago
  7. 3afb87a intel: Modify non secure access function by Hadi Asyrafi · 5 years ago
  8. 966f282 intel: Fix memory calibration by Hadi Asyrafi · 5 years ago
  9. 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · 5 years ago
  10. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 5 years ago
  11. cc077d9 Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration by Paul Beesley · 5 years ago
  12. 5d7c656 intel: agilex: HMC driver calculate DDR size by Hadi Asyrafi · 5 years ago
  13. 56c4901 intel: agilex: Clear PLL lostlock bypass mode by Hadi Asyrafi · 5 years ago
  14. ad90712 Merge "intel: agilex: Fix memory controller driver" into integration by Paul Beesley · 5 years ago
  15. 83fe38e intel: agilex: Fix memory controller driver by Hadi Asyrafi · 5 years ago
  16. a813fed intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  17. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · 5 years ago