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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +01006#ifndef PLAT_ARM_H
7#define PLAT_ARM_H
Dan Handley9df48042015-03-19 18:58:55 +00008
9#include <bakery_lock.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <cassert.h>
11#include <cpu_data.h>
12#include <stdint.h>
Roberto Vargas00996942017-11-13 13:41:58 +000013#include <spinlock.h>
Summer Qin5ce394c2018-03-12 11:28:26 +080014#include <tzc_common.h>
Scott Brandenbf404c02017-04-10 11:45:52 -070015#include <utils_def.h>
Antonio Nino Diaz61aff002018-10-19 16:52:22 +010016#include <xlat_tables_compat.h>
Dan Handley9df48042015-03-19 18:58:55 +000017
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010018/*******************************************************************************
19 * Forward declarations
20 ******************************************************************************/
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010021struct meminfo;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010022struct image_info;
Soby Mathew96a1c6b2018-01-15 14:45:33 +000023struct bl_params;
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010024
Summer Qin5ce394c2018-03-12 11:28:26 +080025typedef struct arm_tzc_regions_info {
26 unsigned long long base;
27 unsigned long long end;
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010028 unsigned int sec_attr;
Summer Qin5ce394c2018-03-12 11:28:26 +080029 unsigned int nsaid_permissions;
30} arm_tzc_regions_info_t;
31
32/*******************************************************************************
33 * Default mapping definition of the TrustZone Controller for ARM standard
34 * platforms.
35 * Configure:
36 * - Region 0 with no access;
37 * - Region 1 with secure access only;
38 * - the remaining DRAM regions access from the given Non-Secure masters.
39 ******************************************************************************/
Antonio Nino Diazfe7b2be2018-10-30 11:54:20 +000040#if ENABLE_SPM && SPM_DEPRECATED
Summer Qin5ce394c2018-03-12 11:28:26 +080041#define ARM_TZC_REGIONS_DEF \
42 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
43 TZC_REGION_S_RDWR, 0}, \
44 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
45 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
46 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
48 {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \
49 ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
50 PLAT_ARM_TZC_NS_DEV_ACCESS}
51
52#else
53#define ARM_TZC_REGIONS_DEF \
54 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
55 TZC_REGION_S_RDWR, 0}, \
56 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
57 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
58 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
59 PLAT_ARM_TZC_NS_DEV_ACCESS}
60#endif
61
Chris Kay2b54c0c2018-05-09 15:46:07 +010062#define ARM_CASSERT_MMAP \
63 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
64 assert_plat_arm_mmap_mismatch); \
65 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \
66 <= MAX_MMAP_REGIONS, \
Dan Handley9df48042015-03-19 18:58:55 +000067 assert_max_mmap_regions);
68
Roberto Vargase3adc372018-05-23 09:27:06 +010069void arm_setup_romlib(void);
70
Soby Mathew074f6932017-02-28 22:58:29 +000071#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
Dan Handley9df48042015-03-19 18:58:55 +000072/*
73 * Use this macro to instantiate lock before it is used in below
74 * arm_lock_xxx() macros
75 */
Sandrine Bailleuxceb258e2018-07-11 13:59:18 +020076#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
Soby Mathewea26bad2016-11-14 12:25:45 +000077#define ARM_LOCK_GET_INSTANCE (&arm_lock)
Roberto Vargas00996942017-11-13 13:41:58 +000078
79#if !HW_ASSISTED_COHERENCY
80#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock)
81#else
82#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock
83#endif
84#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock)
85
Dan Handley9df48042015-03-19 18:58:55 +000086/*
87 * These are wrapper macros to the Coherent Memory Bakery Lock API.
88 */
89#define arm_lock_init() bakery_lock_init(&arm_lock)
90#define arm_lock_get() bakery_lock_get(&arm_lock)
91#define arm_lock_release() bakery_lock_release(&arm_lock)
92
93#else
94
Dan Handley9df48042015-03-19 18:58:55 +000095/*
Yatharth Kochar2694cba2016-11-14 12:00:41 +000096 * Empty macros for all other BL stages other than BL31 and BL32
Dan Handley9df48042015-03-19 18:58:55 +000097 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +010098#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
Soby Mathewea26bad2016-11-14 12:25:45 +000099#define ARM_LOCK_GET_INSTANCE 0
Dan Handley9df48042015-03-19 18:58:55 +0000100#define arm_lock_init()
101#define arm_lock_get()
102#define arm_lock_release()
103
Soby Mathew074f6932017-02-28 22:58:29 +0000104#endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */
Dan Handley9df48042015-03-19 18:58:55 +0000105
Soby Mathew7799cf72015-04-16 14:49:09 +0100106#if ARM_RECOM_STATE_ID_ENC
107/*
108 * Macros used to parse state information from State-ID if it is using the
109 * recommended encoding for State-ID.
110 */
111#define ARM_LOCAL_PSTATE_WIDTH 4
112#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
113
114/* Macros to construct the composite power state */
115
116/* Make composite power state parameter till power level 0 */
117#if PSCI_EXTENDED_STATE_ID
118
119#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
120 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
121#else
122#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
123 (((lvl0_state) << PSTATE_ID_SHIFT) | \
124 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
125 ((type) << PSTATE_TYPE_SHIFT))
126#endif /* __PSCI_EXTENDED_STATE_ID__ */
127
128/* Make composite power state parameter till power level 1 */
129#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
130 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
131 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
132
Soby Mathewa869de12015-05-08 10:18:59 +0100133/* Make composite power state parameter till power level 2 */
134#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
135 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
136 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
137
Soby Mathew7799cf72015-04-16 14:49:09 +0100138#endif /* __ARM_RECOM_STATE_ID_ENC__ */
139
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000140/* ARM State switch error codes */
141#define STATE_SW_E_PARAM (-2)
142#define STATE_SW_E_DENIED (-3)
Dan Handley9df48042015-03-19 18:58:55 +0000143
Dan Handley9df48042015-03-19 18:58:55 +0000144/* IO storage utility functions */
145void arm_io_setup(void);
146
147/* Security utility functions */
Summer Qin5ce394c2018-03-12 11:28:26 +0800148void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +0000149struct tzc_dmc500_driver_data;
Summer Qin5ce394c2018-03-12 11:28:26 +0800150void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
151 const arm_tzc_regions_info_t *tzc_regions);
Dan Handley9df48042015-03-19 18:58:55 +0000152
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100153/* Console utility functions */
154void arm_console_boot_init(void);
155void arm_console_boot_end(void);
156void arm_console_runtime_init(void);
157void arm_console_runtime_end(void);
158
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100159/* Systimer utility function */
160void arm_configure_sys_timer(void);
161
Dan Handley9df48042015-03-19 18:58:55 +0000162/* PM utility functions */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100163int arm_validate_power_state(unsigned int power_state,
164 psci_power_state_t *req_state);
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100165int arm_validate_psci_entrypoint(uintptr_t entrypoint);
Soby Mathew0d9e8522015-07-15 13:36:24 +0100166int arm_validate_ns_entrypoint(uintptr_t entrypoint);
Soby Mathew9ca28062017-10-11 16:08:58 +0100167void arm_system_pwr_domain_save(void);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100168void arm_system_pwr_domain_resume(void);
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000169int arm_psci_read_mem_protect(int *enabled);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100170int arm_nor_psci_write_mem_protect(int val);
Roberto Vargas550eb082018-01-05 16:00:05 +0000171void arm_nor_psci_do_static_mem_protect(void);
172void arm_nor_psci_do_dyn_mem_protect(void);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100173int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100174
175/* Topology utility function */
176int arm_check_mpidr(u_register_t mpidr);
Dan Handley9df48042015-03-19 18:58:55 +0000177
178/* BL1 utility functions */
179void arm_bl1_early_platform_setup(void);
180void arm_bl1_platform_setup(void);
181void arm_bl1_plat_arch_setup(void);
182
183/* BL2 utility functions */
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000184void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout);
Dan Handley9df48042015-03-19 18:58:55 +0000185void arm_bl2_platform_setup(void);
186void arm_bl2_plat_arch_setup(void);
187uint32_t arm_get_spsr_for_bl32_entry(void);
188uint32_t arm_get_spsr_for_bl33_entry(void);
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000189int arm_bl2_handle_post_image_load(unsigned int image_id);
Dan Handley9df48042015-03-19 18:58:55 +0000190
Roberto Vargas52207802017-11-17 13:22:18 +0000191/* BL2 at EL3 functions */
192void arm_bl2_el3_early_platform_setup(void);
193void arm_bl2_el3_plat_arch_setup(void);
194
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100195/* BL2U utility functions */
196void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
197 void *plat_info);
198void arm_bl2u_platform_setup(void);
199void arm_bl2u_plat_arch_setup(void);
200
Juan Castillo7d199412015-12-14 09:35:25 +0000201/* BL31 utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000202void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
203 uintptr_t hw_config, void *plat_params_from_bl2);
Dan Handley9df48042015-03-19 18:58:55 +0000204void arm_bl31_platform_setup(void);
Soby Mathew2fd66be2015-12-09 11:38:43 +0000205void arm_bl31_plat_runtime_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000206void arm_bl31_plat_arch_setup(void);
207
208/* TSP utility functions */
209void arm_tsp_early_platform_setup(void);
210
Soby Mathew7b754182016-07-11 14:15:27 +0100211/* SP_MIN utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000212void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
213 uintptr_t hw_config, void *plat_params_from_bl2);
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100214void arm_sp_min_plat_runtime_setup(void);
Soby Mathew7b754182016-07-11 14:15:27 +0100215
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100216/* FIP TOC validity check */
217int arm_io_is_toc_valid(void);
Dan Handley9df48042015-03-19 18:58:55 +0000218
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000219/* Utility functions for Dynamic Config */
220void arm_load_tb_fw_config(void);
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000221void arm_bl2_set_tb_cfg_addr(void *dtb);
222void arm_bl2_dyn_cfg_init(void);
John Tsichritzisc34341a2018-07-30 13:41:52 +0100223void arm_bl1_set_mbedtls_heap(void);
224int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000225
Dan Handley9df48042015-03-19 18:58:55 +0000226/*
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100227 * Free the memory storing initialization code only used during an images boot
228 * time so it can be reclaimed for runtime data
229 */
230void arm_free_init_memory(void);
231
232/*
Dan Handley9df48042015-03-19 18:58:55 +0000233 * Mandatory functions required in ARM standard platforms
234 */
Soby Mathew47e43f22016-02-01 14:04:34 +0000235unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000236void plat_arm_gic_driver_init(void);
Dan Handley9df48042015-03-19 18:58:55 +0000237void plat_arm_gic_init(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000238void plat_arm_gic_cpuif_enable(void);
239void plat_arm_gic_cpuif_disable(void);
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000240void plat_arm_gic_redistif_on(void);
241void plat_arm_gic_redistif_off(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000242void plat_arm_gic_pcpu_init(void);
Soby Mathew9ca28062017-10-11 16:08:58 +0100243void plat_arm_gic_save(void);
244void plat_arm_gic_resume(void);
Dan Handley9df48042015-03-19 18:58:55 +0000245void plat_arm_security_setup(void);
246void plat_arm_pwrc_setup(void);
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000247void plat_arm_interconnect_init(void);
248void plat_arm_interconnect_enter_coherency(void);
249void plat_arm_interconnect_exit_coherency(void);
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100250void plat_arm_program_trusted_mailbox(uintptr_t address);
Sathees Balya22576072018-09-03 17:41:13 +0100251int plat_arm_bl1_fwu_needed(void);
252void plat_arm_error_handler(int err);
Dan Handley9df48042015-03-19 18:58:55 +0000253
Summer Qin93c812f2017-02-28 16:46:17 +0000254#if ARM_PLAT_MT
255unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
256#endif
257
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100258/*
259 * This function is called after loading SCP_BL2 image and it is used to perform
260 * any platform-specific actions required to handle the SCP firmware.
261 */
262int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100263
Dan Handley9df48042015-03-19 18:58:55 +0000264/*
265 * Optional functions required in ARM standard platforms
266 */
267void plat_arm_io_setup(void);
268int plat_arm_get_alt_image_source(
Juan Castillo3a66aca2015-04-13 17:36:19 +0100269 unsigned int image_id,
270 uintptr_t *dev_handle,
271 uintptr_t *image_spec);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100272unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
Vikram Kanigiri07035432015-11-12 18:52:34 +0000273const mmap_region_t *plat_arm_get_mmap(void);
Dan Handley9df48042015-03-19 18:58:55 +0000274
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100275/* Allow platform to override psci_pm_ops during runtime */
276const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
277
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000278/* Execution state switch in ARM platforms */
279int arm_execution_state_switch(unsigned int smc_fid,
280 uint32_t pc_hi,
281 uint32_t pc_lo,
282 uint32_t cookie_hi,
283 uint32_t cookie_lo,
284 void *handle);
285
Soby Mathew6d07e672018-03-01 10:53:33 +0000286/* Optional functions for SP_MIN */
287void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
288 u_register_t arg2, u_register_t arg3);
289
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000290/* global variables */
291extern plat_psci_ops_t plat_arm_psci_pm_ops;
292extern const mmap_region_t plat_arm_mmap[];
Jeenu Viswambharan4542cfe2018-07-19 08:03:46 +0100293extern const unsigned int arm_pm_idle_states[];
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000294
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +0100295#endif /* PLAT_ARM_H */