Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 6 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/debug.h> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 11 | #include <cortex_a53.h> |
| 12 | #include <cpu_macros.S> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 13 | |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 14 | #if A53_DISABLE_NON_TEMPORAL_HINT |
| 15 | #undef ERRATA_A53_836870 |
| 16 | #define ERRATA_A53_836870 1 |
| 17 | #endif |
| 18 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 19 | /* --------------------------------------------- |
| 20 | * Disable intra-cluster coherency |
| 21 | * --------------------------------------------- |
| 22 | */ |
| 23 | func cortex_a53_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 24 | ldcopr16 r0, r1, CORTEX_A53_ECTLR |
| 25 | bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT |
| 26 | stcopr16 r0, r1, CORTEX_A53_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 27 | isb |
| 28 | dsb sy |
| 29 | bx lr |
| 30 | endfunc cortex_a53_disable_smp |
| 31 | |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 32 | /* --------------------------------------------------- |
| 33 | * Errata Workaround for Cortex A53 Errata #819472. |
| 34 | * This applies only to revision <= r0p1 of Cortex A53. |
| 35 | * --------------------------------------------------- |
| 36 | */ |
| 37 | func check_errata_819472 |
| 38 | /* |
| 39 | * Even though this is only needed for revision <= r0p1, it |
| 40 | * is always applied due to limitations of the current |
| 41 | * errata framework. |
| 42 | */ |
| 43 | mov r0, #ERRATA_APPLIES |
| 44 | bx lr |
| 45 | endfunc check_errata_819472 |
| 46 | |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 47 | add_erratum_entry cortex_a53, ERRATUM(819472), ERRATA_A53_819472 |
| 48 | |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 49 | /* --------------------------------------------------- |
| 50 | * Errata Workaround for Cortex A53 Errata #824069. |
| 51 | * This applies only to revision <= r0p2 of Cortex A53. |
| 52 | * --------------------------------------------------- |
| 53 | */ |
| 54 | func check_errata_824069 |
| 55 | /* |
| 56 | * Even though this is only needed for revision <= r0p2, it |
| 57 | * is always applied due to limitations of the current |
| 58 | * errata framework. |
| 59 | */ |
| 60 | mov r0, #ERRATA_APPLIES |
| 61 | bx lr |
| 62 | endfunc check_errata_824069 |
| 63 | |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 64 | add_erratum_entry cortex_a53, ERRATUM(824069), ERRATA_A53_824069 |
| 65 | |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 66 | /* -------------------------------------------------- |
| 67 | * Errata Workaround for Cortex A53 Errata #826319. |
| 68 | * This applies only to revision <= r0p2 of Cortex A53. |
| 69 | * Inputs: |
| 70 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 71 | * Shall clobber: r0-r3 |
| 72 | * -------------------------------------------------- |
| 73 | */ |
| 74 | func errata_a53_826319_wa |
| 75 | /* |
| 76 | * Compare r0 against revision r0p2 |
| 77 | */ |
| 78 | mov r2, lr |
| 79 | bl check_errata_826319 |
| 80 | mov lr, r2 |
| 81 | cmp r0, #ERRATA_NOT_APPLIES |
| 82 | beq 1f |
| 83 | ldcopr r0, CORTEX_A53_L2ACTLR |
| 84 | bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN |
| 85 | orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH |
| 86 | stcopr r0, CORTEX_A53_L2ACTLR |
| 87 | 1: |
| 88 | bx lr |
| 89 | endfunc errata_a53_826319_wa |
| 90 | |
| 91 | func check_errata_826319 |
| 92 | mov r1, #0x02 |
| 93 | b cpu_rev_var_ls |
| 94 | endfunc check_errata_826319 |
| 95 | |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 96 | add_erratum_entry cortex_a53, ERRATUM(826319), ERRATA_A53_826319 |
| 97 | |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 98 | /* --------------------------------------------------- |
| 99 | * Errata Workaround for Cortex A53 Errata #827319. |
| 100 | * This applies only to revision <= r0p2 of Cortex A53. |
| 101 | * --------------------------------------------------- |
| 102 | */ |
| 103 | func check_errata_827319 |
| 104 | /* |
| 105 | * Even though this is only needed for revision <= r0p2, it |
| 106 | * is always applied due to limitations of the current |
| 107 | * errata framework. |
| 108 | */ |
| 109 | mov r0, #ERRATA_APPLIES |
| 110 | bx lr |
| 111 | endfunc check_errata_827319 |
| 112 | |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 113 | add_erratum_entry cortex_a53, ERRATUM(827319), ERRATA_A53_827319 |
| 114 | |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 115 | /* --------------------------------------------------------------------- |
| 116 | * Disable the cache non-temporal hint. |
| 117 | * |
| 118 | * This ignores the Transient allocation hint in the MAIR and treats |
| 119 | * allocations the same as non-transient allocation types. As a result, |
| 120 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 121 | * equivalent LDP and STP instructions. |
| 122 | * |
| 123 | * This is relevant only for revisions <= r0p3 of Cortex-A53. |
| 124 | * From r0p4 and onwards, the bit to disable the hint is enabled by |
| 125 | * default at reset. |
| 126 | * |
| 127 | * Inputs: |
| 128 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 129 | * Shall clobber: r0-r3 |
| 130 | * --------------------------------------------------------------------- |
| 131 | */ |
| 132 | func a53_disable_non_temporal_hint |
| 133 | /* |
| 134 | * Compare r0 against revision r0p3 |
| 135 | */ |
| 136 | mov r2, lr |
| 137 | bl check_errata_disable_non_temporal_hint |
| 138 | mov lr, r2 |
| 139 | cmp r0, #ERRATA_NOT_APPLIES |
| 140 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 141 | ldcopr16 r0, r1, CORTEX_A53_CPUACTLR |
| 142 | orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH |
| 143 | stcopr16 r0, r1, CORTEX_A53_CPUACTLR |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 144 | 1: |
| 145 | bx lr |
| 146 | endfunc a53_disable_non_temporal_hint |
| 147 | |
| 148 | func check_errata_disable_non_temporal_hint |
| 149 | mov r1, #0x03 |
| 150 | b cpu_rev_var_ls |
| 151 | endfunc check_errata_disable_non_temporal_hint |
| 152 | |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 153 | add_erratum_entry cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT, \ |
| 154 | disable_non_temporal_hint |
| 155 | |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 156 | /* -------------------------------------------------- |
| 157 | * Errata Workaround for Cortex A53 Errata #855873. |
| 158 | * |
| 159 | * This applies only to revisions >= r0p3 of Cortex A53. |
| 160 | * Earlier revisions of the core are affected as well, but don't |
| 161 | * have the chicken bit in the CPUACTLR register. It is expected that |
| 162 | * the rich OS takes care of that, especially as the workaround is |
| 163 | * shared with other erratas in those revisions of the CPU. |
| 164 | * Inputs: |
| 165 | * r0: variant[4:7] and revision[0:3] of current cpu. |
| 166 | * Shall clobber: r0-r3 |
| 167 | * -------------------------------------------------- |
| 168 | */ |
| 169 | func errata_a53_855873_wa |
| 170 | /* |
| 171 | * Compare r0 against revision r0p3 and higher |
| 172 | */ |
| 173 | mov r2, lr |
| 174 | bl check_errata_855873 |
| 175 | mov lr, r2 |
| 176 | cmp r0, #ERRATA_NOT_APPLIES |
| 177 | beq 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 178 | ldcopr16 r0, r1, CORTEX_A53_CPUACTLR |
| 179 | orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI |
| 180 | stcopr16 r0, r1, CORTEX_A53_CPUACTLR |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 181 | 1: |
| 182 | bx lr |
| 183 | endfunc errata_a53_855873_wa |
| 184 | |
| 185 | func check_errata_855873 |
| 186 | mov r1, #0x03 |
| 187 | b cpu_rev_var_hs |
| 188 | endfunc check_errata_855873 |
| 189 | |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 190 | add_erratum_entry cortex_a53, ERRATUM(855873), ERRATA_A53_855873 |
| 191 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 192 | /* ------------------------------------------------- |
| 193 | * The CPU Ops reset function for Cortex-A53. |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 194 | * Shall clobber: r0-r6 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 195 | * ------------------------------------------------- |
| 196 | */ |
| 197 | func cortex_a53_reset_func |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 198 | mov r5, lr |
| 199 | bl cpu_get_rev_var |
| 200 | mov r4, r0 |
| 201 | |
| 202 | #if ERRATA_A53_826319 |
| 203 | mov r0, r4 |
| 204 | bl errata_a53_826319_wa |
| 205 | #endif |
| 206 | |
| 207 | #if ERRATA_A53_836870 |
| 208 | mov r0, r4 |
| 209 | bl a53_disable_non_temporal_hint |
| 210 | #endif |
| 211 | |
| 212 | #if ERRATA_A53_855873 |
| 213 | mov r0, r4 |
| 214 | bl errata_a53_855873_wa |
| 215 | #endif |
| 216 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 217 | /* --------------------------------------------- |
| 218 | * Enable the SMP bit. |
| 219 | * --------------------------------------------- |
| 220 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 221 | ldcopr16 r0, r1, CORTEX_A53_ECTLR |
| 222 | orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT |
| 223 | stcopr16 r0, r1, CORTEX_A53_ECTLR |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 224 | isb |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 225 | bx r5 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 226 | endfunc cortex_a53_reset_func |
| 227 | |
| 228 | /* ---------------------------------------------------- |
| 229 | * The CPU Ops core power down function for Cortex-A53. |
| 230 | * ---------------------------------------------------- |
| 231 | */ |
| 232 | func cortex_a53_core_pwr_dwn |
| 233 | push {r12, lr} |
| 234 | |
| 235 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 236 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 237 | ldcopr r0, SCTLR |
| 238 | tst r0, #SCTLR_C_BIT |
| 239 | ASM_ASSERT(eq) |
| 240 | #endif |
| 241 | |
| 242 | /* --------------------------------------------- |
| 243 | * Flush L1 caches. |
| 244 | * --------------------------------------------- |
| 245 | */ |
| 246 | mov r0, #DC_OP_CISW |
| 247 | bl dcsw_op_level1 |
| 248 | |
| 249 | /* --------------------------------------------- |
| 250 | * Come out of intra cluster coherency |
| 251 | * --------------------------------------------- |
| 252 | */ |
| 253 | pop {r12, lr} |
| 254 | b cortex_a53_disable_smp |
| 255 | endfunc cortex_a53_core_pwr_dwn |
| 256 | |
| 257 | /* ------------------------------------------------------- |
| 258 | * The CPU Ops cluster power down function for Cortex-A53. |
| 259 | * Clobbers: r0-r3 |
| 260 | * ------------------------------------------------------- |
| 261 | */ |
| 262 | func cortex_a53_cluster_pwr_dwn |
| 263 | push {r12, lr} |
| 264 | |
| 265 | /* Assert if cache is enabled */ |
Matt Ma | 41b0094 | 2017-11-22 19:31:28 +0800 | [diff] [blame] | 266 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 267 | ldcopr r0, SCTLR |
| 268 | tst r0, #SCTLR_C_BIT |
| 269 | ASM_ASSERT(eq) |
| 270 | #endif |
| 271 | |
| 272 | /* --------------------------------------------- |
| 273 | * Flush L1 caches. |
| 274 | * --------------------------------------------- |
| 275 | */ |
| 276 | mov r0, #DC_OP_CISW |
| 277 | bl dcsw_op_level1 |
| 278 | |
| 279 | /* --------------------------------------------- |
| 280 | * Disable the optional ACP. |
| 281 | * --------------------------------------------- |
| 282 | */ |
| 283 | bl plat_disable_acp |
| 284 | |
| 285 | /* --------------------------------------------- |
| 286 | * Flush L2 caches. |
| 287 | * --------------------------------------------- |
| 288 | */ |
| 289 | mov r0, #DC_OP_CISW |
| 290 | bl dcsw_op_level2 |
| 291 | |
| 292 | /* --------------------------------------------- |
| 293 | * Come out of intra cluster coherency |
| 294 | * --------------------------------------------- |
| 295 | */ |
| 296 | pop {r12, lr} |
| 297 | b cortex_a53_disable_smp |
| 298 | endfunc cortex_a53_cluster_pwr_dwn |
| 299 | |
Jayanth Dodderi Chidanand | 0dd7114 | 2023-04-12 22:14:59 +0100 | [diff] [blame] | 300 | errata_report_shim cortex_a53 |
Dimitris Papastamos | 9c47a5a | 2017-06-05 13:37:25 +0100 | [diff] [blame] | 301 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 302 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 303 | cortex_a53_reset_func, \ |
| 304 | cortex_a53_core_pwr_dwn, \ |
| 305 | cortex_a53_cluster_pwr_dwn |