| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
| 9 | #include <cortex_a53.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <debug.h> |
| 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable intra-cluster coherency |
| 15 | * --------------------------------------------- |
| 16 | */ |
| 17 | func cortex_a53_disable_smp |
| Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 18 | ldcopr16 r0, r1, CORTEX_A53_ECTLR |
| 19 | bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT |
| 20 | stcopr16 r0, r1, CORTEX_A53_ECTLR |
| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 21 | isb |
| 22 | dsb sy |
| 23 | bx lr |
| 24 | endfunc cortex_a53_disable_smp |
| 25 | |
| 26 | /* ------------------------------------------------- |
| 27 | * The CPU Ops reset function for Cortex-A53. |
| 28 | * ------------------------------------------------- |
| 29 | */ |
| 30 | func cortex_a53_reset_func |
| 31 | /* --------------------------------------------- |
| 32 | * Enable the SMP bit. |
| 33 | * --------------------------------------------- |
| 34 | */ |
| Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 35 | ldcopr16 r0, r1, CORTEX_A53_ECTLR |
| 36 | orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT |
| 37 | stcopr16 r0, r1, CORTEX_A53_ECTLR |
| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 38 | isb |
| 39 | bx lr |
| 40 | endfunc cortex_a53_reset_func |
| 41 | |
| 42 | /* ---------------------------------------------------- |
| 43 | * The CPU Ops core power down function for Cortex-A53. |
| 44 | * ---------------------------------------------------- |
| 45 | */ |
| 46 | func cortex_a53_core_pwr_dwn |
| 47 | push {r12, lr} |
| 48 | |
| 49 | /* Assert if cache is enabled */ |
| 50 | #if ASM_ASSERTION |
| 51 | ldcopr r0, SCTLR |
| 52 | tst r0, #SCTLR_C_BIT |
| 53 | ASM_ASSERT(eq) |
| 54 | #endif |
| 55 | |
| 56 | /* --------------------------------------------- |
| 57 | * Flush L1 caches. |
| 58 | * --------------------------------------------- |
| 59 | */ |
| 60 | mov r0, #DC_OP_CISW |
| 61 | bl dcsw_op_level1 |
| 62 | |
| 63 | /* --------------------------------------------- |
| 64 | * Come out of intra cluster coherency |
| 65 | * --------------------------------------------- |
| 66 | */ |
| 67 | pop {r12, lr} |
| 68 | b cortex_a53_disable_smp |
| 69 | endfunc cortex_a53_core_pwr_dwn |
| 70 | |
| 71 | /* ------------------------------------------------------- |
| 72 | * The CPU Ops cluster power down function for Cortex-A53. |
| 73 | * Clobbers: r0-r3 |
| 74 | * ------------------------------------------------------- |
| 75 | */ |
| 76 | func cortex_a53_cluster_pwr_dwn |
| 77 | push {r12, lr} |
| 78 | |
| 79 | /* Assert if cache is enabled */ |
| 80 | #if ASM_ASSERTION |
| 81 | ldcopr r0, SCTLR |
| 82 | tst r0, #SCTLR_C_BIT |
| 83 | ASM_ASSERT(eq) |
| 84 | #endif |
| 85 | |
| 86 | /* --------------------------------------------- |
| 87 | * Flush L1 caches. |
| 88 | * --------------------------------------------- |
| 89 | */ |
| 90 | mov r0, #DC_OP_CISW |
| 91 | bl dcsw_op_level1 |
| 92 | |
| 93 | /* --------------------------------------------- |
| 94 | * Disable the optional ACP. |
| 95 | * --------------------------------------------- |
| 96 | */ |
| 97 | bl plat_disable_acp |
| 98 | |
| 99 | /* --------------------------------------------- |
| 100 | * Flush L2 caches. |
| 101 | * --------------------------------------------- |
| 102 | */ |
| 103 | mov r0, #DC_OP_CISW |
| 104 | bl dcsw_op_level2 |
| 105 | |
| 106 | /* --------------------------------------------- |
| 107 | * Come out of intra cluster coherency |
| 108 | * --------------------------------------------- |
| 109 | */ |
| 110 | pop {r12, lr} |
| 111 | b cortex_a53_disable_smp |
| 112 | endfunc cortex_a53_cluster_pwr_dwn |
| 113 | |
| 114 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 115 | cortex_a53_reset_func, \ |
| 116 | cortex_a53_core_pwr_dwn, \ |
| 117 | cortex_a53_cluster_pwr_dwn |