blob: b56e98b5f327261ef5f17300791b786dbff65ae6 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +01007#ifndef PSCI_H
8#define PSCI_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Soby Mathew981487a2015-07-13 14:10:57 +010010#include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <common/bl_common.h>
13#include <lib/bakery_lock.h>
14#include <lib/psci/psci_lib.h> /* To maintain compatibility for SPDs */
15#include <lib/utils_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010016
Achin Gupta4f6ad662013-10-25 09:08:21 +010017/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000018 * Number of power domains whose state this PSCI implementation can track
Soby Mathew523d6332015-01-08 18:02:19 +000019 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010020#ifdef PLAT_NUM_PWR_DOMAINS
21#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
Soby Mathew523d6332015-01-08 18:02:19 +000022#else
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060023#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT)
Soby Mathew523d6332015-01-08 18:02:19 +000024#endif
25
Soby Mathew981487a2015-07-13 14:10:57 +010026#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \
27 PLATFORM_CORE_COUNT)
28
29/* This is the power level corresponding to a CPU */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010030#define PSCI_CPU_PWR_LVL U(0)
Soby Mathew981487a2015-07-13 14:10:57 +010031
32/*
33 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND
34 * uses the old power_state parameter format which has 2 bits to specify the
35 * power level, this constant is defined to be 3.
36 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070037#define PSCI_MAX_PWR_LVL U(3)
Soby Mathew981487a2015-07-13 14:10:57 +010038
Soby Mathew523d6332015-01-08 18:02:19 +000039/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000040 * Defines for runtime services function ids
Achin Gupta4f6ad662013-10-25 09:08:21 +010041 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070042#define PSCI_VERSION U(0x84000000)
43#define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001)
44#define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001)
45#define PSCI_CPU_OFF U(0x84000002)
46#define PSCI_CPU_ON_AARCH32 U(0x84000003)
47#define PSCI_CPU_ON_AARCH64 U(0xc4000003)
48#define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004)
49#define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004)
50#define PSCI_MIG_AARCH32 U(0x84000005)
51#define PSCI_MIG_AARCH64 U(0xc4000005)
52#define PSCI_MIG_INFO_TYPE U(0x84000006)
53#define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007)
54#define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007)
55#define PSCI_SYSTEM_OFF U(0x84000008)
56#define PSCI_SYSTEM_RESET U(0x84000009)
57#define PSCI_FEATURES U(0x8400000A)
58#define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d)
59#define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d)
60#define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E)
61#define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E)
62#define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010)
63#define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010)
64#define PSCI_STAT_COUNT_AARCH32 U(0x84000011)
65#define PSCI_STAT_COUNT_AARCH64 U(0xc4000011)
Roberto Vargasb820ad02017-07-26 09:23:09 +010066#define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012)
67#define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012)
Roberto Vargas0a4c2612017-08-03 08:16:16 +010068#define PSCI_MEM_PROTECT U(0x84000013)
69#define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014)
70#define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014)
Soby Mathew6cdddaf2015-01-07 11:10:22 +000071
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000072/*
Juan Castillo4dc4a472014-08-12 11:17:06 +010073 * Number of PSCI calls (above) implemented
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000074 */
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010075#if ENABLE_PSCI_STAT
Varun Wadekarc6a11f62017-05-25 18:04:48 -070076#define PSCI_NUM_CALLS U(22)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010077#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -070078#define PSCI_NUM_CALLS U(18)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010079#endif
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000080
Soby Mathewd0194872016-04-29 19:01:30 +010081/* The macros below are used to identify PSCI calls from the SMC function ID */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070082#define PSCI_FID_MASK U(0xffe0)
83#define PSCI_FID_VALUE U(0)
Soby Mathewd0194872016-04-29 19:01:30 +010084#define is_psci_fid(_fid) \
85 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE)
86
Achin Gupta4f6ad662013-10-25 09:08:21 +010087/*******************************************************************************
88 * PSCI Migrate and friends
89 ******************************************************************************/
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010090#define PSCI_TOS_UP_MIG_CAP 0
91#define PSCI_TOS_NOT_UP_MIG_CAP 1
92#define PSCI_TOS_NOT_PRESENT_MP 2
Achin Gupta4f6ad662013-10-25 09:08:21 +010093
94/*******************************************************************************
95 * PSCI CPU_SUSPEND 'power_state' parameter specific defines
96 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070097#define PSTATE_ID_SHIFT U(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010098
Soby Mathew981487a2015-07-13 14:10:57 +010099#if PSCI_EXTENDED_STATE_ID
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700100#define PSTATE_VALID_MASK U(0xB0000000)
101#define PSTATE_TYPE_SHIFT U(30)
102#define PSTATE_ID_MASK U(0xfffffff)
Soby Mathew981487a2015-07-13 14:10:57 +0100103#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700104#define PSTATE_VALID_MASK U(0xFCFE0000)
105#define PSTATE_TYPE_SHIFT U(16)
106#define PSTATE_PWR_LVL_SHIFT U(24)
107#define PSTATE_ID_MASK U(0xffff)
108#define PSTATE_PWR_LVL_MASK U(0x3)
Soby Mathew981487a2015-07-13 14:10:57 +0100109
110#define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \
111 PSTATE_PWR_LVL_MASK)
112#define psci_make_powerstate(state_id, type, pwrlvl) \
113 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\
114 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\
115 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT)
116#endif /* __PSCI_EXTENDED_STATE_ID__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700118#define PSTATE_TYPE_STANDBY U(0x0)
119#define PSTATE_TYPE_POWERDOWN U(0x1)
120#define PSTATE_TYPE_MASK U(0x1)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000121
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122/*******************************************************************************
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000123 * PSCI CPU_FEATURES feature flag specific defines
124 ******************************************************************************/
125/* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700126#define FF_PSTATE_SHIFT U(1)
127#define FF_PSTATE_ORIG U(0)
128#define FF_PSTATE_EXTENDED U(1)
Soby Mathew981487a2015-07-13 14:10:57 +0100129#if PSCI_EXTENDED_STATE_ID
130#define FF_PSTATE FF_PSTATE_EXTENDED
131#else
132#define FF_PSTATE FF_PSTATE_ORIG
133#endif
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000134
135/* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700136#define FF_MODE_SUPPORT_SHIFT U(0)
137#define FF_SUPPORTS_OS_INIT_MODE U(1)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000138
139/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140 * PSCI version
141 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700142#define PSCI_MAJOR_VER (U(1) << 16)
Roberto Vargasffb34d02017-09-11 09:11:58 +0100143#define PSCI_MINOR_VER U(0x1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
145/*******************************************************************************
146 * PSCI error codes
147 ******************************************************************************/
148#define PSCI_E_SUCCESS 0
149#define PSCI_E_NOT_SUPPORTED -1
150#define PSCI_E_INVALID_PARAMS -2
151#define PSCI_E_DENIED -3
152#define PSCI_E_ALREADY_ON -4
153#define PSCI_E_ON_PENDING -5
154#define PSCI_E_INTERN_FAIL -6
155#define PSCI_E_NOT_PRESENT -7
156#define PSCI_E_DISABLED -8
Soby Mathewf1f97a12015-07-15 12:13:26 +0100157#define PSCI_E_INVALID_ADDRESS -9
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158
Soby Mathew011ca182015-07-29 17:05:03 +0100159#define PSCI_INVALID_MPIDR ~((u_register_t)0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160
Roberto Vargasb820ad02017-07-26 09:23:09 +0100161/*
162 * SYSTEM_RESET2 macros
163 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100164#define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31)
165#define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
166#define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
167#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0))
Roberto Vargasb820ad02017-07-26 09:23:09 +0100168
Julius Werner53456fc2019-07-09 13:49:11 -0700169#ifndef __ASSEMBLER__
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170
Soby Mathew981487a2015-07-13 14:10:57 +0100171#include <stdint.h>
Soby Mathew981487a2015-07-13 14:10:57 +0100172
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100173/* Function to help build the psci capabilities bitfield */
174
175static inline unsigned int define_psci_cap(unsigned int x)
176{
177 return U(1) << (x & U(0x1f));
178}
179
180
181/* Power state helper functions */
182
183static inline unsigned int psci_get_pstate_id(unsigned int power_state)
184{
185 return ((power_state) >> PSTATE_ID_SHIFT) & PSTATE_ID_MASK;
186}
187
188static inline unsigned int psci_get_pstate_type(unsigned int power_state)
189{
190 return ((power_state) >> PSTATE_TYPE_SHIFT) & PSTATE_TYPE_MASK;
191}
192
193static inline unsigned int psci_check_power_state(unsigned int power_state)
194{
195 return ((power_state) & PSTATE_VALID_MASK);
196}
197
Soby Mathew981487a2015-07-13 14:10:57 +0100198/*
199 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified
200 * CPU. The definitions of these states can be found in Section 5.7.1 in the
201 * PSCI specification (ARM DEN 0022C).
202 */
203typedef enum {
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700204 AFF_STATE_ON = U(0),
205 AFF_STATE_OFF = U(1),
206 AFF_STATE_ON_PENDING = U(2)
Soby Mathew981487a2015-07-13 14:10:57 +0100207} aff_info_state_t;
208
209/*
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100210 * These are the power states reported by PSCI_NODE_HW_STATE API for the
211 * specified CPU. The definitions of these states can be found in Section 5.15.3
212 * of PSCI specification (ARM DEN 0022C).
213 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100214#define HW_ON 0
215#define HW_OFF 1
216#define HW_STANDBY 2
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100217
218/*
Soby Mathew981487a2015-07-13 14:10:57 +0100219 * Macro to represent invalid affinity level within PSCI.
220 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700221#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1))
Vikram Kanigirif100f412014-04-01 19:26:26 +0100222
Soby Mathew981487a2015-07-13 14:10:57 +0100223/*
224 * Type for representing the local power state at a particular level.
225 */
226typedef uint8_t plat_local_state_t;
227
228/* The local state macro used to represent RUN state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100229#define PSCI_LOCAL_STATE_RUN U(0)
Achin Gupta75f73672013-12-05 16:33:10 +0000230
Soby Mathew981487a2015-07-13 14:10:57 +0100231/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100232 * Function to test whether the plat_local_state is RUN state
Soby Mathew981487a2015-07-13 14:10:57 +0100233 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100234static inline int is_local_state_run(unsigned int plat_local_state)
235{
236 return (plat_local_state == PSCI_LOCAL_STATE_RUN) ? 1 : 0;
237}
Vikram Kanigirif100f412014-04-01 19:26:26 +0100238
Soby Mathew981487a2015-07-13 14:10:57 +0100239/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100240 * Function to test whether the plat_local_state is RETENTION state
Soby Mathew981487a2015-07-13 14:10:57 +0100241 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100242static inline int is_local_state_retn(unsigned int plat_local_state)
243{
244 return ((plat_local_state > PSCI_LOCAL_STATE_RUN) &&
245 (plat_local_state <= PLAT_MAX_RET_STATE)) ? 1 : 0;
246}
Vikram Kanigirif100f412014-04-01 19:26:26 +0100247
Soby Mathew981487a2015-07-13 14:10:57 +0100248/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100249 * Function to test whether the plat_local_state is OFF state
Soby Mathew981487a2015-07-13 14:10:57 +0100250 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100251static inline int is_local_state_off(unsigned int plat_local_state)
252{
253 return ((plat_local_state > PLAT_MAX_RET_STATE) &&
254 (plat_local_state <= PLAT_MAX_OFF_STATE)) ? 1 : 0;
255}
Dan Handley2bd4ef22014-04-09 13:14:54 +0100256
Soby Mathew981487a2015-07-13 14:10:57 +0100257/*****************************************************************************
258 * This data structure defines the representation of the power state parameter
259 * for its exchange between the generic PSCI code and the platform port. For
260 * example, it is used by the platform port to specify the requested power
261 * states during a power management operation. It is used by the generic code to
262 * inform the platform about the target power states that each level should
263 * enter.
264 ****************************************************************************/
265typedef struct psci_power_state {
266 /*
267 * The pwr_domain_state[] stores the local power state at each level
268 * for the CPU.
269 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700270 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)];
Soby Mathew981487a2015-07-13 14:10:57 +0100271} psci_power_state_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100272
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100273/*******************************************************************************
274 * Structure used to store per-cpu information relevant to the PSCI service.
275 * It is populated in the per-cpu data array. In return we get a guarantee that
276 * this information will not reside on a cache line shared with another cpu.
277 ******************************************************************************/
278typedef struct psci_cpu_data {
Soby Mathew981487a2015-07-13 14:10:57 +0100279 /* State as seen by PSCI Affinity Info API */
280 aff_info_state_t aff_info_state;
Soby Mathew011ca182015-07-29 17:05:03 +0100281
Soby Mathew981487a2015-07-13 14:10:57 +0100282 /*
283 * Highest power level which takes part in a power management
284 * operation.
285 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100286 unsigned int target_pwrlvl;
Soby Mathew011ca182015-07-29 17:05:03 +0100287
Soby Mathew981487a2015-07-13 14:10:57 +0100288 /* The local power state of this CPU */
289 plat_local_state_t local_state;
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100290} psci_cpu_data_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100291
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292/*******************************************************************************
293 * Structure populated by platform specific code to export routines which
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000294 * perform common low level power management functions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100296typedef struct plat_psci_ops {
297 void (*cpu_standby)(plat_local_state_t cpu_state);
298 int (*pwr_domain_on)(u_register_t mpidr);
299 void (*pwr_domain_off)(const psci_power_state_t *target_state);
Varun Wadekarae87f4b2017-07-10 16:02:05 -0700300 void (*pwr_domain_suspend_pwrdown_early)(
301 const psci_power_state_t *target_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100302 void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
303 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -0500304 void (*pwr_domain_on_finish_late)(
305 const psci_power_state_t *target_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100306 void (*pwr_domain_suspend_finish)(
307 const psci_power_state_t *target_state);
Yann Gautierbcf8ba22018-11-09 18:21:51 +0100308 void __dead2 (*pwr_domain_pwr_down_wfi)(
309 const psci_power_state_t *target_state);
310 void __dead2 (*system_off)(void);
311 void __dead2 (*system_reset)(void);
Soby Mathew981487a2015-07-13 14:10:57 +0100312 int (*validate_power_state)(unsigned int power_state,
313 psci_power_state_t *req_state);
Soby Mathew011ca182015-07-29 17:05:03 +0100314 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint);
Soby Mathew981487a2015-07-13 14:10:57 +0100315 void (*get_sys_suspend_power_state)(
316 psci_power_state_t *req_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100317 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
318 int pwrlvl);
319 int (*translate_power_state_by_mpidr)(u_register_t mpidr,
320 unsigned int power_state,
321 psci_power_state_t *output_state);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100322 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level);
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100323 int (*mem_protect_chk)(uintptr_t base, u_register_t length);
324 int (*read_mem_protect)(int *val);
325 int (*write_mem_protect)(int val);
Roberto Vargasb820ad02017-07-26 09:23:09 +0100326 int (*system_reset2)(int is_vendor,
327 int reset_type, u_register_t cookie);
Soby Mathew981487a2015-07-13 14:10:57 +0100328} plat_psci_ops_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100329
330/*******************************************************************************
331 * Function & Data prototypes
332 ******************************************************************************/
Dan Handleya17fefa2014-05-14 12:38:32 +0100333unsigned int psci_version(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100334int psci_cpu_on(u_register_t target_cpu,
335 uintptr_t entrypoint,
336 u_register_t context_id);
337int psci_cpu_suspend(unsigned int power_state,
338 uintptr_t entrypoint,
339 u_register_t context_id);
340int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id);
341int psci_cpu_off(void);
342int psci_affinity_info(u_register_t target_affinity,
343 unsigned int lowest_affinity_level);
344int psci_migrate(u_register_t target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100345int psci_migrate_info_type(void);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100346u_register_t psci_migrate_info_up_cpu(void);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100347int psci_node_hw_state(u_register_t target_cpu,
348 unsigned int power_level);
Soby Mathew011ca182015-07-29 17:05:03 +0100349int psci_features(unsigned int psci_fid);
Dan Handleya17fefa2014-05-14 12:38:32 +0100350void __dead2 psci_power_down_wfi(void);
Soby Mathewd0194872016-04-29 19:01:30 +0100351void psci_arch_setup(void);
352
Julius Werner53456fc2019-07-09 13:49:11 -0700353#endif /*__ASSEMBLER__*/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100354
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100355#endif /* PSCI_H */