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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew981487a2015-07-13 14:10:57 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PSCI_H__
32#define __PSCI_H__
33
Soby Mathew523d6332015-01-08 18:02:19 +000034#include <bakery_lock.h>
Soby Mathew981487a2015-07-13 14:10:57 +010035#include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */
36#if ENABLE_PLAT_COMPAT
37#include <psci_compat.h>
38#endif
Dan Handley2bd4ef22014-04-09 13:14:54 +010039
Achin Gupta4f6ad662013-10-25 09:08:21 +010040/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000041 * Number of power domains whose state this PSCI implementation can track
Soby Mathew523d6332015-01-08 18:02:19 +000042 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010043#ifdef PLAT_NUM_PWR_DOMAINS
44#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
Soby Mathew523d6332015-01-08 18:02:19 +000045#else
Soby Mathew981487a2015-07-13 14:10:57 +010046#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT)
Soby Mathew523d6332015-01-08 18:02:19 +000047#endif
48
Soby Mathew981487a2015-07-13 14:10:57 +010049#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \
50 PLATFORM_CORE_COUNT)
51
52/* This is the power level corresponding to a CPU */
53#define PSCI_CPU_PWR_LVL 0
54
55/*
56 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND
57 * uses the old power_state parameter format which has 2 bits to specify the
58 * power level, this constant is defined to be 3.
59 */
60#define PSCI_MAX_PWR_LVL 3
61
Soby Mathew523d6332015-01-08 18:02:19 +000062/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000063 * Defines for runtime services function ids
Achin Gupta4f6ad662013-10-25 09:08:21 +010064 ******************************************************************************/
65#define PSCI_VERSION 0x84000000
66#define PSCI_CPU_SUSPEND_AARCH32 0x84000001
67#define PSCI_CPU_SUSPEND_AARCH64 0xc4000001
68#define PSCI_CPU_OFF 0x84000002
69#define PSCI_CPU_ON_AARCH32 0x84000003
70#define PSCI_CPU_ON_AARCH64 0xc4000003
71#define PSCI_AFFINITY_INFO_AARCH32 0x84000004
72#define PSCI_AFFINITY_INFO_AARCH64 0xc4000004
73#define PSCI_MIG_AARCH32 0x84000005
74#define PSCI_MIG_AARCH64 0xc4000005
75#define PSCI_MIG_INFO_TYPE 0x84000006
76#define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007
77#define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000078#define PSCI_SYSTEM_OFF 0x84000008
Achin Gupta4f6ad662013-10-25 09:08:21 +010079#define PSCI_SYSTEM_RESET 0x84000009
Soby Mathew6cdddaf2015-01-07 11:10:22 +000080#define PSCI_FEATURES 0x8400000A
Soby Mathew96168382014-12-17 14:47:57 +000081#define PSCI_SYSTEM_SUSPEND_AARCH32 0x8400000E
82#define PSCI_SYSTEM_SUSPEND_AARCH64 0xc400000E
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010083#define PSCI_STAT_RESIDENCY_AARCH32 0x84000010
84#define PSCI_STAT_RESIDENCY_AARCH64 0xc4000010
85#define PSCI_STAT_COUNT_AARCH32 0x84000011
86#define PSCI_STAT_COUNT_AARCH64 0xc4000011
Soby Mathew6cdddaf2015-01-07 11:10:22 +000087
88/* Macro to help build the psci capabilities bitfield */
89#define define_psci_cap(x) (1 << (x & 0x1f))
Achin Gupta4f6ad662013-10-25 09:08:21 +010090
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000091/*
Juan Castillo4dc4a472014-08-12 11:17:06 +010092 * Number of PSCI calls (above) implemented
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000093 */
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010094#if ENABLE_PSCI_STAT
95#define PSCI_NUM_CALLS 22
96#else
Soby Mathew96168382014-12-17 14:47:57 +000097#define PSCI_NUM_CALLS 18
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010098#endif
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000099
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100/*******************************************************************************
101 * PSCI Migrate and friends
102 ******************************************************************************/
103#define PSCI_TOS_UP_MIG_CAP 0
104#define PSCI_TOS_NOT_UP_MIG_CAP 1
Achin Gupta607084e2014-02-09 18:24:19 +0000105#define PSCI_TOS_NOT_PRESENT_MP 2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106
107/*******************************************************************************
108 * PSCI CPU_SUSPEND 'power_state' parameter specific defines
109 ******************************************************************************/
Achin Gupta994dfce2013-10-26 13:10:31 +0100110#define PSTATE_ID_SHIFT 0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111
Soby Mathew981487a2015-07-13 14:10:57 +0100112#if PSCI_EXTENDED_STATE_ID
113#define PSTATE_VALID_MASK 0xB0000000
114#define PSTATE_TYPE_SHIFT 30
115#define PSTATE_ID_MASK 0xfffffff
116#else
117#define PSTATE_VALID_MASK 0xFCFE0000
118#define PSTATE_TYPE_SHIFT 16
119#define PSTATE_PWR_LVL_SHIFT 24
Achin Gupta4f6ad662013-10-25 09:08:21 +0100120#define PSTATE_ID_MASK 0xffff
Soby Mathew981487a2015-07-13 14:10:57 +0100121#define PSTATE_PWR_LVL_MASK 0x3
122
123#define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \
124 PSTATE_PWR_LVL_MASK)
125#define psci_make_powerstate(state_id, type, pwrlvl) \
126 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\
127 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\
128 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT)
129#endif /* __PSCI_EXTENDED_STATE_ID__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000131#define PSTATE_TYPE_STANDBY 0x0
132#define PSTATE_TYPE_POWERDOWN 0x1
Soby Mathew981487a2015-07-13 14:10:57 +0100133#define PSTATE_TYPE_MASK 0x1
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000134
Soby Mathew96168382014-12-17 14:47:57 +0000135#define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \
Soby Mathew74e52a72014-10-02 16:56:51 +0100136 PSTATE_ID_MASK)
Soby Mathew96168382014-12-17 14:47:57 +0000137#define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \
Soby Mathew74e52a72014-10-02 16:56:51 +0100138 PSTATE_TYPE_MASK)
Soby Mathew981487a2015-07-13 14:10:57 +0100139#define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140
141/*******************************************************************************
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000142 * PSCI CPU_FEATURES feature flag specific defines
143 ******************************************************************************/
144/* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */
145#define FF_PSTATE_SHIFT 1
146#define FF_PSTATE_ORIG 0
147#define FF_PSTATE_EXTENDED 1
Soby Mathew981487a2015-07-13 14:10:57 +0100148#if PSCI_EXTENDED_STATE_ID
149#define FF_PSTATE FF_PSTATE_EXTENDED
150#else
151#define FF_PSTATE FF_PSTATE_ORIG
152#endif
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000153
154/* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */
155#define FF_MODE_SUPPORT_SHIFT 0
156#define FF_SUPPORTS_OS_INIT_MODE 1
157
158/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159 * PSCI version
160 ******************************************************************************/
Soby Mathew1df077b2015-01-15 11:49:58 +0000161#define PSCI_MAJOR_VER (1 << 16)
162#define PSCI_MINOR_VER 0x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163
164/*******************************************************************************
165 * PSCI error codes
166 ******************************************************************************/
167#define PSCI_E_SUCCESS 0
168#define PSCI_E_NOT_SUPPORTED -1
169#define PSCI_E_INVALID_PARAMS -2
170#define PSCI_E_DENIED -3
171#define PSCI_E_ALREADY_ON -4
172#define PSCI_E_ON_PENDING -5
173#define PSCI_E_INTERN_FAIL -6
174#define PSCI_E_NOT_PRESENT -7
175#define PSCI_E_DISABLED -8
Soby Mathewf1f97a12015-07-15 12:13:26 +0100176#define PSCI_E_INVALID_ADDRESS -9
Achin Gupta4f6ad662013-10-25 09:08:21 +0100177
Soby Mathew011ca182015-07-29 17:05:03 +0100178#define PSCI_INVALID_MPIDR ~((u_register_t)0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179
Soby Mathew981487a2015-07-13 14:10:57 +0100180#ifndef __ASSEMBLY__
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181
Soby Mathew981487a2015-07-13 14:10:57 +0100182#include <stdint.h>
183#include <types.h>
184
185/*
186 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified
187 * CPU. The definitions of these states can be found in Section 5.7.1 in the
188 * PSCI specification (ARM DEN 0022C).
189 */
190typedef enum {
191 AFF_STATE_ON = 0,
192 AFF_STATE_OFF = 1,
193 AFF_STATE_ON_PENDING = 2
194} aff_info_state_t;
195
196/*
197 * Macro to represent invalid affinity level within PSCI.
198 */
Soby Mathew011ca182015-07-29 17:05:03 +0100199#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + 1)
Vikram Kanigirif100f412014-04-01 19:26:26 +0100200
Soby Mathew981487a2015-07-13 14:10:57 +0100201/*
202 * Type for representing the local power state at a particular level.
203 */
204typedef uint8_t plat_local_state_t;
205
206/* The local state macro used to represent RUN state. */
207#define PSCI_LOCAL_STATE_RUN 0
Achin Gupta75f73672013-12-05 16:33:10 +0000208
Soby Mathew981487a2015-07-13 14:10:57 +0100209/*
210 * Macro to test whether the plat_local_state is RUN state
211 */
212#define is_local_state_run(plat_local_state) \
213 ((plat_local_state) == PSCI_LOCAL_STATE_RUN)
Vikram Kanigirif100f412014-04-01 19:26:26 +0100214
Soby Mathew981487a2015-07-13 14:10:57 +0100215/*
216 * Macro to test whether the plat_local_state is RETENTION state
217 */
218#define is_local_state_retn(plat_local_state) \
219 (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \
220 ((plat_local_state) <= PLAT_MAX_RET_STATE))
Vikram Kanigirif100f412014-04-01 19:26:26 +0100221
Soby Mathew981487a2015-07-13 14:10:57 +0100222/*
223 * Macro to test whether the plat_local_state is OFF state
224 */
225#define is_local_state_off(plat_local_state) \
226 (((plat_local_state) > PLAT_MAX_RET_STATE) && \
227 ((plat_local_state) <= PLAT_MAX_OFF_STATE))
Dan Handley2bd4ef22014-04-09 13:14:54 +0100228
Soby Mathew981487a2015-07-13 14:10:57 +0100229/*****************************************************************************
230 * This data structure defines the representation of the power state parameter
231 * for its exchange between the generic PSCI code and the platform port. For
232 * example, it is used by the platform port to specify the requested power
233 * states during a power management operation. It is used by the generic code to
234 * inform the platform about the target power states that each level should
235 * enter.
236 ****************************************************************************/
237typedef struct psci_power_state {
238 /*
239 * The pwr_domain_state[] stores the local power state at each level
240 * for the CPU.
241 */
242 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1];
243} psci_power_state_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100244
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100245/*******************************************************************************
246 * Structure used to store per-cpu information relevant to the PSCI service.
247 * It is populated in the per-cpu data array. In return we get a guarantee that
248 * this information will not reside on a cache line shared with another cpu.
249 ******************************************************************************/
250typedef struct psci_cpu_data {
Soby Mathew981487a2015-07-13 14:10:57 +0100251 /* State as seen by PSCI Affinity Info API */
252 aff_info_state_t aff_info_state;
Soby Mathew011ca182015-07-29 17:05:03 +0100253
Soby Mathew981487a2015-07-13 14:10:57 +0100254 /*
255 * Highest power level which takes part in a power management
256 * operation.
257 */
Soby Mathew011ca182015-07-29 17:05:03 +0100258 unsigned char target_pwrlvl;
259
Soby Mathew981487a2015-07-13 14:10:57 +0100260 /* The local power state of this CPU */
261 plat_local_state_t local_state;
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100262} psci_cpu_data_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100263
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264/*******************************************************************************
265 * Structure populated by platform specific code to export routines which
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000266 * perform common low level power management functions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100267 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100268typedef struct plat_psci_ops {
269 void (*cpu_standby)(plat_local_state_t cpu_state);
270 int (*pwr_domain_on)(u_register_t mpidr);
271 void (*pwr_domain_off)(const psci_power_state_t *target_state);
272 void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
273 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
274 void (*pwr_domain_suspend_finish)(
275 const psci_power_state_t *target_state);
Soby Mathew6a816412016-04-27 14:46:28 +0100276 void (*pwr_domain_pwr_down_wfi)(
277 const psci_power_state_t *target_state) __dead2;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100278 void (*system_off)(void) __dead2;
279 void (*system_reset)(void) __dead2;
Soby Mathew981487a2015-07-13 14:10:57 +0100280 int (*validate_power_state)(unsigned int power_state,
281 psci_power_state_t *req_state);
Soby Mathew011ca182015-07-29 17:05:03 +0100282 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint);
Soby Mathew981487a2015-07-13 14:10:57 +0100283 void (*get_sys_suspend_power_state)(
284 psci_power_state_t *req_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100285 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
286 int pwrlvl);
287 int (*translate_power_state_by_mpidr)(u_register_t mpidr,
288 unsigned int power_state,
289 psci_power_state_t *output_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100290} plat_psci_ops_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100291
292/*******************************************************************************
Achin Gupta607084e2014-02-09 18:24:19 +0000293 * Optional structure populated by the Secure Payload Dispatcher to be given a
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000294 * chance to perform any bookkeeping before PSCI executes a power management
Achin Gupta607084e2014-02-09 18:24:19 +0000295 * operation. It also allows PSCI to determine certain properties of the SP e.g.
296 * migrate capability etc.
297 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100298typedef struct spd_pm_ops {
Achin Gupta607084e2014-02-09 18:24:19 +0000299 void (*svc_on)(uint64_t target_cpu);
300 int32_t (*svc_off)(uint64_t __unused);
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100301 void (*svc_suspend)(uint64_t max_off_pwrlvl);
Achin Gupta607084e2014-02-09 18:24:19 +0000302 void (*svc_on_finish)(uint64_t __unused);
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100303 void (*svc_suspend_finish)(uint64_t max_off_pwrlvl);
Soby Mathew110fe362014-10-23 10:35:34 +0100304 int32_t (*svc_migrate)(uint64_t from_cpu, uint64_t to_cpu);
305 int32_t (*svc_migrate_info)(uint64_t *resident_cpu);
Juan Castillo4dc4a472014-08-12 11:17:06 +0100306 void (*svc_system_off)(void);
307 void (*svc_system_reset)(void);
Dan Handleye2712bc2014-04-10 15:37:22 +0100308} spd_pm_ops_t;
Achin Gupta607084e2014-02-09 18:24:19 +0000309
310/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311 * Function & Data prototypes
312 ******************************************************************************/
Dan Handleya17fefa2014-05-14 12:38:32 +0100313unsigned int psci_version(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100314int psci_cpu_on(u_register_t target_cpu,
315 uintptr_t entrypoint,
316 u_register_t context_id);
317int psci_cpu_suspend(unsigned int power_state,
318 uintptr_t entrypoint,
319 u_register_t context_id);
320int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id);
321int psci_cpu_off(void);
322int psci_affinity_info(u_register_t target_affinity,
323 unsigned int lowest_affinity_level);
324int psci_migrate(u_register_t target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100325int psci_migrate_info_type(void);
326long psci_migrate_info_up_cpu(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100327int psci_features(unsigned int psci_fid);
Dan Handleya17fefa2014-05-14 12:38:32 +0100328void __dead2 psci_power_down_wfi(void);
Soby Mathew981487a2015-07-13 14:10:57 +0100329void psci_entrypoint(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100330void psci_register_spd_pm_hook(const spd_pm_ops_t *);
Dan Handleya17fefa2014-05-14 12:38:32 +0100331uint64_t psci_smc_handler(uint32_t smc_fid,
332 uint64_t x1,
333 uint64_t x2,
334 uint64_t x3,
335 uint64_t x4,
336 void *cookie,
337 void *handle,
338 uint64_t flags);
Dan Handley27f6e7d2014-04-23 15:22:18 +0100339
340/* PSCI setup function */
Soby Mathew011ca182015-07-29 17:05:03 +0100341int psci_setup(void);
Dan Handley27f6e7d2014-04-23 15:22:18 +0100342
Achin Gupta4f6ad662013-10-25 09:08:21 +0100343#endif /*__ASSEMBLY__*/
344
Achin Gupta4f6ad662013-10-25 09:08:21 +0100345#endif /* __PSCI_H__ */