Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <m0_param.h> |
| 32 | #include "rk3399_mcu.h" |
| 33 | |
| 34 | /* PMU */ |
| 35 | #define PMU_PWRDN_ST 0x18 |
| 36 | #define PMU_BUS_IDLE_REQ 0x60 |
| 37 | #define PMU_BUS_IDLE_ST 0x64 |
| 38 | #define PMU_NOC_AUTO_ENA 0xd8 |
| 39 | |
| 40 | /* PMU_BUS_IDLE_REQ */ |
| 41 | #define IDLE_REQ_MSCH1 (1 << 19) |
| 42 | #define IDLE_REQ_MSCH0 (1 << 18) |
| 43 | |
| 44 | /* #define PMU_BUS_IDLE_ST */ |
| 45 | #define IDLE_MSCH1 (1 << 19) |
| 46 | #define IDLE_MSCH0 (1 << 18) |
| 47 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 48 | /* CRU */ |
| 49 | #define CRU_DPLL_CON0 0x40 |
| 50 | #define CRU_DPLL_CON1 0x44 |
| 51 | #define CRU_DPLL_CON2 0x48 |
| 52 | #define CRU_DPLL_CON3 0x4c |
| 53 | #define CRU_DPLL_CON4 0x50 |
| 54 | #define CRU_DPLL_CON5 0x54 |
| 55 | |
| 56 | #define CRU_DPLL_CON2 0x48 |
| 57 | #define CRU_DPLL_CON3 0x4c |
| 58 | #define CRU_CLKGATE10_CON 0x328 |
| 59 | #define CRU_CLKGATE28_CON 0x370 |
| 60 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 61 | /* CRU_PLL_CON3 */ |
| 62 | #define PLL_SLOW_MODE 0 |
| 63 | #define PLL_NORMAL_MODE 1 |
| 64 | #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) |
| 65 | #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) |
| 66 | |
| 67 | /* PMU CRU */ |
| 68 | #define PMU_CRU_GATEDIS_CON0 0x130 |
| 69 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 70 | /* CIC */ |
| 71 | #define CIC_CTRL0 0 |
| 72 | #define CIC_CTRL1 0x4 |
| 73 | #define CIC_STATUS0 0x10 |
| 74 | |
Lin Huang | 2510366 | 2016-12-30 11:50:01 +0800 | [diff] [blame] | 75 | uint32_t gatedis_con0; |
| 76 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 77 | static void idle_port(void) |
| 78 | { |
Lin Huang | 2510366 | 2016-12-30 11:50:01 +0800 | [diff] [blame] | 79 | gatedis_con0 = mmio_read_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 80 | mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, 0x3fffffff); |
| 81 | mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, |
| 82 | IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1); |
| 83 | while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & |
| 84 | (IDLE_MSCH1 | IDLE_MSCH0)) != (IDLE_MSCH1 | IDLE_MSCH0)) |
| 85 | continue; |
| 86 | } |
| 87 | |
| 88 | static void deidle_port(void) |
| 89 | { |
| 90 | mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, |
| 91 | IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1); |
| 92 | while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & |
| 93 | (IDLE_MSCH1 | IDLE_MSCH0)) |
| 94 | continue; |
Lin Huang | 2510366 | 2016-12-30 11:50:01 +0800 | [diff] [blame] | 95 | |
| 96 | /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ |
| 97 | mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, gatedis_con0); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | static void ddr_set_pll(void) |
| 101 | { |
| 102 | mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); |
| 103 | |
| 104 | mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); |
| 105 | mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON0, |
| 106 | mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); |
| 107 | mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON1, |
| 108 | mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); |
| 109 | mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); |
| 110 | |
| 111 | while ((mmio_read_32(CRU_BASE_ADDR + CRU_DPLL_CON2) & (1u << 31)) == 0) |
| 112 | continue; |
| 113 | |
| 114 | mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); |
| 115 | } |
| 116 | |
| 117 | void handle_dram(void) |
| 118 | { |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 119 | idle_port(); |
| 120 | |
| 121 | mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0, |
| 122 | (((0x3 << 4) | (1 << 2) | 1) << 16) | |
| 123 | (1 << 2) | 1 | |
| 124 | mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); |
| 125 | while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 2)) == 0) |
| 126 | continue; |
| 127 | |
| 128 | ddr_set_pll(); |
| 129 | mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0, 0x20002); |
| 130 | while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 0)) == 0) |
| 131 | continue; |
| 132 | |
| 133 | deidle_port(); |
| 134 | } |