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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +01002 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <bl_common.h>
32#include <console.h>
33#include <debug.h>
34#include <platform_tsp.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -080035#include <plat_arm.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -080036#include "../zynqmp_private.h"
37
Soren Brinkmann76fcae32016-03-06 20:16:27 -080038#define BL32_END (unsigned long)(&__BL32_END__)
39
Soren Brinkmann76fcae32016-03-06 20:16:27 -080040/*******************************************************************************
41 * Initialize the UART
42 ******************************************************************************/
43void tsp_early_platform_setup(void)
44{
45 /*
46 * Initialize a different console than already in use to display
47 * messages from TSP
48 */
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070049 console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(),
Soren Brinkmann76fcae32016-03-06 20:16:27 -080050 ZYNQMP_UART_BAUDRATE);
51
52 /* Initialize the platform config for future decision making */
53 zynqmp_config_setup();
54}
55
56/*******************************************************************************
57 * Perform platform specific setup placeholder
58 ******************************************************************************/
59void tsp_platform_setup(void)
60{
61 plat_arm_gic_driver_init();
62 plat_arm_gic_init();
63}
64
65/*******************************************************************************
66 * Perform the very early platform specific architectural setup here. At the
67 * moment this is only intializes the MMU
68 ******************************************************************************/
69void tsp_plat_arch_setup(void)
70{
Soren Brinkmann6d1ba582016-07-08 14:45:14 -070071 arm_setup_page_tables(BL32_BASE,
72 BL32_END - BL32_BASE,
73 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +090074 BL_CODE_END,
Soren Brinkmann6d1ba582016-07-08 14:45:14 -070075 BL_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +090076 BL_RO_DATA_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090077 BL_COHERENT_RAM_BASE,
78 BL_COHERENT_RAM_END
Soren Brinkmann76fcae32016-03-06 20:16:27 -080079 );
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010080 enable_mmu_el1(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080081}