zynqmp: Separate code and rodata
Set the SEPARATE_CODE_AND_RODATA build flag to map read-only data as
execute never.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index ae66fa4..8e3ca62 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -35,19 +35,8 @@
#include <plat_arm.h>
#include "../zynqmp_private.h"
-/*
- * The next 3 constants identify the extents of the code & RO data region and
- * the limit of the BL32 image. These addresses are used by the MMU setup code
- * and therefore they must be page-aligned. It is the responsibility of the
- * linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__
- * linker symbols refer to page-aligned addresses.
- */
-#define BL32_RO_BASE (unsigned long)(&__RO_START__)
-#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL32_END (unsigned long)(&__BL32_END__)
-
-#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
@@ -57,7 +46,6 @@
*/
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
/*******************************************************************************
* Initialize the UART
@@ -90,16 +78,14 @@
******************************************************************************/
void tsp_plat_arch_setup(void)
{
- arm_setup_page_tables(BL32_RO_BASE,
- (BL32_END - BL32_RO_BASE),
- BL32_RO_BASE,
- BL32_RO_LIMIT,
- 0,
- 0
-#if USE_COHERENT_MEM
- , BL32_COHERENT_RAM_BASE,
+ arm_setup_page_tables(BL32_BASE,
+ BL32_END - BL32_BASE,
+ BL_CODE_BASE,
+ BL_CODE_LIMIT,
+ BL_RO_DATA_BASE,
+ BL_RO_DATA_LIMIT,
+ BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT
-#endif
);
enable_mmu_el1(0);
}