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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +01002 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <bl_common.h>
32#include <console.h>
33#include <debug.h>
34#include <platform_tsp.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -080035#include <plat_arm.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -080036#include "../zynqmp_private.h"
37
38/*
39 * The next 3 constants identify the extents of the code & RO data region and
40 * the limit of the BL32 image. These addresses are used by the MMU setup code
41 * and therefore they must be page-aligned. It is the responsibility of the
42 * linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__
43 * linker symbols refer to page-aligned addresses.
44 */
45#define BL32_RO_BASE (unsigned long)(&__RO_START__)
46#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
47#define BL32_END (unsigned long)(&__BL32_END__)
48
49
50#if USE_COHERENT_MEM
51/*
52 * The next 2 constants identify the extents of the coherent memory region.
53 * These addresses are used by the MMU setup code and therefore they must be
54 * page-aligned. It is the responsibility of the linker script to ensure that
55 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
56 * page-aligned addresses.
57 */
58#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
59#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
60#endif
61
62/*******************************************************************************
63 * Initialize the UART
64 ******************************************************************************/
65void tsp_early_platform_setup(void)
66{
67 /*
68 * Initialize a different console than already in use to display
69 * messages from TSP
70 */
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070071 console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(),
Soren Brinkmann76fcae32016-03-06 20:16:27 -080072 ZYNQMP_UART_BAUDRATE);
73
74 /* Initialize the platform config for future decision making */
75 zynqmp_config_setup();
76}
77
78/*******************************************************************************
79 * Perform platform specific setup placeholder
80 ******************************************************************************/
81void tsp_platform_setup(void)
82{
83 plat_arm_gic_driver_init();
84 plat_arm_gic_init();
85}
86
87/*******************************************************************************
88 * Perform the very early platform specific architectural setup here. At the
89 * moment this is only intializes the MMU
90 ******************************************************************************/
91void tsp_plat_arch_setup(void)
92{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010093 arm_setup_page_tables(BL32_RO_BASE,
Soren Brinkmann76fcae32016-03-06 20:16:27 -080094 (BL32_END - BL32_RO_BASE),
95 BL32_RO_BASE,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010096 BL32_RO_LIMIT,
97 0,
98 0
Soren Brinkmann76fcae32016-03-06 20:16:27 -080099#if USE_COHERENT_MEM
100 , BL32_COHERENT_RAM_BASE,
101 BL32_COHERENT_RAM_LIMIT
102#endif
103 );
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100104 enable_mmu_el1(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800105}