Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 31 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 32 | #include <assert.h> |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 33 | #include <bl_common.h> |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 34 | #include <context_mgmt.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 35 | #include <string.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 36 | #include "tspd_private.h" |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 37 | |
| 38 | /******************************************************************************* |
| 39 | * Given a secure payload entrypoint, register width, cpu id & pointer to a |
| 40 | * context data structure, this function will create a secure context ready for |
| 41 | * programming an entry into the secure payload. |
| 42 | ******************************************************************************/ |
| 43 | int32_t tspd_init_secure_context(uint64_t entrypoint, |
Achin Gupta | aeaab68 | 2014-05-09 13:21:31 +0100 | [diff] [blame] | 44 | uint32_t rw, |
| 45 | uint64_t mpidr, |
| 46 | tsp_context_t *tsp_ctx) |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 47 | { |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 48 | entry_point_info_t ep; |
| 49 | uint32_t ep_attr; |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 50 | |
| 51 | /* Passing a NULL context is a critical programming error */ |
| 52 | assert(tsp_ctx); |
| 53 | |
| 54 | /* |
| 55 | * We support AArch64 TSP for now. |
| 56 | * TODO: Add support for AArch32 TSP |
| 57 | */ |
| 58 | assert(rw == TSP_AARCH64); |
| 59 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 60 | /* Associate this context with the cpu specified */ |
| 61 | tsp_ctx->mpidr = mpidr; |
| 62 | tsp_ctx->state = 0; |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 63 | set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); |
Achin Gupta | 18d6eaf | 2014-05-04 18:23:26 +0100 | [diff] [blame] | 64 | clr_std_smc_active_flag(tsp_ctx->state); |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 65 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 66 | cm_set_context_by_mpidr(mpidr, &tsp_ctx->cpu_ctx, SECURE); |
| 67 | |
| 68 | /* initialise an entrypoint to set up the CPU context */ |
| 69 | ep_attr = SECURE | EP_ST_ENABLE; |
| 70 | if (read_sctlr_el3() & SCTLR_EE_BIT) |
| 71 | ep_attr |= EP_EE_BIG; |
| 72 | SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1, ep_attr); |
| 73 | ep.pc = entrypoint; |
| 74 | ep.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 75 | memset(&ep.args, 0, sizeof(ep.args)); |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 76 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 77 | cm_init_context(mpidr, &ep); |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 78 | |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | /******************************************************************************* |
| 83 | * This function takes an SP context pointer and: |
| 84 | * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx. |
| 85 | * 2. Saves the current C runtime state (callee saved registers) on the stack |
| 86 | * frame and saves a reference to this state. |
| 87 | * 3. Calls el3_exit() so that the EL3 system and general purpose registers |
| 88 | * from the tsp_ctx->cpu_ctx are used to enter the secure payload image. |
| 89 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 90 | uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx) |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 91 | { |
| 92 | uint64_t rc; |
| 93 | |
| 94 | assert(tsp_ctx->c_rt_ctx == 0); |
| 95 | |
| 96 | /* Apply the Secure EL1 system register context and switch to it */ |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 97 | assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 98 | cm_el1_sysregs_context_restore(SECURE); |
| 99 | cm_set_next_eret_context(SECURE); |
| 100 | |
| 101 | rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx); |
| 102 | #if DEBUG |
| 103 | tsp_ctx->c_rt_ctx = 0; |
| 104 | #endif |
| 105 | |
| 106 | return rc; |
| 107 | } |
| 108 | |
| 109 | |
| 110 | /******************************************************************************* |
| 111 | * This function takes an SP context pointer and: |
| 112 | * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx. |
| 113 | * 2. Restores the current C runtime state (callee saved registers) from the |
| 114 | * stack frame using the reference to this state saved in tspd_enter_sp(). |
| 115 | * 3. It does not need to save any general purpose or EL3 system register state |
| 116 | * as the generic smc entry routine should have saved those. |
| 117 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 118 | void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret) |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 119 | { |
| 120 | /* Save the Secure EL1 system register context */ |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 121 | assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); |
Achin Gupta | 375f538 | 2014-02-18 18:12:48 +0000 | [diff] [blame] | 122 | cm_el1_sysregs_context_save(SECURE); |
| 123 | |
| 124 | assert(tsp_ctx->c_rt_ctx != 0); |
| 125 | tspd_exit_sp(tsp_ctx->c_rt_ctx, ret); |
| 126 | |
| 127 | /* Should never reach here */ |
| 128 | assert(0); |
| 129 | } |