Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / fa3cf0bf903ad0d8320713870ca58410e1ab8758 / . / plat / mediatek / mt6795 / include / mcucfg.h
blob: c81de3320d8d05598e29198affa36da870729771 [file] [log] [blame]
developer550bf5e2016-07-11 16:05:23 +0800[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame^]4 * SPDX-License-Identifier: BSD-3-Clause
developer550bf5e2016-07-11 16:05:23 +0800[diff] [blame]5 */
6
7#ifndef __MCUCFG_H__
8#define __MCUCFG_H__
9
10#include <platform_def.h>
11#include <stdint.h>
12
13struct mt6795_mcucfg_regs {
14 uint32_t mp0_ca7l_cache_config;
15 struct {
16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
18 } mp0_cpu[4];
19 uint32_t mp0_cache_mem_delsel0;
20 uint32_t mp0_cache_mem_delsel1;
21 uint32_t mp0_axi_config;
22 uint32_t mp0_misc_config[2];
23 struct {
24 uint32_t rv_addr_lw;
25 uint32_t rv_addr_hw;
26 } mp0_rv_addr[4];
27 uint32_t mp0_ca7l_cfg_dis;
28 uint32_t mp0_ca7l_clken_ctrl;
29 uint32_t mp0_ca7l_rst_ctrl;
30 uint32_t mp0_ca7l_misc_config;
31 uint32_t mp0_ca7l_dbg_pwr_ctrl;
32 uint32_t mp0_rw_rsvd0;
33 uint32_t mp0_rw_rsvd1;
34 uint32_t mp0_ro_rsvd;
35 uint32_t reserved0_0[100];
36 uint32_t mp1_cpucfg;
37 uint32_t mp1_miscdbg;
38 uint32_t reserved0_1[13];
39 uint32_t mp1_rst_ctl;
40 uint32_t mp1_clkenm_div;
41 uint32_t reserved0_2[7];
42 uint32_t mp1_config_res;
43 uint32_t reserved0_3[13];
44 struct {
45 uint32_t rv_addr_lw;
46 uint32_t rv_addr_hw;
47 } mp1_rv_addr[2];
48 uint32_t reserved0_4[84];
49 uint32_t mp0_rst_status; /* 0x400 */
50 uint32_t mp0_dbg_ctrl;
51 uint32_t mp0_dbg_flag;
52 uint32_t mp0_ca7l_ir_mon;
53 struct {
54 uint32_t pc_lw;
55 uint32_t pc_hw;
56 uint32_t fp_arch32;
57 uint32_t sp_arch32;
58 uint32_t fp_arch64_lw;
59 uint32_t fp_arch64_hw;
60 uint32_t sp_arch64_lw;
61 uint32_t sp_arch64_hw;
62 } mp0_dbg_core[4];
63 uint32_t dfd_ctrl;
64 uint32_t dfd_cnt_l;
65 uint32_t dfd_cnt_h;
66 uint32_t misccfg_mp0_rw_rsvd;
67 uint32_t misccfg_sec_vio_status0;
68 uint32_t misccfg_sec_vio_status1;
69 uint32_t reserved1[22];
70 uint32_t misccfg_rw_rsvd; /* 0x500 */
71 uint32_t mcusys_dbg_mon_sel_a;
72 uint32_t mcusys_dbg_mon;
73 uint32_t reserved2[61];
74 uint32_t mcusys_config_a; /* 0x600 */
75 uint32_t mcusys_config1_a;
76 uint32_t mcusys_gic_peribase_a;
77 uint32_t reserved3;
78 uint32_t sec_range0_start; /* 0x610 */
79 uint32_t sec_range0_end;
80 uint32_t sec_range_enable;
81 uint32_t reserved4;
82 uint32_t int_pol_ctl[8]; /* 0x620 */
83 uint32_t aclken_div; /* 0x640 */
84 uint32_t pclken_div;
85 uint32_t l2c_sram_ctrl;
86 uint32_t armpll_jit_ctrl;
87 uint32_t cci_addrmap; /* 0x650 */
88 uint32_t cci_config;
89 uint32_t cci_periphbase;
90 uint32_t cci_nevntcntovfl;
91 uint32_t cci_clk_ctrl; /* 0x660 */
92 uint32_t cci_acel_s1_ctrl;
93 uint32_t bus_fabric_dcm_ctrl;
94 uint32_t reserved5;
95 uint32_t xgpt_ctl; /* 0x670 */
96 uint32_t xgpt_idx;
97 uint32_t ptpod2_ctl0;
98 uint32_t ptpod2_ctl1;
99 uint32_t mcusys_revid;
100 uint32_t mcusys_rw_rsvd0;
101 uint32_t mcusys_rw_rsvd1;
102};
103
104static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE;
105
106/* cpu boot mode */
107enum {
108 MP0_CPUCFG_64BIT_SHIFT = 12,
109 MP1_CPUCFG_64BIT_SHIFT = 28,
110 MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
111 MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
112};
113
114/* scu related */
115enum {
116 MP0_ACINACTM_SHIFT = 4,
117 MP1_ACINACTM_SHIFT = 0,
118 MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
119 MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT
120};
121
122enum {
123 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
124 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
125 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
126 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
127 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
128
129 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
130 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
131 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
132 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
133 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
134 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
135 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
136 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
137 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
138 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
139};
140
141enum {
142 MP1_AINACTS_SHIFT = 4,
143 MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
144};
145
146enum {
147 MP1_SW_CG_GEN_SHIFT = 12,
148 MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
149};
150
151enum {
152 MP1_L2RSTDISABLE_SHIFT = 14,
153 MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
154};
155
156#endif /* __MCUCFG_H__ */