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git01.mediatek.com / filogic / atf / 550bf5ea93dcf20ac733e7f067b2ef9ddddf1b23 / . / plat / mediatek / mt6795 / include / mcucfg.h
blob: 879e7fae989305791ba62174eb0a9361947fbcc5 [file] [log] [blame]
developer550bf5e2016-07-11 16:05:23 +0800[diff] [blame^]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __MCUCFG_H__
32#define __MCUCFG_H__
33
34#include <platform_def.h>
35#include <stdint.h>
36
37struct mt6795_mcucfg_regs {
38 uint32_t mp0_ca7l_cache_config;
39 struct {
40 uint32_t mem_delsel0;
41 uint32_t mem_delsel1;
42 } mp0_cpu[4];
43 uint32_t mp0_cache_mem_delsel0;
44 uint32_t mp0_cache_mem_delsel1;
45 uint32_t mp0_axi_config;
46 uint32_t mp0_misc_config[2];
47 struct {
48 uint32_t rv_addr_lw;
49 uint32_t rv_addr_hw;
50 } mp0_rv_addr[4];
51 uint32_t mp0_ca7l_cfg_dis;
52 uint32_t mp0_ca7l_clken_ctrl;
53 uint32_t mp0_ca7l_rst_ctrl;
54 uint32_t mp0_ca7l_misc_config;
55 uint32_t mp0_ca7l_dbg_pwr_ctrl;
56 uint32_t mp0_rw_rsvd0;
57 uint32_t mp0_rw_rsvd1;
58 uint32_t mp0_ro_rsvd;
59 uint32_t reserved0_0[100];
60 uint32_t mp1_cpucfg;
61 uint32_t mp1_miscdbg;
62 uint32_t reserved0_1[13];
63 uint32_t mp1_rst_ctl;
64 uint32_t mp1_clkenm_div;
65 uint32_t reserved0_2[7];
66 uint32_t mp1_config_res;
67 uint32_t reserved0_3[13];
68 struct {
69 uint32_t rv_addr_lw;
70 uint32_t rv_addr_hw;
71 } mp1_rv_addr[2];
72 uint32_t reserved0_4[84];
73 uint32_t mp0_rst_status; /* 0x400 */
74 uint32_t mp0_dbg_ctrl;
75 uint32_t mp0_dbg_flag;
76 uint32_t mp0_ca7l_ir_mon;
77 struct {
78 uint32_t pc_lw;
79 uint32_t pc_hw;
80 uint32_t fp_arch32;
81 uint32_t sp_arch32;
82 uint32_t fp_arch64_lw;
83 uint32_t fp_arch64_hw;
84 uint32_t sp_arch64_lw;
85 uint32_t sp_arch64_hw;
86 } mp0_dbg_core[4];
87 uint32_t dfd_ctrl;
88 uint32_t dfd_cnt_l;
89 uint32_t dfd_cnt_h;
90 uint32_t misccfg_mp0_rw_rsvd;
91 uint32_t misccfg_sec_vio_status0;
92 uint32_t misccfg_sec_vio_status1;
93 uint32_t reserved1[22];
94 uint32_t misccfg_rw_rsvd; /* 0x500 */
95 uint32_t mcusys_dbg_mon_sel_a;
96 uint32_t mcusys_dbg_mon;
97 uint32_t reserved2[61];
98 uint32_t mcusys_config_a; /* 0x600 */
99 uint32_t mcusys_config1_a;
100 uint32_t mcusys_gic_peribase_a;
101 uint32_t reserved3;
102 uint32_t sec_range0_start; /* 0x610 */
103 uint32_t sec_range0_end;
104 uint32_t sec_range_enable;
105 uint32_t reserved4;
106 uint32_t int_pol_ctl[8]; /* 0x620 */
107 uint32_t aclken_div; /* 0x640 */
108 uint32_t pclken_div;
109 uint32_t l2c_sram_ctrl;
110 uint32_t armpll_jit_ctrl;
111 uint32_t cci_addrmap; /* 0x650 */
112 uint32_t cci_config;
113 uint32_t cci_periphbase;
114 uint32_t cci_nevntcntovfl;
115 uint32_t cci_clk_ctrl; /* 0x660 */
116 uint32_t cci_acel_s1_ctrl;
117 uint32_t bus_fabric_dcm_ctrl;
118 uint32_t reserved5;
119 uint32_t xgpt_ctl; /* 0x670 */
120 uint32_t xgpt_idx;
121 uint32_t ptpod2_ctl0;
122 uint32_t ptpod2_ctl1;
123 uint32_t mcusys_revid;
124 uint32_t mcusys_rw_rsvd0;
125 uint32_t mcusys_rw_rsvd1;
126};
127
128static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE;
129
130/* cpu boot mode */
131enum {
132 MP0_CPUCFG_64BIT_SHIFT = 12,
133 MP1_CPUCFG_64BIT_SHIFT = 28,
134 MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
135 MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
136};
137
138/* scu related */
139enum {
140 MP0_ACINACTM_SHIFT = 4,
141 MP1_ACINACTM_SHIFT = 0,
142 MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
143 MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT
144};
145
146enum {
147 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
148 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
149 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
150 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
151 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
152
153 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
154 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
155 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
156 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
157 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
158 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
159 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
160 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
161 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
162 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
163};
164
165enum {
166 MP1_AINACTS_SHIFT = 4,
167 MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
168};
169
170enum {
171 MP1_SW_CG_GEN_SHIFT = 12,
172 MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
173};
174
175enum {
176 MP1_L2RSTDISABLE_SHIFT = 14,
177 MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
178};
179
180#endif /* __MCUCFG_H__ */