Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 1 | /* |
Norbert Werner | 6f98002 | 2020-01-19 14:51:01 +0100 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * ZynqMP system level PM-API functions for pin control. |
| 9 | */ |
| 10 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 11 | #include <string.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <arch_helpers.h> |
| 14 | #include <plat/common/platform.h> |
| 15 | |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 16 | #include "pm_api_pinctrl.h" |
| 17 | #include "pm_api_sys.h" |
| 18 | #include "pm_client.h" |
| 19 | #include "pm_common.h" |
| 20 | #include "pm_ipi.h" |
| 21 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 22 | struct pinctrl_function { |
| 23 | char name[FUNCTION_NAME_LEN]; |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 24 | uint16_t group_base; |
| 25 | uint8_t group_size; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 26 | uint8_t regval; |
| 27 | }; |
| 28 | |
| 29 | /* Max groups for one pin */ |
HariBabu Gattem | 6535f86 | 2022-09-22 02:45:16 -0700 | [diff] [blame] | 30 | #define MAX_PIN_GROUPS (13U) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 31 | |
| 32 | struct zynqmp_pin_group { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 33 | uint16_t (*groups)[]; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = { |
| 37 | [PINCTRL_FUNC_CAN0] = { |
| 38 | .name = "can0", |
| 39 | .regval = 0x20, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 40 | .group_base = PINCTRL_GRP_CAN0_0, |
| 41 | .group_size = PINCTRL_GRP_CAN0_18 - PINCTRL_GRP_CAN0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 42 | }, |
| 43 | [PINCTRL_FUNC_CAN1] = { |
| 44 | .name = "can1", |
| 45 | .regval = 0x20, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 46 | .group_base = PINCTRL_GRP_CAN1_0, |
| 47 | .group_size = PINCTRL_GRP_CAN1_19 - PINCTRL_GRP_CAN1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 48 | }, |
| 49 | [PINCTRL_FUNC_ETHERNET0] = { |
| 50 | .name = "ethernet0", |
| 51 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 52 | .group_base = PINCTRL_GRP_ETHERNET0_0, |
| 53 | .group_size = PINCTRL_GRP_ETHERNET0_0 - PINCTRL_GRP_ETHERNET0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 54 | }, |
| 55 | [PINCTRL_FUNC_ETHERNET1] = { |
| 56 | .name = "ethernet1", |
| 57 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 58 | .group_base = PINCTRL_GRP_ETHERNET1_0, |
| 59 | .group_size = PINCTRL_GRP_ETHERNET1_0 - PINCTRL_GRP_ETHERNET1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 60 | }, |
| 61 | [PINCTRL_FUNC_ETHERNET2] = { |
| 62 | .name = "ethernet2", |
| 63 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 64 | .group_base = PINCTRL_GRP_ETHERNET2_0, |
| 65 | .group_size = PINCTRL_GRP_ETHERNET2_0 - PINCTRL_GRP_ETHERNET2_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 66 | }, |
| 67 | [PINCTRL_FUNC_ETHERNET3] = { |
| 68 | .name = "ethernet3", |
| 69 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 70 | .group_base = PINCTRL_GRP_ETHERNET3_0, |
| 71 | .group_size = PINCTRL_GRP_ETHERNET3_0 - PINCTRL_GRP_ETHERNET3_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 72 | }, |
| 73 | [PINCTRL_FUNC_GEMTSU0] = { |
| 74 | .name = "gemtsu0", |
| 75 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 76 | .group_base = PINCTRL_GRP_GEMTSU0_0, |
| 77 | .group_size = PINCTRL_GRP_GEMTSU0_2 - PINCTRL_GRP_GEMTSU0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 78 | }, |
| 79 | [PINCTRL_FUNC_GPIO0] = { |
| 80 | .name = "gpio0", |
| 81 | .regval = 0x00, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 82 | .group_base = PINCTRL_GRP_GPIO0_0, |
| 83 | .group_size = PINCTRL_GRP_GPIO0_77 - PINCTRL_GRP_GPIO0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 84 | }, |
| 85 | [PINCTRL_FUNC_I2C0] = { |
| 86 | .name = "i2c0", |
| 87 | .regval = 0x40, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 88 | .group_base = PINCTRL_GRP_I2C0_0, |
| 89 | .group_size = PINCTRL_GRP_I2C0_18 - PINCTRL_GRP_I2C0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 90 | }, |
| 91 | [PINCTRL_FUNC_I2C1] = { |
| 92 | .name = "i2c1", |
| 93 | .regval = 0x40, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 94 | .group_base = PINCTRL_GRP_I2C1_0, |
| 95 | .group_size = PINCTRL_GRP_I2C1_19 - PINCTRL_GRP_I2C1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 96 | }, |
| 97 | [PINCTRL_FUNC_MDIO0] = { |
| 98 | .name = "mdio0", |
| 99 | .regval = 0x60, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 100 | .group_base = PINCTRL_GRP_MDIO0_0, |
| 101 | .group_size = PINCTRL_GRP_MDIO0_0 - PINCTRL_GRP_MDIO0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 102 | }, |
| 103 | [PINCTRL_FUNC_MDIO1] = { |
| 104 | .name = "mdio1", |
| 105 | .regval = 0x80, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 106 | .group_base = PINCTRL_GRP_MDIO1_0, |
| 107 | .group_size = PINCTRL_GRP_MDIO1_1 - PINCTRL_GRP_MDIO1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 108 | }, |
| 109 | [PINCTRL_FUNC_MDIO2] = { |
| 110 | .name = "mdio2", |
| 111 | .regval = 0xa0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 112 | .group_base = PINCTRL_GRP_MDIO2_0, |
| 113 | .group_size = PINCTRL_GRP_MDIO2_0 - PINCTRL_GRP_MDIO2_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 114 | }, |
| 115 | [PINCTRL_FUNC_MDIO3] = { |
| 116 | .name = "mdio3", |
| 117 | .regval = 0xc0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 118 | .group_base = PINCTRL_GRP_MDIO3_0, |
| 119 | .group_size = PINCTRL_GRP_MDIO3_0 - PINCTRL_GRP_MDIO3_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 120 | }, |
| 121 | [PINCTRL_FUNC_QSPI0] = { |
| 122 | .name = "qspi0", |
| 123 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 124 | .group_base = PINCTRL_GRP_QSPI0_0, |
| 125 | .group_size = PINCTRL_GRP_QSPI0_0 - PINCTRL_GRP_QSPI0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 126 | }, |
| 127 | [PINCTRL_FUNC_QSPI_FBCLK] = { |
| 128 | .name = "qspi_fbclk", |
| 129 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 130 | .group_base = PINCTRL_GRP_QSPI_FBCLK, |
| 131 | .group_size = PINCTRL_GRP_QSPI_FBCLK - PINCTRL_GRP_QSPI_FBCLK + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 132 | }, |
| 133 | [PINCTRL_FUNC_QSPI_SS] = { |
| 134 | .name = "qspi_ss", |
| 135 | .regval = 0x02, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 136 | .group_base = PINCTRL_GRP_QSPI_SS, |
| 137 | .group_size = PINCTRL_GRP_QSPI_SS - PINCTRL_GRP_QSPI_SS + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 138 | }, |
| 139 | [PINCTRL_FUNC_SPI0] = { |
| 140 | .name = "spi0", |
| 141 | .regval = 0x80, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 142 | .group_base = PINCTRL_GRP_SPI0_0, |
| 143 | .group_size = PINCTRL_GRP_SPI0_5 - PINCTRL_GRP_SPI0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 144 | }, |
| 145 | [PINCTRL_FUNC_SPI1] = { |
| 146 | .name = "spi1", |
| 147 | .regval = 0x80, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 148 | .group_base = PINCTRL_GRP_SPI1_0, |
| 149 | .group_size = PINCTRL_GRP_SPI1_5 - PINCTRL_GRP_SPI1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 150 | }, |
| 151 | [PINCTRL_FUNC_SPI0_SS] = { |
| 152 | .name = "spi0_ss", |
| 153 | .regval = 0x80, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 154 | .group_base = PINCTRL_GRP_SPI0_0_SS0, |
| 155 | .group_size = PINCTRL_GRP_SPI0_5_SS2 - PINCTRL_GRP_SPI0_0_SS0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 156 | }, |
| 157 | [PINCTRL_FUNC_SPI1_SS] = { |
| 158 | .name = "spi1_ss", |
| 159 | .regval = 0x80, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 160 | .group_base = PINCTRL_GRP_SPI1_0_SS0, |
| 161 | .group_size = PINCTRL_GRP_SPI1_5_SS2 - PINCTRL_GRP_SPI1_0_SS0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 162 | }, |
| 163 | [PINCTRL_FUNC_SDIO0] = { |
| 164 | .name = "sdio0", |
| 165 | .regval = 0x08, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 166 | .group_base = PINCTRL_GRP_SDIO0_0, |
| 167 | .group_size = PINCTRL_GRP_SDIO0_1BIT_2_7 - PINCTRL_GRP_SDIO0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 168 | }, |
| 169 | [PINCTRL_FUNC_SDIO0_PC] = { |
| 170 | .name = "sdio0_pc", |
| 171 | .regval = 0x08, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 172 | .group_base = PINCTRL_GRP_SDIO0_0_PC, |
| 173 | .group_size = PINCTRL_GRP_SDIO0_2_PC - PINCTRL_GRP_SDIO0_0_PC + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 174 | }, |
| 175 | [PINCTRL_FUNC_SDIO0_CD] = { |
| 176 | .name = "sdio0_cd", |
| 177 | .regval = 0x08, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 178 | .group_base = PINCTRL_GRP_SDIO0_0_CD, |
| 179 | .group_size = PINCTRL_GRP_SDIO0_2_CD - PINCTRL_GRP_SDIO0_0_CD + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 180 | }, |
| 181 | [PINCTRL_FUNC_SDIO0_WP] = { |
| 182 | .name = "sdio0_wp", |
| 183 | .regval = 0x08, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 184 | .group_base = PINCTRL_GRP_SDIO0_0_WP, |
| 185 | .group_size = PINCTRL_GRP_SDIO0_2_WP - PINCTRL_GRP_SDIO0_0_WP + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 186 | }, |
| 187 | [PINCTRL_FUNC_SDIO1] = { |
| 188 | .name = "sdio1", |
| 189 | .regval = 0x10, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 190 | .group_base = PINCTRL_GRP_SDIO1_0, |
| 191 | .group_size = PINCTRL_GRP_SDIO1_1BIT_1_3 - PINCTRL_GRP_SDIO1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 192 | }, |
| 193 | [PINCTRL_FUNC_SDIO1_PC] = { |
| 194 | .name = "sdio1_pc", |
| 195 | .regval = 0x10, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 196 | .group_base = PINCTRL_GRP_SDIO1_0_PC, |
| 197 | .group_size = PINCTRL_GRP_SDIO1_1_PC - PINCTRL_GRP_SDIO1_0_PC + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 198 | }, |
| 199 | [PINCTRL_FUNC_SDIO1_CD] = { |
| 200 | .name = "sdio1_cd", |
| 201 | .regval = 0x10, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 202 | .group_base = PINCTRL_GRP_SDIO1_0_CD, |
| 203 | .group_size = PINCTRL_GRP_SDIO1_1_CD - PINCTRL_GRP_SDIO1_0_CD + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 204 | }, |
| 205 | [PINCTRL_FUNC_SDIO1_WP] = { |
| 206 | .name = "sdio1_wp", |
| 207 | .regval = 0x10, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 208 | .group_base = PINCTRL_GRP_SDIO1_0_WP, |
| 209 | .group_size = PINCTRL_GRP_SDIO1_1_WP - PINCTRL_GRP_SDIO1_0_WP + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 210 | }, |
| 211 | [PINCTRL_FUNC_NAND0] = { |
| 212 | .name = "nand0", |
| 213 | .regval = 0x04, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 214 | .group_base = PINCTRL_GRP_NAND0_0, |
| 215 | .group_size = PINCTRL_GRP_NAND0_0 - PINCTRL_GRP_NAND0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 216 | }, |
| 217 | [PINCTRL_FUNC_NAND0_CE] = { |
| 218 | .name = "nand0_ce", |
| 219 | .regval = 0x04, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 220 | .group_base = PINCTRL_GRP_NAND0_0_CE, |
| 221 | .group_size = PINCTRL_GRP_NAND0_1_CE - PINCTRL_GRP_NAND0_0_CE + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 222 | }, |
| 223 | [PINCTRL_FUNC_NAND0_RB] = { |
| 224 | .name = "nand0_rb", |
| 225 | .regval = 0x04, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 226 | .group_base = PINCTRL_GRP_NAND0_0_RB, |
| 227 | .group_size = PINCTRL_GRP_NAND0_1_RB - PINCTRL_GRP_NAND0_0_RB + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 228 | }, |
| 229 | [PINCTRL_FUNC_NAND0_DQS] = { |
| 230 | .name = "nand0_dqs", |
| 231 | .regval = 0x04, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 232 | .group_base = PINCTRL_GRP_NAND0_0_DQS, |
| 233 | .group_size = PINCTRL_GRP_NAND0_1_DQS - PINCTRL_GRP_NAND0_0_DQS + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 234 | }, |
| 235 | [PINCTRL_FUNC_TTC0_CLK] = { |
| 236 | .name = "ttc0_clk", |
| 237 | .regval = 0xa0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 238 | .group_base = PINCTRL_GRP_TTC0_0_CLK, |
| 239 | .group_size = PINCTRL_GRP_TTC0_8_CLK - PINCTRL_GRP_TTC0_0_CLK + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 240 | }, |
| 241 | [PINCTRL_FUNC_TTC0_WAV] = { |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 242 | .name = "ttc0_wav", |
| 243 | .regval = 0xa0, |
| 244 | .group_base = PINCTRL_GRP_TTC0_0_WAV, |
| 245 | .group_size = PINCTRL_GRP_TTC0_8_WAV - PINCTRL_GRP_TTC0_0_WAV + 1U, |
| 246 | }, |
| 247 | [PINCTRL_FUNC_TTC1_CLK] = { |
| 248 | .name = "ttc1_clk", |
| 249 | .regval = 0xa0, |
| 250 | .group_base = PINCTRL_GRP_TTC1_0_CLK, |
| 251 | .group_size = PINCTRL_GRP_TTC1_8_CLK - PINCTRL_GRP_TTC1_0_CLK + 1U, |
| 252 | }, |
| 253 | [PINCTRL_FUNC_TTC1_WAV] = { |
| 254 | .name = "ttc1_wav", |
| 255 | .regval = 0xa0, |
| 256 | .group_base = PINCTRL_GRP_TTC1_0_WAV, |
| 257 | .group_size = PINCTRL_GRP_TTC1_8_WAV - PINCTRL_GRP_TTC1_0_WAV + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 258 | }, |
| 259 | [PINCTRL_FUNC_TTC2_CLK] = { |
| 260 | .name = "ttc2_clk", |
| 261 | .regval = 0xa0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 262 | .group_base = PINCTRL_GRP_TTC2_0_CLK, |
| 263 | .group_size = PINCTRL_GRP_TTC2_8_CLK - PINCTRL_GRP_TTC2_0_CLK + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 264 | }, |
| 265 | [PINCTRL_FUNC_TTC2_WAV] = { |
| 266 | .name = "ttc2_wav", |
| 267 | .regval = 0xa0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 268 | .group_base = PINCTRL_GRP_TTC2_0_WAV, |
| 269 | .group_size = PINCTRL_GRP_TTC2_8_WAV - PINCTRL_GRP_TTC2_0_WAV + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 270 | }, |
| 271 | [PINCTRL_FUNC_TTC3_CLK] = { |
| 272 | .name = "ttc3_clk", |
| 273 | .regval = 0xa0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 274 | .group_base = PINCTRL_GRP_TTC3_0_CLK, |
| 275 | .group_size = PINCTRL_GRP_TTC3_8_CLK - PINCTRL_GRP_TTC3_0_CLK + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 276 | }, |
| 277 | [PINCTRL_FUNC_TTC3_WAV] = { |
| 278 | .name = "ttc3_wav", |
| 279 | .regval = 0xa0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 280 | .group_base = PINCTRL_GRP_TTC3_0_WAV, |
| 281 | .group_size = PINCTRL_GRP_TTC3_8_WAV - PINCTRL_GRP_TTC3_0_WAV + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 282 | }, |
| 283 | [PINCTRL_FUNC_UART0] = { |
| 284 | .name = "uart0", |
| 285 | .regval = 0xc0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 286 | .group_base = PINCTRL_GRP_UART0_0, |
| 287 | .group_size = PINCTRL_GRP_UART0_18 - PINCTRL_GRP_UART0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 288 | }, |
| 289 | [PINCTRL_FUNC_UART1] = { |
| 290 | .name = "uart1", |
| 291 | .regval = 0xc0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 292 | .group_base = PINCTRL_GRP_UART1_0, |
| 293 | .group_size = PINCTRL_GRP_UART1_18 - PINCTRL_GRP_UART1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 294 | }, |
| 295 | [PINCTRL_FUNC_USB0] = { |
| 296 | .name = "usb0", |
| 297 | .regval = 0x04, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 298 | .group_base = PINCTRL_GRP_USB0_0, |
| 299 | .group_size = PINCTRL_GRP_USB0_0 - PINCTRL_GRP_USB0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 300 | }, |
| 301 | [PINCTRL_FUNC_USB1] = { |
| 302 | .name = "usb1", |
| 303 | .regval = 0x04, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 304 | .group_base = PINCTRL_GRP_USB1_0, |
| 305 | .group_size = PINCTRL_GRP_USB1_0 - PINCTRL_GRP_USB1_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 306 | }, |
| 307 | [PINCTRL_FUNC_SWDT0_CLK] = { |
| 308 | .name = "swdt0_clk", |
| 309 | .regval = 0x60, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 310 | .group_base = PINCTRL_GRP_SWDT0_0_CLK, |
| 311 | .group_size = PINCTRL_GRP_SWDT0_12_CLK - PINCTRL_GRP_SWDT0_0_CLK + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 312 | }, |
| 313 | [PINCTRL_FUNC_SWDT0_RST] = { |
| 314 | .name = "swdt0_rst", |
| 315 | .regval = 0x60, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 316 | .group_base = PINCTRL_GRP_SWDT0_0_RST, |
| 317 | .group_size = PINCTRL_GRP_SWDT0_12_RST - PINCTRL_GRP_SWDT0_0_RST + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 318 | }, |
| 319 | [PINCTRL_FUNC_SWDT1_CLK] = { |
| 320 | .name = "swdt1_clk", |
| 321 | .regval = 0x60, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 322 | .group_base = PINCTRL_GRP_SWDT1_0_CLK, |
| 323 | .group_size = PINCTRL_GRP_SWDT1_12_CLK - PINCTRL_GRP_SWDT1_0_CLK + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 324 | }, |
| 325 | [PINCTRL_FUNC_SWDT1_RST] = { |
| 326 | .name = "swdt1_rst", |
| 327 | .regval = 0x60, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 328 | .group_base = PINCTRL_GRP_SWDT1_0_RST, |
| 329 | .group_size = PINCTRL_GRP_SWDT1_12_RST - PINCTRL_GRP_SWDT1_0_RST + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 330 | }, |
| 331 | [PINCTRL_FUNC_PMU0] = { |
| 332 | .name = "pmu0", |
| 333 | .regval = 0x08, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 334 | .group_base = PINCTRL_GRP_PMU0_0, |
| 335 | .group_size = PINCTRL_GRP_PMU0_11 - PINCTRL_GRP_PMU0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 336 | }, |
| 337 | [PINCTRL_FUNC_PCIE0] = { |
| 338 | .name = "pcie0", |
| 339 | .regval = 0x04, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 340 | .group_base = PINCTRL_GRP_PCIE0_0, |
| 341 | .group_size = PINCTRL_GRP_PCIE0_7 - PINCTRL_GRP_PCIE0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 342 | }, |
| 343 | [PINCTRL_FUNC_CSU0] = { |
| 344 | .name = "csu0", |
| 345 | .regval = 0x18, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 346 | .group_base = PINCTRL_GRP_CSU0_0, |
| 347 | .group_size = PINCTRL_GRP_CSU0_11 - PINCTRL_GRP_CSU0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 348 | }, |
| 349 | [PINCTRL_FUNC_DPAUX0] = { |
| 350 | .name = "dpaux0", |
| 351 | .regval = 0x18, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 352 | .group_base = PINCTRL_GRP_DPAUX0_0, |
| 353 | .group_size = PINCTRL_GRP_DPAUX0_3 - PINCTRL_GRP_DPAUX0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 354 | }, |
| 355 | [PINCTRL_FUNC_PJTAG0] = { |
| 356 | .name = "pjtag0", |
| 357 | .regval = 0x60, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 358 | .group_base = PINCTRL_GRP_PJTAG0_0, |
| 359 | .group_size = PINCTRL_GRP_PJTAG0_5 - PINCTRL_GRP_PJTAG0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 360 | }, |
| 361 | [PINCTRL_FUNC_TRACE0] = { |
| 362 | .name = "trace0", |
| 363 | .regval = 0xe0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 364 | .group_base = PINCTRL_GRP_TRACE0_0, |
| 365 | .group_size = PINCTRL_GRP_TRACE0_2 - PINCTRL_GRP_TRACE0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 366 | }, |
| 367 | [PINCTRL_FUNC_TRACE0_CLK] = { |
| 368 | .name = "trace0_clk", |
| 369 | .regval = 0xe0, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 370 | .group_base = PINCTRL_GRP_TRACE0_0_CLK, |
| 371 | .group_size = PINCTRL_GRP_TRACE0_2_CLK - PINCTRL_GRP_TRACE0_0_CLK + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 372 | }, |
| 373 | [PINCTRL_FUNC_TESTSCAN0] = { |
| 374 | .name = "testscan0", |
| 375 | .regval = 0x10, |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 376 | .group_base = PINCTRL_GRP_TESTSCAN0_0, |
| 377 | .group_size = PINCTRL_GRP_TESTSCAN0_0 - PINCTRL_GRP_TESTSCAN0_0 + 1U, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 378 | }, |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 379 | }; |
| 380 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 381 | static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { |
| 382 | [PINCTRL_PIN_0] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 383 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 384 | PINCTRL_GRP_QSPI0_0, |
| 385 | PINCTRL_GRP_RESERVED, |
| 386 | PINCTRL_GRP_RESERVED, |
| 387 | PINCTRL_GRP_TESTSCAN0_0, |
| 388 | PINCTRL_GRP_RESERVED, |
| 389 | PINCTRL_GRP_GPIO0_0, |
| 390 | PINCTRL_GRP_CAN1_0, |
| 391 | PINCTRL_GRP_I2C1_0, |
| 392 | PINCTRL_GRP_PJTAG0_0, |
| 393 | PINCTRL_GRP_SPI0_0, |
| 394 | PINCTRL_GRP_TTC3_0_CLK, |
| 395 | PINCTRL_GRP_UART1_0, |
| 396 | PINCTRL_GRP_TRACE0_0_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 397 | END_OF_GROUPS, |
| 398 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 399 | }, |
| 400 | [PINCTRL_PIN_1] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 401 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 402 | PINCTRL_GRP_QSPI0_0, |
| 403 | PINCTRL_GRP_RESERVED, |
| 404 | PINCTRL_GRP_RESERVED, |
| 405 | PINCTRL_GRP_TESTSCAN0_0, |
| 406 | PINCTRL_GRP_RESERVED, |
| 407 | PINCTRL_GRP_GPIO0_1, |
| 408 | PINCTRL_GRP_CAN1_0, |
| 409 | PINCTRL_GRP_I2C1_0, |
| 410 | PINCTRL_GRP_PJTAG0_0, |
| 411 | PINCTRL_GRP_SPI0_0_SS2, |
| 412 | PINCTRL_GRP_TTC3_0_WAV, |
| 413 | PINCTRL_GRP_UART1_0, |
| 414 | PINCTRL_GRP_TRACE0_0_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 415 | END_OF_GROUPS, |
| 416 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 417 | }, |
| 418 | [PINCTRL_PIN_2] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 419 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 420 | PINCTRL_GRP_QSPI0_0, |
| 421 | PINCTRL_GRP_RESERVED, |
| 422 | PINCTRL_GRP_RESERVED, |
| 423 | PINCTRL_GRP_TESTSCAN0_0, |
| 424 | PINCTRL_GRP_RESERVED, |
| 425 | PINCTRL_GRP_GPIO0_2, |
| 426 | PINCTRL_GRP_CAN0_0, |
| 427 | PINCTRL_GRP_I2C0_0, |
| 428 | PINCTRL_GRP_PJTAG0_0, |
| 429 | PINCTRL_GRP_SPI0_0_SS1, |
| 430 | PINCTRL_GRP_TTC2_0_CLK, |
| 431 | PINCTRL_GRP_UART0_0, |
| 432 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 433 | END_OF_GROUPS, |
| 434 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 435 | }, |
| 436 | [PINCTRL_PIN_3] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 437 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 438 | PINCTRL_GRP_QSPI0_0, |
| 439 | PINCTRL_GRP_RESERVED, |
| 440 | PINCTRL_GRP_RESERVED, |
| 441 | PINCTRL_GRP_TESTSCAN0_0, |
| 442 | PINCTRL_GRP_RESERVED, |
| 443 | PINCTRL_GRP_GPIO0_3, |
| 444 | PINCTRL_GRP_CAN0_0, |
| 445 | PINCTRL_GRP_I2C0_0, |
| 446 | PINCTRL_GRP_PJTAG0_0, |
| 447 | PINCTRL_GRP_SPI0_0_SS0, |
| 448 | PINCTRL_GRP_TTC2_0_WAV, |
| 449 | PINCTRL_GRP_UART0_0, |
| 450 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 451 | END_OF_GROUPS, |
| 452 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 453 | }, |
| 454 | [PINCTRL_PIN_4] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 455 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 456 | PINCTRL_GRP_QSPI0_0, |
| 457 | PINCTRL_GRP_RESERVED, |
| 458 | PINCTRL_GRP_RESERVED, |
| 459 | PINCTRL_GRP_TESTSCAN0_0, |
| 460 | PINCTRL_GRP_RESERVED, |
| 461 | PINCTRL_GRP_GPIO0_4, |
| 462 | PINCTRL_GRP_CAN1_1, |
| 463 | PINCTRL_GRP_I2C1_1, |
| 464 | PINCTRL_GRP_SWDT1_0_CLK, |
| 465 | PINCTRL_GRP_SPI0_0, |
| 466 | PINCTRL_GRP_TTC1_0_CLK, |
| 467 | PINCTRL_GRP_UART1_1, |
| 468 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 469 | END_OF_GROUPS, |
| 470 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 471 | }, |
| 472 | [PINCTRL_PIN_5] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 473 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 474 | PINCTRL_GRP_QSPI_SS, |
| 475 | PINCTRL_GRP_RESERVED, |
| 476 | PINCTRL_GRP_RESERVED, |
| 477 | PINCTRL_GRP_TESTSCAN0_0, |
| 478 | PINCTRL_GRP_RESERVED, |
| 479 | PINCTRL_GRP_GPIO0_5, |
| 480 | PINCTRL_GRP_CAN1_1, |
| 481 | PINCTRL_GRP_I2C1_1, |
| 482 | PINCTRL_GRP_SWDT1_0_RST, |
| 483 | PINCTRL_GRP_SPI0_0, |
| 484 | PINCTRL_GRP_TTC1_0_WAV, |
| 485 | PINCTRL_GRP_UART1_1, |
| 486 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 487 | END_OF_GROUPS, |
| 488 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 489 | }, |
| 490 | [PINCTRL_PIN_6] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 491 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 492 | PINCTRL_GRP_QSPI_FBCLK, |
| 493 | PINCTRL_GRP_RESERVED, |
| 494 | PINCTRL_GRP_RESERVED, |
| 495 | PINCTRL_GRP_TESTSCAN0_0, |
| 496 | PINCTRL_GRP_RESERVED, |
| 497 | PINCTRL_GRP_GPIO0_6, |
| 498 | PINCTRL_GRP_CAN0_1, |
| 499 | PINCTRL_GRP_I2C0_1, |
| 500 | PINCTRL_GRP_SWDT0_0_CLK, |
| 501 | PINCTRL_GRP_SPI1_0, |
| 502 | PINCTRL_GRP_TTC0_0_CLK, |
| 503 | PINCTRL_GRP_UART0_1, |
| 504 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 505 | END_OF_GROUPS, |
| 506 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 507 | }, |
| 508 | [PINCTRL_PIN_7] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 509 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 510 | PINCTRL_GRP_QSPI_SS, |
| 511 | PINCTRL_GRP_RESERVED, |
| 512 | PINCTRL_GRP_RESERVED, |
| 513 | PINCTRL_GRP_TESTSCAN0_0, |
| 514 | PINCTRL_GRP_RESERVED, |
| 515 | PINCTRL_GRP_GPIO0_7, |
| 516 | PINCTRL_GRP_CAN0_1, |
| 517 | PINCTRL_GRP_I2C0_1, |
| 518 | PINCTRL_GRP_SWDT0_0_RST, |
| 519 | PINCTRL_GRP_SPI1_0_SS2, |
| 520 | PINCTRL_GRP_TTC0_0_WAV, |
| 521 | PINCTRL_GRP_UART0_1, |
| 522 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 523 | END_OF_GROUPS, |
| 524 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 525 | }, |
| 526 | [PINCTRL_PIN_8] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 527 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 528 | PINCTRL_GRP_QSPI0_0, |
| 529 | PINCTRL_GRP_RESERVED, |
| 530 | PINCTRL_GRP_RESERVED, |
| 531 | PINCTRL_GRP_TESTSCAN0_0, |
| 532 | PINCTRL_GRP_RESERVED, |
| 533 | PINCTRL_GRP_GPIO0_8, |
| 534 | PINCTRL_GRP_CAN1_2, |
| 535 | PINCTRL_GRP_I2C1_2, |
| 536 | PINCTRL_GRP_SWDT1_1_CLK, |
| 537 | PINCTRL_GRP_SPI1_0_SS1, |
| 538 | PINCTRL_GRP_TTC3_1_CLK, |
| 539 | PINCTRL_GRP_UART1_2, |
| 540 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 541 | END_OF_GROUPS, |
| 542 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 543 | }, |
| 544 | [PINCTRL_PIN_9] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 545 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 546 | PINCTRL_GRP_QSPI0_0, |
| 547 | PINCTRL_GRP_NAND0_0_CE, |
| 548 | PINCTRL_GRP_RESERVED, |
| 549 | PINCTRL_GRP_TESTSCAN0_0, |
| 550 | PINCTRL_GRP_RESERVED, |
| 551 | PINCTRL_GRP_GPIO0_9, |
| 552 | PINCTRL_GRP_CAN1_2, |
| 553 | PINCTRL_GRP_I2C1_2, |
| 554 | PINCTRL_GRP_SWDT1_1_RST, |
| 555 | PINCTRL_GRP_SPI1_0_SS0, |
| 556 | PINCTRL_GRP_TTC3_1_WAV, |
| 557 | PINCTRL_GRP_UART1_2, |
| 558 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 559 | END_OF_GROUPS, |
| 560 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 561 | }, |
| 562 | [PINCTRL_PIN_10] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 563 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 564 | PINCTRL_GRP_QSPI0_0, |
| 565 | PINCTRL_GRP_NAND0_0_RB, |
| 566 | PINCTRL_GRP_RESERVED, |
| 567 | PINCTRL_GRP_TESTSCAN0_0, |
| 568 | PINCTRL_GRP_RESERVED, |
| 569 | PINCTRL_GRP_GPIO0_10, |
| 570 | PINCTRL_GRP_CAN0_2, |
| 571 | PINCTRL_GRP_I2C0_2, |
| 572 | PINCTRL_GRP_SWDT0_1_CLK, |
| 573 | PINCTRL_GRP_SPI1_0, |
| 574 | PINCTRL_GRP_TTC2_1_CLK, |
| 575 | PINCTRL_GRP_UART0_2, |
| 576 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 577 | END_OF_GROUPS, |
| 578 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 579 | }, |
| 580 | [PINCTRL_PIN_11] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 581 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 582 | PINCTRL_GRP_QSPI0_0, |
| 583 | PINCTRL_GRP_NAND0_0_RB, |
| 584 | PINCTRL_GRP_RESERVED, |
| 585 | PINCTRL_GRP_TESTSCAN0_0, |
| 586 | PINCTRL_GRP_RESERVED, |
| 587 | PINCTRL_GRP_GPIO0_11, |
| 588 | PINCTRL_GRP_CAN0_2, |
| 589 | PINCTRL_GRP_I2C0_2, |
| 590 | PINCTRL_GRP_SWDT0_1_RST, |
| 591 | PINCTRL_GRP_SPI1_0, |
| 592 | PINCTRL_GRP_TTC2_1_WAV, |
| 593 | PINCTRL_GRP_UART0_2, |
| 594 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 595 | END_OF_GROUPS, |
| 596 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 597 | }, |
| 598 | [PINCTRL_PIN_12] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 599 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 600 | PINCTRL_GRP_QSPI0_0, |
| 601 | PINCTRL_GRP_NAND0_0_DQS, |
| 602 | PINCTRL_GRP_RESERVED, |
| 603 | PINCTRL_GRP_TESTSCAN0_0, |
| 604 | PINCTRL_GRP_RESERVED, |
| 605 | PINCTRL_GRP_GPIO0_12, |
| 606 | PINCTRL_GRP_CAN1_3, |
| 607 | PINCTRL_GRP_I2C1_3, |
| 608 | PINCTRL_GRP_PJTAG0_1, |
| 609 | PINCTRL_GRP_SPI0_1, |
| 610 | PINCTRL_GRP_TTC1_1_CLK, |
| 611 | PINCTRL_GRP_UART1_3, |
| 612 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 613 | END_OF_GROUPS, |
| 614 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 615 | }, |
| 616 | [PINCTRL_PIN_13] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 617 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 618 | PINCTRL_GRP_RESERVED, |
| 619 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 620 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 621 | PINCTRL_GRP_TESTSCAN0_0, |
| 622 | PINCTRL_GRP_RESERVED, |
| 623 | PINCTRL_GRP_GPIO0_13, |
| 624 | PINCTRL_GRP_CAN1_3, |
| 625 | PINCTRL_GRP_I2C1_3, |
| 626 | PINCTRL_GRP_PJTAG0_1, |
| 627 | PINCTRL_GRP_SPI0_1_SS2, |
| 628 | PINCTRL_GRP_TTC1_1_WAV, |
| 629 | PINCTRL_GRP_UART1_3, |
| 630 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 631 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 632 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 633 | END_OF_GROUPS, |
| 634 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 635 | }, |
| 636 | [PINCTRL_PIN_14] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 637 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 638 | PINCTRL_GRP_RESERVED, |
| 639 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 640 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 641 | PINCTRL_GRP_TESTSCAN0_0, |
| 642 | PINCTRL_GRP_RESERVED, |
| 643 | PINCTRL_GRP_GPIO0_14, |
| 644 | PINCTRL_GRP_CAN0_3, |
| 645 | PINCTRL_GRP_I2C0_3, |
| 646 | PINCTRL_GRP_PJTAG0_1, |
| 647 | PINCTRL_GRP_SPI0_1_SS1, |
| 648 | PINCTRL_GRP_TTC0_1_CLK, |
| 649 | PINCTRL_GRP_UART0_3, |
| 650 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 651 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 652 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 653 | END_OF_GROUPS, |
| 654 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 655 | }, |
| 656 | [PINCTRL_PIN_15] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 657 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 658 | PINCTRL_GRP_RESERVED, |
| 659 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 660 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 661 | PINCTRL_GRP_TESTSCAN0_0, |
| 662 | PINCTRL_GRP_RESERVED, |
| 663 | PINCTRL_GRP_GPIO0_15, |
| 664 | PINCTRL_GRP_CAN0_3, |
| 665 | PINCTRL_GRP_I2C0_3, |
| 666 | PINCTRL_GRP_PJTAG0_1, |
| 667 | PINCTRL_GRP_SPI0_1_SS0, |
| 668 | PINCTRL_GRP_TTC0_1_WAV, |
| 669 | PINCTRL_GRP_UART0_3, |
| 670 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 671 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 672 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 673 | END_OF_GROUPS, |
| 674 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 675 | }, |
| 676 | [PINCTRL_PIN_16] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 677 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 678 | PINCTRL_GRP_RESERVED, |
| 679 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 680 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 681 | PINCTRL_GRP_TESTSCAN0_0, |
| 682 | PINCTRL_GRP_RESERVED, |
| 683 | PINCTRL_GRP_GPIO0_16, |
| 684 | PINCTRL_GRP_CAN1_4, |
| 685 | PINCTRL_GRP_I2C1_4, |
| 686 | PINCTRL_GRP_SWDT1_2_CLK, |
| 687 | PINCTRL_GRP_SPI0_1, |
| 688 | PINCTRL_GRP_TTC3_2_CLK, |
| 689 | PINCTRL_GRP_UART1_4, |
| 690 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 691 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 692 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 693 | END_OF_GROUPS, |
| 694 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 695 | }, |
| 696 | [PINCTRL_PIN_17] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 697 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 698 | PINCTRL_GRP_RESERVED, |
| 699 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 700 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 701 | PINCTRL_GRP_TESTSCAN0_0, |
| 702 | PINCTRL_GRP_RESERVED, |
| 703 | PINCTRL_GRP_GPIO0_17, |
| 704 | PINCTRL_GRP_CAN1_4, |
| 705 | PINCTRL_GRP_I2C1_4, |
| 706 | PINCTRL_GRP_SWDT1_2_RST, |
| 707 | PINCTRL_GRP_SPI0_1, |
| 708 | PINCTRL_GRP_TTC3_2_WAV, |
| 709 | PINCTRL_GRP_UART1_4, |
| 710 | PINCTRL_GRP_TRACE0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 711 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 712 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 713 | END_OF_GROUPS, |
| 714 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 715 | }, |
| 716 | [PINCTRL_PIN_18] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 717 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 718 | PINCTRL_GRP_RESERVED, |
| 719 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 720 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 721 | PINCTRL_GRP_TESTSCAN0_0, |
| 722 | PINCTRL_GRP_CSU0_0, |
| 723 | PINCTRL_GRP_GPIO0_18, |
| 724 | PINCTRL_GRP_CAN0_4, |
| 725 | PINCTRL_GRP_I2C0_4, |
| 726 | PINCTRL_GRP_SWDT0_2_CLK, |
| 727 | PINCTRL_GRP_SPI1_1, |
| 728 | PINCTRL_GRP_TTC2_2_CLK, |
| 729 | PINCTRL_GRP_UART0_4, |
| 730 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 731 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 732 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 733 | END_OF_GROUPS, |
| 734 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 735 | }, |
| 736 | [PINCTRL_PIN_19] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 737 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 738 | PINCTRL_GRP_RESERVED, |
| 739 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 740 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 741 | PINCTRL_GRP_TESTSCAN0_0, |
| 742 | PINCTRL_GRP_CSU0_1, |
| 743 | PINCTRL_GRP_GPIO0_19, |
| 744 | PINCTRL_GRP_CAN0_4, |
| 745 | PINCTRL_GRP_I2C0_4, |
| 746 | PINCTRL_GRP_SWDT0_2_RST, |
| 747 | PINCTRL_GRP_SPI1_1_SS2, |
| 748 | PINCTRL_GRP_TTC2_2_WAV, |
| 749 | PINCTRL_GRP_UART0_4, |
| 750 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 751 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 752 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 753 | END_OF_GROUPS, |
| 754 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 755 | }, |
| 756 | [PINCTRL_PIN_20] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 757 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 758 | PINCTRL_GRP_RESERVED, |
| 759 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 760 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 761 | PINCTRL_GRP_TESTSCAN0_0, |
| 762 | PINCTRL_GRP_CSU0_2, |
| 763 | PINCTRL_GRP_GPIO0_20, |
| 764 | PINCTRL_GRP_CAN1_5, |
| 765 | PINCTRL_GRP_I2C1_5, |
| 766 | PINCTRL_GRP_SWDT1_3_CLK, |
| 767 | PINCTRL_GRP_SPI1_1_SS1, |
| 768 | PINCTRL_GRP_TTC1_2_CLK, |
| 769 | PINCTRL_GRP_UART1_5, |
| 770 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 771 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 772 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
| 773 | END_OF_GROUPS, |
| 774 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 775 | }, |
| 776 | [PINCTRL_PIN_21] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 777 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 778 | PINCTRL_GRP_RESERVED, |
| 779 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 780 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 781 | PINCTRL_GRP_TESTSCAN0_0, |
| 782 | PINCTRL_GRP_CSU0_3, |
| 783 | PINCTRL_GRP_GPIO0_21, |
| 784 | PINCTRL_GRP_CAN1_5, |
| 785 | PINCTRL_GRP_I2C1_5, |
| 786 | PINCTRL_GRP_SWDT1_3_RST, |
| 787 | PINCTRL_GRP_SPI1_1_SS0, |
| 788 | PINCTRL_GRP_TTC1_2_WAV, |
| 789 | PINCTRL_GRP_UART1_5, |
| 790 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 791 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 792 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 793 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 794 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 795 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 796 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 797 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 798 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 799 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 800 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
| 801 | END_OF_GROUPS, |
| 802 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 803 | }, |
| 804 | [PINCTRL_PIN_22] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 805 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 806 | PINCTRL_GRP_RESERVED, |
| 807 | PINCTRL_GRP_NAND0_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 808 | PINCTRL_GRP_SDIO0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 809 | PINCTRL_GRP_TESTSCAN0_0, |
| 810 | PINCTRL_GRP_CSU0_4, |
| 811 | PINCTRL_GRP_GPIO0_22, |
| 812 | PINCTRL_GRP_CAN0_5, |
| 813 | PINCTRL_GRP_I2C0_5, |
| 814 | PINCTRL_GRP_SWDT0_3_CLK, |
| 815 | PINCTRL_GRP_SPI1_1, |
| 816 | PINCTRL_GRP_TTC0_2_CLK, |
| 817 | PINCTRL_GRP_UART0_5, |
| 818 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 819 | PINCTRL_GRP_SDIO0_4BIT_0_0, |
| 820 | PINCTRL_GRP_SDIO0_4BIT_0_1, |
| 821 | PINCTRL_GRP_SDIO0_1BIT_0_0, |
| 822 | PINCTRL_GRP_SDIO0_1BIT_0_1, |
| 823 | PINCTRL_GRP_SDIO0_1BIT_0_2, |
| 824 | PINCTRL_GRP_SDIO0_1BIT_0_3, |
| 825 | PINCTRL_GRP_SDIO0_1BIT_0_4, |
| 826 | PINCTRL_GRP_SDIO0_1BIT_0_5, |
| 827 | PINCTRL_GRP_SDIO0_1BIT_0_6, |
| 828 | PINCTRL_GRP_SDIO0_1BIT_0_7, |
| 829 | END_OF_GROUPS, |
| 830 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 831 | }, |
| 832 | [PINCTRL_PIN_23] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 833 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 834 | PINCTRL_GRP_RESERVED, |
| 835 | PINCTRL_GRP_NAND0_0, |
| 836 | PINCTRL_GRP_SDIO0_0_PC, |
| 837 | PINCTRL_GRP_TESTSCAN0_0, |
| 838 | PINCTRL_GRP_CSU0_5, |
| 839 | PINCTRL_GRP_GPIO0_23, |
| 840 | PINCTRL_GRP_CAN0_5, |
| 841 | PINCTRL_GRP_I2C0_5, |
| 842 | PINCTRL_GRP_SWDT0_3_RST, |
| 843 | PINCTRL_GRP_SPI1_1, |
| 844 | PINCTRL_GRP_TTC0_2_WAV, |
| 845 | PINCTRL_GRP_UART0_5, |
| 846 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 847 | END_OF_GROUPS, |
| 848 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 849 | }, |
| 850 | [PINCTRL_PIN_24] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 851 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 852 | PINCTRL_GRP_RESERVED, |
| 853 | PINCTRL_GRP_NAND0_0, |
| 854 | PINCTRL_GRP_SDIO0_0_CD, |
| 855 | PINCTRL_GRP_TESTSCAN0_0, |
| 856 | PINCTRL_GRP_CSU0_6, |
| 857 | PINCTRL_GRP_GPIO0_24, |
| 858 | PINCTRL_GRP_CAN1_6, |
| 859 | PINCTRL_GRP_I2C1_6, |
| 860 | PINCTRL_GRP_SWDT1_4_CLK, |
| 861 | PINCTRL_GRP_RESERVED, |
| 862 | PINCTRL_GRP_TTC3_3_CLK, |
| 863 | PINCTRL_GRP_UART1_6, |
| 864 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 865 | END_OF_GROUPS, |
| 866 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 867 | }, |
| 868 | [PINCTRL_PIN_25] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 869 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 870 | PINCTRL_GRP_RESERVED, |
| 871 | PINCTRL_GRP_NAND0_0, |
| 872 | PINCTRL_GRP_SDIO0_0_WP, |
| 873 | PINCTRL_GRP_TESTSCAN0_0, |
| 874 | PINCTRL_GRP_CSU0_7, |
| 875 | PINCTRL_GRP_GPIO0_25, |
| 876 | PINCTRL_GRP_CAN1_6, |
| 877 | PINCTRL_GRP_I2C1_6, |
| 878 | PINCTRL_GRP_SWDT1_4_RST, |
| 879 | PINCTRL_GRP_RESERVED, |
| 880 | PINCTRL_GRP_TTC3_3_WAV, |
| 881 | PINCTRL_GRP_UART1_6, |
| 882 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 883 | END_OF_GROUPS, |
| 884 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 885 | }, |
| 886 | [PINCTRL_PIN_26] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 887 | .groups = &((uint16_t []) { |
Norbert Werner | 6f98002 | 2020-01-19 14:51:01 +0100 | [diff] [blame] | 888 | PINCTRL_GRP_ETHERNET0_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 889 | PINCTRL_GRP_GEMTSU0_0, |
| 890 | PINCTRL_GRP_NAND0_1_CE, |
| 891 | PINCTRL_GRP_PMU0_0, |
| 892 | PINCTRL_GRP_TESTSCAN0_0, |
| 893 | PINCTRL_GRP_CSU0_8, |
| 894 | PINCTRL_GRP_GPIO0_26, |
| 895 | PINCTRL_GRP_CAN0_6, |
| 896 | PINCTRL_GRP_I2C0_6, |
| 897 | PINCTRL_GRP_PJTAG0_2, |
| 898 | PINCTRL_GRP_SPI0_2, |
| 899 | PINCTRL_GRP_TTC2_3_CLK, |
| 900 | PINCTRL_GRP_UART0_6, |
| 901 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 902 | END_OF_GROUPS, |
| 903 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 904 | }, |
| 905 | [PINCTRL_PIN_27] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 906 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 907 | PINCTRL_GRP_ETHERNET0_0, |
| 908 | PINCTRL_GRP_NAND0_1_RB, |
| 909 | PINCTRL_GRP_PMU0_1, |
| 910 | PINCTRL_GRP_TESTSCAN0_0, |
| 911 | PINCTRL_GRP_DPAUX0_0, |
| 912 | PINCTRL_GRP_GPIO0_27, |
| 913 | PINCTRL_GRP_CAN0_6, |
| 914 | PINCTRL_GRP_I2C0_6, |
| 915 | PINCTRL_GRP_PJTAG0_2, |
| 916 | PINCTRL_GRP_SPI0_2_SS2, |
| 917 | PINCTRL_GRP_TTC2_3_WAV, |
| 918 | PINCTRL_GRP_UART0_6, |
| 919 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 920 | END_OF_GROUPS, |
| 921 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 922 | }, |
| 923 | [PINCTRL_PIN_28] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 924 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 925 | PINCTRL_GRP_ETHERNET0_0, |
| 926 | PINCTRL_GRP_NAND0_1_RB, |
| 927 | PINCTRL_GRP_PMU0_2, |
| 928 | PINCTRL_GRP_TESTSCAN0_0, |
| 929 | PINCTRL_GRP_DPAUX0_0, |
| 930 | PINCTRL_GRP_GPIO0_28, |
| 931 | PINCTRL_GRP_CAN1_7, |
| 932 | PINCTRL_GRP_I2C1_7, |
| 933 | PINCTRL_GRP_PJTAG0_2, |
| 934 | PINCTRL_GRP_SPI0_2_SS1, |
| 935 | PINCTRL_GRP_TTC1_3_CLK, |
| 936 | PINCTRL_GRP_UART1_7, |
| 937 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 938 | END_OF_GROUPS, |
| 939 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 940 | }, |
| 941 | [PINCTRL_PIN_29] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 942 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 943 | PINCTRL_GRP_ETHERNET0_0, |
| 944 | PINCTRL_GRP_PCIE0_0, |
| 945 | PINCTRL_GRP_PMU0_3, |
| 946 | PINCTRL_GRP_TESTSCAN0_0, |
| 947 | PINCTRL_GRP_DPAUX0_1, |
| 948 | PINCTRL_GRP_GPIO0_29, |
| 949 | PINCTRL_GRP_CAN1_7, |
| 950 | PINCTRL_GRP_I2C1_7, |
| 951 | PINCTRL_GRP_PJTAG0_2, |
| 952 | PINCTRL_GRP_SPI0_2_SS0, |
| 953 | PINCTRL_GRP_TTC1_3_WAV, |
| 954 | PINCTRL_GRP_UART1_7, |
| 955 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 956 | END_OF_GROUPS, |
| 957 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 958 | }, |
| 959 | [PINCTRL_PIN_30] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 960 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 961 | PINCTRL_GRP_ETHERNET0_0, |
| 962 | PINCTRL_GRP_PCIE0_1, |
| 963 | PINCTRL_GRP_PMU0_4, |
| 964 | PINCTRL_GRP_TESTSCAN0_0, |
| 965 | PINCTRL_GRP_DPAUX0_1, |
| 966 | PINCTRL_GRP_GPIO0_30, |
| 967 | PINCTRL_GRP_CAN0_7, |
| 968 | PINCTRL_GRP_I2C0_7, |
| 969 | PINCTRL_GRP_SWDT0_4_CLK, |
| 970 | PINCTRL_GRP_SPI0_2, |
| 971 | PINCTRL_GRP_TTC0_3_CLK, |
| 972 | PINCTRL_GRP_UART0_7, |
| 973 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 974 | END_OF_GROUPS, |
| 975 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 976 | }, |
| 977 | [PINCTRL_PIN_31] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 978 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 979 | PINCTRL_GRP_ETHERNET0_0, |
| 980 | PINCTRL_GRP_PCIE0_2, |
| 981 | PINCTRL_GRP_PMU0_5, |
| 982 | PINCTRL_GRP_TESTSCAN0_0, |
| 983 | PINCTRL_GRP_CSU0_9, |
| 984 | PINCTRL_GRP_GPIO0_31, |
| 985 | PINCTRL_GRP_CAN0_7, |
| 986 | PINCTRL_GRP_I2C0_7, |
| 987 | PINCTRL_GRP_SWDT0_4_RST, |
| 988 | PINCTRL_GRP_SPI0_2, |
| 989 | PINCTRL_GRP_TTC0_3_WAV, |
| 990 | PINCTRL_GRP_UART0_7, |
| 991 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 992 | END_OF_GROUPS, |
| 993 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 994 | }, |
| 995 | [PINCTRL_PIN_32] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 996 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 997 | PINCTRL_GRP_ETHERNET0_0, |
| 998 | PINCTRL_GRP_NAND0_1_DQS, |
| 999 | PINCTRL_GRP_PMU0_6, |
| 1000 | PINCTRL_GRP_TESTSCAN0_0, |
| 1001 | PINCTRL_GRP_CSU0_10, |
| 1002 | PINCTRL_GRP_GPIO0_32, |
| 1003 | PINCTRL_GRP_CAN1_8, |
| 1004 | PINCTRL_GRP_I2C1_8, |
| 1005 | PINCTRL_GRP_SWDT1_5_CLK, |
| 1006 | PINCTRL_GRP_SPI1_2, |
| 1007 | PINCTRL_GRP_TTC3_4_CLK, |
| 1008 | PINCTRL_GRP_UART1_8, |
| 1009 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1010 | END_OF_GROUPS, |
| 1011 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1012 | }, |
| 1013 | [PINCTRL_PIN_33] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1014 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1015 | PINCTRL_GRP_ETHERNET0_0, |
| 1016 | PINCTRL_GRP_PCIE0_3, |
| 1017 | PINCTRL_GRP_PMU0_7, |
| 1018 | PINCTRL_GRP_TESTSCAN0_0, |
| 1019 | PINCTRL_GRP_CSU0_11, |
| 1020 | PINCTRL_GRP_GPIO0_33, |
| 1021 | PINCTRL_GRP_CAN1_8, |
| 1022 | PINCTRL_GRP_I2C1_8, |
| 1023 | PINCTRL_GRP_SWDT1_5_RST, |
| 1024 | PINCTRL_GRP_SPI1_2_SS2, |
| 1025 | PINCTRL_GRP_TTC3_4_WAV, |
| 1026 | PINCTRL_GRP_UART1_8, |
| 1027 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1028 | END_OF_GROUPS, |
| 1029 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1030 | }, |
| 1031 | [PINCTRL_PIN_34] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1032 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1033 | PINCTRL_GRP_ETHERNET0_0, |
| 1034 | PINCTRL_GRP_PCIE0_4, |
| 1035 | PINCTRL_GRP_PMU0_8, |
| 1036 | PINCTRL_GRP_TESTSCAN0_0, |
| 1037 | PINCTRL_GRP_DPAUX0_2, |
| 1038 | PINCTRL_GRP_GPIO0_34, |
| 1039 | PINCTRL_GRP_CAN0_8, |
| 1040 | PINCTRL_GRP_I2C0_8, |
| 1041 | PINCTRL_GRP_SWDT0_5_CLK, |
| 1042 | PINCTRL_GRP_SPI1_2_SS1, |
| 1043 | PINCTRL_GRP_TTC2_4_CLK, |
| 1044 | PINCTRL_GRP_UART0_8, |
| 1045 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1046 | END_OF_GROUPS, |
| 1047 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1048 | }, |
| 1049 | [PINCTRL_PIN_35] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1050 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1051 | PINCTRL_GRP_ETHERNET0_0, |
| 1052 | PINCTRL_GRP_PCIE0_5, |
| 1053 | PINCTRL_GRP_PMU0_9, |
| 1054 | PINCTRL_GRP_TESTSCAN0_0, |
| 1055 | PINCTRL_GRP_DPAUX0_2, |
| 1056 | PINCTRL_GRP_GPIO0_35, |
| 1057 | PINCTRL_GRP_CAN0_8, |
| 1058 | PINCTRL_GRP_I2C0_8, |
| 1059 | PINCTRL_GRP_SWDT0_5_RST, |
| 1060 | PINCTRL_GRP_SPI1_2_SS0, |
| 1061 | PINCTRL_GRP_TTC2_4_WAV, |
| 1062 | PINCTRL_GRP_UART0_8, |
| 1063 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1064 | END_OF_GROUPS, |
| 1065 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1066 | }, |
| 1067 | [PINCTRL_PIN_36] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1068 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1069 | PINCTRL_GRP_ETHERNET0_0, |
| 1070 | PINCTRL_GRP_PCIE0_6, |
| 1071 | PINCTRL_GRP_PMU0_10, |
| 1072 | PINCTRL_GRP_TESTSCAN0_0, |
| 1073 | PINCTRL_GRP_DPAUX0_3, |
| 1074 | PINCTRL_GRP_GPIO0_36, |
| 1075 | PINCTRL_GRP_CAN1_9, |
| 1076 | PINCTRL_GRP_I2C1_9, |
| 1077 | PINCTRL_GRP_SWDT1_6_CLK, |
| 1078 | PINCTRL_GRP_SPI1_2, |
| 1079 | PINCTRL_GRP_TTC1_4_CLK, |
| 1080 | PINCTRL_GRP_UART1_9, |
| 1081 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1082 | END_OF_GROUPS, |
| 1083 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1084 | }, |
| 1085 | [PINCTRL_PIN_37] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1086 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1087 | PINCTRL_GRP_ETHERNET0_0, |
| 1088 | PINCTRL_GRP_PCIE0_7, |
| 1089 | PINCTRL_GRP_PMU0_11, |
| 1090 | PINCTRL_GRP_TESTSCAN0_0, |
| 1091 | PINCTRL_GRP_DPAUX0_3, |
| 1092 | PINCTRL_GRP_GPIO0_37, |
| 1093 | PINCTRL_GRP_CAN1_9, |
| 1094 | PINCTRL_GRP_I2C1_9, |
| 1095 | PINCTRL_GRP_SWDT1_6_RST, |
| 1096 | PINCTRL_GRP_SPI1_2, |
| 1097 | PINCTRL_GRP_TTC1_4_WAV, |
| 1098 | PINCTRL_GRP_UART1_9, |
| 1099 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1100 | END_OF_GROUPS, |
| 1101 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1102 | }, |
| 1103 | [PINCTRL_PIN_38] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1104 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1105 | PINCTRL_GRP_ETHERNET1_0, |
| 1106 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1107 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1108 | PINCTRL_GRP_RESERVED, |
| 1109 | PINCTRL_GRP_RESERVED, |
| 1110 | PINCTRL_GRP_GPIO0_38, |
| 1111 | PINCTRL_GRP_CAN0_9, |
| 1112 | PINCTRL_GRP_I2C0_9, |
| 1113 | PINCTRL_GRP_PJTAG0_3, |
| 1114 | PINCTRL_GRP_SPI0_3, |
| 1115 | PINCTRL_GRP_TTC0_4_CLK, |
| 1116 | PINCTRL_GRP_UART0_9, |
| 1117 | PINCTRL_GRP_TRACE0_1_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1118 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1119 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1120 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 1121 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 1122 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 1123 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 1124 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 1125 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 1126 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 1127 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
| 1128 | END_OF_GROUPS, |
| 1129 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1130 | }, |
| 1131 | [PINCTRL_PIN_39] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1132 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1133 | PINCTRL_GRP_ETHERNET1_0, |
| 1134 | PINCTRL_GRP_RESERVED, |
| 1135 | PINCTRL_GRP_SDIO0_1_CD, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1136 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1137 | PINCTRL_GRP_RESERVED, |
| 1138 | PINCTRL_GRP_GPIO0_39, |
| 1139 | PINCTRL_GRP_CAN0_9, |
| 1140 | PINCTRL_GRP_I2C0_9, |
| 1141 | PINCTRL_GRP_PJTAG0_3, |
| 1142 | PINCTRL_GRP_SPI0_3_SS2, |
| 1143 | PINCTRL_GRP_TTC0_4_WAV, |
| 1144 | PINCTRL_GRP_UART0_9, |
| 1145 | PINCTRL_GRP_TRACE0_1_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1146 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1147 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 1148 | END_OF_GROUPS, |
| 1149 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1150 | }, |
| 1151 | [PINCTRL_PIN_40] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1152 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1153 | PINCTRL_GRP_ETHERNET1_0, |
| 1154 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1155 | PINCTRL_GRP_SDIO0_1, |
| 1156 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1157 | PINCTRL_GRP_RESERVED, |
| 1158 | PINCTRL_GRP_GPIO0_40, |
| 1159 | PINCTRL_GRP_CAN1_10, |
| 1160 | PINCTRL_GRP_I2C1_10, |
| 1161 | PINCTRL_GRP_PJTAG0_3, |
| 1162 | PINCTRL_GRP_SPI0_3_SS1, |
| 1163 | PINCTRL_GRP_TTC3_5_CLK, |
| 1164 | PINCTRL_GRP_UART1_10, |
| 1165 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1166 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1167 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1168 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 1169 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 1170 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 1171 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 1172 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 1173 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 1174 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 1175 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
| 1176 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1177 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 1178 | END_OF_GROUPS, |
| 1179 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1180 | }, |
| 1181 | [PINCTRL_PIN_41] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1182 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1183 | PINCTRL_GRP_ETHERNET1_0, |
| 1184 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1185 | PINCTRL_GRP_SDIO0_1, |
| 1186 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1187 | PINCTRL_GRP_RESERVED, |
| 1188 | PINCTRL_GRP_GPIO0_41, |
| 1189 | PINCTRL_GRP_CAN1_10, |
| 1190 | PINCTRL_GRP_I2C1_10, |
| 1191 | PINCTRL_GRP_PJTAG0_3, |
| 1192 | PINCTRL_GRP_SPI0_3_SS0, |
| 1193 | PINCTRL_GRP_TTC3_5_WAV, |
| 1194 | PINCTRL_GRP_UART1_10, |
| 1195 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1196 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1197 | PINCTRL_GRP_SDIO0_1BIT_1_0, |
| 1198 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1199 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 1200 | END_OF_GROUPS, |
| 1201 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1202 | }, |
| 1203 | [PINCTRL_PIN_42] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1204 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1205 | PINCTRL_GRP_ETHERNET1_0, |
| 1206 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1207 | PINCTRL_GRP_SDIO0_1, |
| 1208 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1209 | PINCTRL_GRP_RESERVED, |
| 1210 | PINCTRL_GRP_GPIO0_42, |
| 1211 | PINCTRL_GRP_CAN0_10, |
| 1212 | PINCTRL_GRP_I2C0_10, |
| 1213 | PINCTRL_GRP_SWDT0_6_CLK, |
| 1214 | PINCTRL_GRP_SPI0_3, |
| 1215 | PINCTRL_GRP_TTC2_5_CLK, |
| 1216 | PINCTRL_GRP_UART0_10, |
| 1217 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1218 | PINCTRL_GRP_SDIO0_1, |
| 1219 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1220 | PINCTRL_GRP_SDIO0_1BIT_1_1, |
| 1221 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1222 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 1223 | END_OF_GROUPS, |
| 1224 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1225 | }, |
| 1226 | [PINCTRL_PIN_43] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1227 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1228 | PINCTRL_GRP_ETHERNET1_0, |
| 1229 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1230 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1231 | PINCTRL_GRP_SDIO1_0_PC, |
| 1232 | PINCTRL_GRP_RESERVED, |
| 1233 | PINCTRL_GRP_GPIO0_43, |
| 1234 | PINCTRL_GRP_CAN0_10, |
| 1235 | PINCTRL_GRP_I2C0_10, |
| 1236 | PINCTRL_GRP_SWDT0_6_RST, |
| 1237 | PINCTRL_GRP_SPI0_3, |
| 1238 | PINCTRL_GRP_TTC2_5_WAV, |
| 1239 | PINCTRL_GRP_UART0_10, |
| 1240 | PINCTRL_GRP_TRACE0_1, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1241 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1242 | PINCTRL_GRP_SDIO0_1BIT_1_2, |
| 1243 | END_OF_GROUPS, |
| 1244 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1245 | }, |
| 1246 | [PINCTRL_PIN_44] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1247 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1248 | PINCTRL_GRP_ETHERNET1_0, |
| 1249 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1250 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1251 | PINCTRL_GRP_SDIO1_0_WP, |
| 1252 | PINCTRL_GRP_RESERVED, |
| 1253 | PINCTRL_GRP_GPIO0_44, |
| 1254 | PINCTRL_GRP_CAN1_11, |
| 1255 | PINCTRL_GRP_I2C1_11, |
| 1256 | PINCTRL_GRP_SWDT1_7_CLK, |
| 1257 | PINCTRL_GRP_SPI1_3, |
| 1258 | PINCTRL_GRP_TTC1_5_CLK, |
| 1259 | PINCTRL_GRP_UART1_11, |
| 1260 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1261 | PINCTRL_GRP_SDIO0_4BIT_1_0, |
| 1262 | PINCTRL_GRP_SDIO0_1BIT_1_3, |
| 1263 | END_OF_GROUPS, |
| 1264 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1265 | }, |
| 1266 | [PINCTRL_PIN_45] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1267 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1268 | PINCTRL_GRP_ETHERNET1_0, |
| 1269 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1270 | PINCTRL_GRP_SDIO0_1, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1271 | PINCTRL_GRP_SDIO1_0_CD, |
| 1272 | PINCTRL_GRP_RESERVED, |
| 1273 | PINCTRL_GRP_GPIO0_45, |
| 1274 | PINCTRL_GRP_CAN1_11, |
| 1275 | PINCTRL_GRP_I2C1_11, |
| 1276 | PINCTRL_GRP_SWDT1_7_RST, |
| 1277 | PINCTRL_GRP_SPI1_3_SS2, |
| 1278 | PINCTRL_GRP_TTC1_5_WAV, |
| 1279 | PINCTRL_GRP_UART1_11, |
| 1280 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1281 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1282 | PINCTRL_GRP_SDIO0_1BIT_1_4, |
| 1283 | END_OF_GROUPS, |
| 1284 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1285 | }, |
| 1286 | [PINCTRL_PIN_46] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1287 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1288 | PINCTRL_GRP_ETHERNET1_0, |
| 1289 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1290 | PINCTRL_GRP_SDIO0_1, |
| 1291 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1292 | PINCTRL_GRP_RESERVED, |
| 1293 | PINCTRL_GRP_GPIO0_46, |
| 1294 | PINCTRL_GRP_CAN0_11, |
| 1295 | PINCTRL_GRP_I2C0_11, |
| 1296 | PINCTRL_GRP_SWDT0_7_CLK, |
| 1297 | PINCTRL_GRP_SPI1_3_SS1, |
| 1298 | PINCTRL_GRP_TTC0_5_CLK, |
| 1299 | PINCTRL_GRP_UART0_11, |
| 1300 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1301 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1302 | PINCTRL_GRP_SDIO0_1BIT_1_5, |
| 1303 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1304 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 1305 | END_OF_GROUPS, |
| 1306 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1307 | }, |
| 1308 | [PINCTRL_PIN_47] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1309 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1310 | PINCTRL_GRP_ETHERNET1_0, |
| 1311 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1312 | PINCTRL_GRP_SDIO0_1, |
| 1313 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1314 | PINCTRL_GRP_RESERVED, |
| 1315 | PINCTRL_GRP_GPIO0_47, |
| 1316 | PINCTRL_GRP_CAN0_11, |
| 1317 | PINCTRL_GRP_I2C0_11, |
| 1318 | PINCTRL_GRP_SWDT0_7_RST, |
| 1319 | PINCTRL_GRP_SPI1_3_SS0, |
| 1320 | PINCTRL_GRP_TTC0_5_WAV, |
| 1321 | PINCTRL_GRP_UART0_11, |
| 1322 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1323 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1324 | PINCTRL_GRP_SDIO0_1BIT_1_6, |
| 1325 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1326 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 1327 | END_OF_GROUPS, |
| 1328 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1329 | }, |
| 1330 | [PINCTRL_PIN_48] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1331 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1332 | PINCTRL_GRP_ETHERNET1_0, |
| 1333 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1334 | PINCTRL_GRP_SDIO0_1, |
| 1335 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1336 | PINCTRL_GRP_RESERVED, |
| 1337 | PINCTRL_GRP_GPIO0_48, |
| 1338 | PINCTRL_GRP_CAN1_12, |
| 1339 | PINCTRL_GRP_I2C1_12, |
| 1340 | PINCTRL_GRP_SWDT1_8_CLK, |
| 1341 | PINCTRL_GRP_SPI1_3, |
| 1342 | PINCTRL_GRP_TTC3_6_CLK, |
| 1343 | PINCTRL_GRP_UART1_12, |
| 1344 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1345 | PINCTRL_GRP_SDIO0_4BIT_1_1, |
| 1346 | PINCTRL_GRP_SDIO0_1BIT_1_7, |
| 1347 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1348 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 1349 | END_OF_GROUPS, |
| 1350 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1351 | }, |
| 1352 | [PINCTRL_PIN_49] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1353 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1354 | PINCTRL_GRP_ETHERNET1_0, |
| 1355 | PINCTRL_GRP_RESERVED, |
| 1356 | PINCTRL_GRP_SDIO0_1_PC, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1357 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1358 | PINCTRL_GRP_RESERVED, |
| 1359 | PINCTRL_GRP_GPIO0_49, |
| 1360 | PINCTRL_GRP_CAN1_12, |
| 1361 | PINCTRL_GRP_I2C1_12, |
| 1362 | PINCTRL_GRP_SWDT1_8_RST, |
| 1363 | PINCTRL_GRP_SPI1_3, |
| 1364 | PINCTRL_GRP_TTC3_6_WAV, |
| 1365 | PINCTRL_GRP_UART1_12, |
| 1366 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1367 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1368 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
| 1369 | END_OF_GROUPS, |
| 1370 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1371 | }, |
| 1372 | [PINCTRL_PIN_50] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1373 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1374 | PINCTRL_GRP_GEMTSU0_1, |
| 1375 | PINCTRL_GRP_RESERVED, |
| 1376 | PINCTRL_GRP_SDIO0_1_WP, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1377 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1378 | PINCTRL_GRP_RESERVED, |
| 1379 | PINCTRL_GRP_GPIO0_50, |
| 1380 | PINCTRL_GRP_CAN0_12, |
| 1381 | PINCTRL_GRP_I2C0_12, |
| 1382 | PINCTRL_GRP_SWDT0_8_CLK, |
| 1383 | PINCTRL_GRP_MDIO1_0, |
| 1384 | PINCTRL_GRP_TTC2_6_CLK, |
| 1385 | PINCTRL_GRP_UART0_12, |
| 1386 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1387 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1388 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1389 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 1390 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 1391 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 1392 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 1393 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 1394 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 1395 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 1396 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
| 1397 | END_OF_GROUPS, |
| 1398 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1399 | }, |
| 1400 | [PINCTRL_PIN_51] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1401 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1402 | PINCTRL_GRP_GEMTSU0_2, |
| 1403 | PINCTRL_GRP_RESERVED, |
| 1404 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1405 | PINCTRL_GRP_SDIO1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1406 | PINCTRL_GRP_RESERVED, |
| 1407 | PINCTRL_GRP_GPIO0_51, |
| 1408 | PINCTRL_GRP_CAN0_12, |
| 1409 | PINCTRL_GRP_I2C0_12, |
| 1410 | PINCTRL_GRP_SWDT0_8_RST, |
| 1411 | PINCTRL_GRP_MDIO1_0, |
| 1412 | PINCTRL_GRP_TTC2_6_WAV, |
| 1413 | PINCTRL_GRP_UART0_12, |
| 1414 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1415 | PINCTRL_GRP_SDIO1_4BIT_0_0, |
| 1416 | PINCTRL_GRP_SDIO1_4BIT_0_1, |
| 1417 | PINCTRL_GRP_SDIO1_1BIT_0_0, |
| 1418 | PINCTRL_GRP_SDIO1_1BIT_0_1, |
| 1419 | PINCTRL_GRP_SDIO1_1BIT_0_2, |
| 1420 | PINCTRL_GRP_SDIO1_1BIT_0_3, |
| 1421 | PINCTRL_GRP_SDIO1_1BIT_0_4, |
| 1422 | PINCTRL_GRP_SDIO1_1BIT_0_5, |
| 1423 | PINCTRL_GRP_SDIO1_1BIT_0_6, |
| 1424 | PINCTRL_GRP_SDIO1_1BIT_0_7, |
| 1425 | END_OF_GROUPS, |
| 1426 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1427 | }, |
| 1428 | [PINCTRL_PIN_52] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1429 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1430 | PINCTRL_GRP_ETHERNET2_0, |
| 1431 | PINCTRL_GRP_USB0_0, |
| 1432 | PINCTRL_GRP_RESERVED, |
| 1433 | PINCTRL_GRP_RESERVED, |
| 1434 | PINCTRL_GRP_RESERVED, |
| 1435 | PINCTRL_GRP_GPIO0_52, |
| 1436 | PINCTRL_GRP_CAN1_13, |
| 1437 | PINCTRL_GRP_I2C1_13, |
| 1438 | PINCTRL_GRP_PJTAG0_4, |
| 1439 | PINCTRL_GRP_SPI0_4, |
| 1440 | PINCTRL_GRP_TTC1_6_CLK, |
| 1441 | PINCTRL_GRP_UART1_13, |
| 1442 | PINCTRL_GRP_TRACE0_2_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1443 | END_OF_GROUPS, |
| 1444 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1445 | }, |
| 1446 | [PINCTRL_PIN_53] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1447 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1448 | PINCTRL_GRP_ETHERNET2_0, |
| 1449 | PINCTRL_GRP_USB0_0, |
| 1450 | PINCTRL_GRP_RESERVED, |
| 1451 | PINCTRL_GRP_RESERVED, |
| 1452 | PINCTRL_GRP_RESERVED, |
| 1453 | PINCTRL_GRP_GPIO0_53, |
| 1454 | PINCTRL_GRP_CAN1_13, |
| 1455 | PINCTRL_GRP_I2C1_13, |
| 1456 | PINCTRL_GRP_PJTAG0_4, |
| 1457 | PINCTRL_GRP_SPI0_4_SS2, |
| 1458 | PINCTRL_GRP_TTC1_6_WAV, |
| 1459 | PINCTRL_GRP_UART1_13, |
| 1460 | PINCTRL_GRP_TRACE0_2_CLK, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1461 | END_OF_GROUPS, |
| 1462 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1463 | }, |
| 1464 | [PINCTRL_PIN_54] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1465 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1466 | PINCTRL_GRP_ETHERNET2_0, |
| 1467 | PINCTRL_GRP_USB0_0, |
| 1468 | PINCTRL_GRP_RESERVED, |
| 1469 | PINCTRL_GRP_RESERVED, |
| 1470 | PINCTRL_GRP_RESERVED, |
| 1471 | PINCTRL_GRP_GPIO0_54, |
| 1472 | PINCTRL_GRP_CAN0_13, |
| 1473 | PINCTRL_GRP_I2C0_13, |
| 1474 | PINCTRL_GRP_PJTAG0_4, |
| 1475 | PINCTRL_GRP_SPI0_4_SS1, |
| 1476 | PINCTRL_GRP_TTC0_6_CLK, |
| 1477 | PINCTRL_GRP_UART0_13, |
| 1478 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1479 | END_OF_GROUPS, |
| 1480 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1481 | }, |
| 1482 | [PINCTRL_PIN_55] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1483 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1484 | PINCTRL_GRP_ETHERNET2_0, |
| 1485 | PINCTRL_GRP_USB0_0, |
| 1486 | PINCTRL_GRP_RESERVED, |
| 1487 | PINCTRL_GRP_RESERVED, |
| 1488 | PINCTRL_GRP_RESERVED, |
| 1489 | PINCTRL_GRP_GPIO0_55, |
| 1490 | PINCTRL_GRP_CAN0_13, |
| 1491 | PINCTRL_GRP_I2C0_13, |
| 1492 | PINCTRL_GRP_PJTAG0_4, |
| 1493 | PINCTRL_GRP_SPI0_4_SS0, |
| 1494 | PINCTRL_GRP_TTC0_6_WAV, |
| 1495 | PINCTRL_GRP_UART0_13, |
| 1496 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1497 | END_OF_GROUPS, |
| 1498 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1499 | }, |
| 1500 | [PINCTRL_PIN_56] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1501 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1502 | PINCTRL_GRP_ETHERNET2_0, |
| 1503 | PINCTRL_GRP_USB0_0, |
| 1504 | PINCTRL_GRP_RESERVED, |
| 1505 | PINCTRL_GRP_RESERVED, |
| 1506 | PINCTRL_GRP_RESERVED, |
| 1507 | PINCTRL_GRP_GPIO0_56, |
| 1508 | PINCTRL_GRP_CAN1_14, |
| 1509 | PINCTRL_GRP_I2C1_14, |
| 1510 | PINCTRL_GRP_SWDT1_9_CLK, |
| 1511 | PINCTRL_GRP_SPI0_4, |
| 1512 | PINCTRL_GRP_TTC3_7_CLK, |
| 1513 | PINCTRL_GRP_UART1_14, |
| 1514 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1515 | END_OF_GROUPS, |
| 1516 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1517 | }, |
| 1518 | [PINCTRL_PIN_57] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1519 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1520 | PINCTRL_GRP_ETHERNET2_0, |
| 1521 | PINCTRL_GRP_USB0_0, |
| 1522 | PINCTRL_GRP_RESERVED, |
| 1523 | PINCTRL_GRP_RESERVED, |
| 1524 | PINCTRL_GRP_RESERVED, |
| 1525 | PINCTRL_GRP_GPIO0_57, |
| 1526 | PINCTRL_GRP_CAN1_14, |
| 1527 | PINCTRL_GRP_I2C1_14, |
| 1528 | PINCTRL_GRP_SWDT1_9_RST, |
| 1529 | PINCTRL_GRP_SPI0_4, |
| 1530 | PINCTRL_GRP_TTC3_7_WAV, |
| 1531 | PINCTRL_GRP_UART1_14, |
| 1532 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1533 | END_OF_GROUPS, |
| 1534 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1535 | }, |
| 1536 | [PINCTRL_PIN_58] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1537 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1538 | PINCTRL_GRP_ETHERNET2_0, |
| 1539 | PINCTRL_GRP_USB0_0, |
| 1540 | PINCTRL_GRP_RESERVED, |
| 1541 | PINCTRL_GRP_RESERVED, |
| 1542 | PINCTRL_GRP_RESERVED, |
| 1543 | PINCTRL_GRP_GPIO0_58, |
| 1544 | PINCTRL_GRP_CAN0_14, |
| 1545 | PINCTRL_GRP_I2C0_14, |
| 1546 | PINCTRL_GRP_PJTAG0_5, |
| 1547 | PINCTRL_GRP_SPI1_4, |
| 1548 | PINCTRL_GRP_TTC2_7_CLK, |
| 1549 | PINCTRL_GRP_UART0_14, |
| 1550 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1551 | END_OF_GROUPS, |
| 1552 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1553 | }, |
| 1554 | [PINCTRL_PIN_59] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1555 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1556 | PINCTRL_GRP_ETHERNET2_0, |
| 1557 | PINCTRL_GRP_USB0_0, |
| 1558 | PINCTRL_GRP_RESERVED, |
| 1559 | PINCTRL_GRP_RESERVED, |
| 1560 | PINCTRL_GRP_RESERVED, |
| 1561 | PINCTRL_GRP_GPIO0_59, |
| 1562 | PINCTRL_GRP_CAN0_14, |
| 1563 | PINCTRL_GRP_I2C0_14, |
| 1564 | PINCTRL_GRP_PJTAG0_5, |
| 1565 | PINCTRL_GRP_SPI1_4_SS2, |
| 1566 | PINCTRL_GRP_TTC2_7_WAV, |
| 1567 | PINCTRL_GRP_UART0_14, |
| 1568 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1569 | END_OF_GROUPS, |
| 1570 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1571 | }, |
| 1572 | [PINCTRL_PIN_60] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1573 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1574 | PINCTRL_GRP_ETHERNET2_0, |
| 1575 | PINCTRL_GRP_USB0_0, |
| 1576 | PINCTRL_GRP_RESERVED, |
| 1577 | PINCTRL_GRP_RESERVED, |
| 1578 | PINCTRL_GRP_RESERVED, |
| 1579 | PINCTRL_GRP_GPIO0_60, |
| 1580 | PINCTRL_GRP_CAN1_15, |
| 1581 | PINCTRL_GRP_I2C1_15, |
| 1582 | PINCTRL_GRP_PJTAG0_5, |
| 1583 | PINCTRL_GRP_SPI1_4_SS1, |
| 1584 | PINCTRL_GRP_TTC1_7_CLK, |
| 1585 | PINCTRL_GRP_UART1_15, |
| 1586 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1587 | END_OF_GROUPS, |
| 1588 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1589 | }, |
| 1590 | [PINCTRL_PIN_61] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1591 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1592 | PINCTRL_GRP_ETHERNET2_0, |
| 1593 | PINCTRL_GRP_USB0_0, |
| 1594 | PINCTRL_GRP_RESERVED, |
| 1595 | PINCTRL_GRP_RESERVED, |
| 1596 | PINCTRL_GRP_RESERVED, |
| 1597 | PINCTRL_GRP_GPIO0_61, |
| 1598 | PINCTRL_GRP_CAN1_15, |
| 1599 | PINCTRL_GRP_I2C1_15, |
| 1600 | PINCTRL_GRP_PJTAG0_5, |
| 1601 | PINCTRL_GRP_SPI1_4_SS0, |
| 1602 | PINCTRL_GRP_TTC1_7_WAV, |
| 1603 | PINCTRL_GRP_UART1_15, |
| 1604 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1605 | END_OF_GROUPS, |
| 1606 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1607 | }, |
| 1608 | [PINCTRL_PIN_62] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1609 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1610 | PINCTRL_GRP_ETHERNET2_0, |
| 1611 | PINCTRL_GRP_USB0_0, |
| 1612 | PINCTRL_GRP_RESERVED, |
| 1613 | PINCTRL_GRP_RESERVED, |
| 1614 | PINCTRL_GRP_RESERVED, |
| 1615 | PINCTRL_GRP_GPIO0_62, |
| 1616 | PINCTRL_GRP_CAN0_15, |
| 1617 | PINCTRL_GRP_I2C0_15, |
| 1618 | PINCTRL_GRP_SWDT0_9_CLK, |
| 1619 | PINCTRL_GRP_SPI1_4, |
| 1620 | PINCTRL_GRP_TTC0_7_CLK, |
| 1621 | PINCTRL_GRP_UART0_15, |
| 1622 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1623 | END_OF_GROUPS, |
| 1624 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1625 | }, |
| 1626 | [PINCTRL_PIN_63] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1627 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1628 | PINCTRL_GRP_ETHERNET2_0, |
| 1629 | PINCTRL_GRP_USB0_0, |
| 1630 | PINCTRL_GRP_RESERVED, |
| 1631 | PINCTRL_GRP_RESERVED, |
| 1632 | PINCTRL_GRP_RESERVED, |
| 1633 | PINCTRL_GRP_GPIO0_63, |
| 1634 | PINCTRL_GRP_CAN0_15, |
| 1635 | PINCTRL_GRP_I2C0_15, |
| 1636 | PINCTRL_GRP_SWDT0_9_RST, |
| 1637 | PINCTRL_GRP_SPI1_4, |
| 1638 | PINCTRL_GRP_TTC0_7_WAV, |
| 1639 | PINCTRL_GRP_UART0_15, |
| 1640 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1641 | END_OF_GROUPS, |
| 1642 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1643 | }, |
| 1644 | [PINCTRL_PIN_64] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1645 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1646 | PINCTRL_GRP_ETHERNET3_0, |
| 1647 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1648 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1649 | PINCTRL_GRP_RESERVED, |
| 1650 | PINCTRL_GRP_RESERVED, |
| 1651 | PINCTRL_GRP_GPIO0_64, |
| 1652 | PINCTRL_GRP_CAN1_16, |
| 1653 | PINCTRL_GRP_I2C1_16, |
| 1654 | PINCTRL_GRP_SWDT1_10_CLK, |
| 1655 | PINCTRL_GRP_SPI0_5, |
| 1656 | PINCTRL_GRP_TTC3_8_CLK, |
| 1657 | PINCTRL_GRP_UART1_16, |
| 1658 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1659 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 1660 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 1661 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 1662 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 1663 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 1664 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 1665 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 1666 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 1667 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 1668 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
| 1669 | END_OF_GROUPS, |
| 1670 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1671 | }, |
| 1672 | [PINCTRL_PIN_65] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1673 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1674 | PINCTRL_GRP_ETHERNET3_0, |
| 1675 | PINCTRL_GRP_USB1_0, |
| 1676 | PINCTRL_GRP_SDIO0_2_CD, |
| 1677 | PINCTRL_GRP_RESERVED, |
| 1678 | PINCTRL_GRP_RESERVED, |
| 1679 | PINCTRL_GRP_GPIO0_65, |
| 1680 | PINCTRL_GRP_CAN1_16, |
| 1681 | PINCTRL_GRP_I2C1_16, |
| 1682 | PINCTRL_GRP_SWDT1_10_RST, |
| 1683 | PINCTRL_GRP_SPI0_5_SS2, |
| 1684 | PINCTRL_GRP_TTC3_8_WAV, |
| 1685 | PINCTRL_GRP_UART1_16, |
| 1686 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1687 | END_OF_GROUPS, |
| 1688 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1689 | }, |
| 1690 | [PINCTRL_PIN_66] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1691 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1692 | PINCTRL_GRP_ETHERNET3_0, |
| 1693 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1694 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1695 | PINCTRL_GRP_RESERVED, |
| 1696 | PINCTRL_GRP_RESERVED, |
| 1697 | PINCTRL_GRP_GPIO0_66, |
| 1698 | PINCTRL_GRP_CAN0_16, |
| 1699 | PINCTRL_GRP_I2C0_16, |
| 1700 | PINCTRL_GRP_SWDT0_10_CLK, |
| 1701 | PINCTRL_GRP_SPI0_5_SS1, |
| 1702 | PINCTRL_GRP_TTC2_8_CLK, |
| 1703 | PINCTRL_GRP_UART0_16, |
| 1704 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1705 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 1706 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 1707 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 1708 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 1709 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 1710 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 1711 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 1712 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 1713 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 1714 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
| 1715 | END_OF_GROUPS, |
| 1716 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1717 | }, |
| 1718 | [PINCTRL_PIN_67] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1719 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1720 | PINCTRL_GRP_ETHERNET3_0, |
| 1721 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1722 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1723 | PINCTRL_GRP_RESERVED, |
| 1724 | PINCTRL_GRP_RESERVED, |
| 1725 | PINCTRL_GRP_GPIO0_67, |
| 1726 | PINCTRL_GRP_CAN0_16, |
| 1727 | PINCTRL_GRP_I2C0_16, |
| 1728 | PINCTRL_GRP_SWDT0_10_RST, |
| 1729 | PINCTRL_GRP_SPI0_5_SS0, |
| 1730 | PINCTRL_GRP_TTC2_8_WAV, |
| 1731 | PINCTRL_GRP_UART0_16, |
| 1732 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1733 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 1734 | PINCTRL_GRP_SDIO0_1BIT_2_0, |
| 1735 | END_OF_GROUPS, |
| 1736 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1737 | }, |
| 1738 | [PINCTRL_PIN_68] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1739 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1740 | PINCTRL_GRP_ETHERNET3_0, |
| 1741 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1742 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1743 | PINCTRL_GRP_RESERVED, |
| 1744 | PINCTRL_GRP_RESERVED, |
| 1745 | PINCTRL_GRP_GPIO0_68, |
| 1746 | PINCTRL_GRP_CAN1_17, |
| 1747 | PINCTRL_GRP_I2C1_17, |
| 1748 | PINCTRL_GRP_SWDT1_11_CLK, |
| 1749 | PINCTRL_GRP_SPI0_5, |
| 1750 | PINCTRL_GRP_TTC1_8_CLK, |
| 1751 | PINCTRL_GRP_UART1_17, |
| 1752 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1753 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 1754 | PINCTRL_GRP_SDIO0_1BIT_2_1, |
| 1755 | END_OF_GROUPS, |
| 1756 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1757 | }, |
| 1758 | [PINCTRL_PIN_69] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1759 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1760 | PINCTRL_GRP_ETHERNET3_0, |
| 1761 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1762 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1763 | PINCTRL_GRP_SDIO1_1_WP, |
| 1764 | PINCTRL_GRP_RESERVED, |
| 1765 | PINCTRL_GRP_GPIO0_69, |
| 1766 | PINCTRL_GRP_CAN1_17, |
| 1767 | PINCTRL_GRP_I2C1_17, |
| 1768 | PINCTRL_GRP_SWDT1_11_RST, |
| 1769 | PINCTRL_GRP_SPI0_5, |
| 1770 | PINCTRL_GRP_TTC1_8_WAV, |
| 1771 | PINCTRL_GRP_UART1_17, |
| 1772 | PINCTRL_GRP_TRACE0_2, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1773 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 1774 | PINCTRL_GRP_SDIO0_1BIT_2_2, |
| 1775 | END_OF_GROUPS, |
| 1776 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1777 | }, |
| 1778 | [PINCTRL_PIN_70] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1779 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1780 | PINCTRL_GRP_ETHERNET3_0, |
| 1781 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1782 | PINCTRL_GRP_SDIO0_2, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1783 | PINCTRL_GRP_SDIO1_1_PC, |
| 1784 | PINCTRL_GRP_RESERVED, |
| 1785 | PINCTRL_GRP_GPIO0_70, |
| 1786 | PINCTRL_GRP_CAN0_17, |
| 1787 | PINCTRL_GRP_I2C0_17, |
| 1788 | PINCTRL_GRP_SWDT0_11_CLK, |
| 1789 | PINCTRL_GRP_SPI1_5, |
| 1790 | PINCTRL_GRP_TTC0_8_CLK, |
| 1791 | PINCTRL_GRP_UART0_17, |
| 1792 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1793 | PINCTRL_GRP_SDIO0_4BIT_2_0, |
| 1794 | PINCTRL_GRP_SDIO0_1BIT_2_3, |
| 1795 | END_OF_GROUPS, |
| 1796 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1797 | }, |
| 1798 | [PINCTRL_PIN_71] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1799 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1800 | PINCTRL_GRP_ETHERNET3_0, |
| 1801 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1802 | PINCTRL_GRP_SDIO0_2, |
| 1803 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1804 | PINCTRL_GRP_RESERVED, |
| 1805 | PINCTRL_GRP_GPIO0_71, |
| 1806 | PINCTRL_GRP_CAN0_17, |
| 1807 | PINCTRL_GRP_I2C0_17, |
| 1808 | PINCTRL_GRP_SWDT0_11_RST, |
| 1809 | PINCTRL_GRP_SPI1_5_SS2, |
| 1810 | PINCTRL_GRP_TTC0_8_WAV, |
| 1811 | PINCTRL_GRP_UART0_17, |
| 1812 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1813 | PINCTRL_GRP_SDIO0_2, |
| 1814 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 1815 | PINCTRL_GRP_SDIO0_1BIT_2_4, |
| 1816 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 1817 | END_OF_GROUPS, |
| 1818 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1819 | }, |
| 1820 | [PINCTRL_PIN_72] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1821 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1822 | PINCTRL_GRP_ETHERNET3_0, |
| 1823 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1824 | PINCTRL_GRP_SDIO0_2, |
| 1825 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1826 | PINCTRL_GRP_RESERVED, |
| 1827 | PINCTRL_GRP_GPIO0_72, |
| 1828 | PINCTRL_GRP_CAN1_18, |
| 1829 | PINCTRL_GRP_I2C1_18, |
| 1830 | PINCTRL_GRP_SWDT1_12_CLK, |
| 1831 | PINCTRL_GRP_SPI1_5_SS1, |
| 1832 | PINCTRL_GRP_RESERVED, |
| 1833 | PINCTRL_GRP_UART1_18, |
| 1834 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1835 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 1836 | PINCTRL_GRP_SDIO0_1BIT_2_5, |
| 1837 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 1838 | END_OF_GROUPS, |
| 1839 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1840 | }, |
| 1841 | [PINCTRL_PIN_73] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1842 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1843 | PINCTRL_GRP_ETHERNET3_0, |
| 1844 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1845 | PINCTRL_GRP_SDIO0_2, |
| 1846 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1847 | PINCTRL_GRP_RESERVED, |
| 1848 | PINCTRL_GRP_GPIO0_73, |
| 1849 | PINCTRL_GRP_CAN1_18, |
| 1850 | PINCTRL_GRP_I2C1_18, |
| 1851 | PINCTRL_GRP_SWDT1_12_RST, |
| 1852 | PINCTRL_GRP_SPI1_5_SS0, |
| 1853 | PINCTRL_GRP_RESERVED, |
| 1854 | PINCTRL_GRP_UART1_18, |
| 1855 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1856 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 1857 | PINCTRL_GRP_SDIO0_1BIT_2_6, |
| 1858 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 1859 | END_OF_GROUPS, |
| 1860 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1861 | }, |
| 1862 | [PINCTRL_PIN_74] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1863 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1864 | PINCTRL_GRP_ETHERNET3_0, |
| 1865 | PINCTRL_GRP_USB1_0, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1866 | PINCTRL_GRP_SDIO0_2, |
| 1867 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1868 | PINCTRL_GRP_RESERVED, |
| 1869 | PINCTRL_GRP_GPIO0_74, |
| 1870 | PINCTRL_GRP_CAN0_18, |
| 1871 | PINCTRL_GRP_I2C0_18, |
| 1872 | PINCTRL_GRP_SWDT0_12_CLK, |
| 1873 | PINCTRL_GRP_SPI1_5, |
| 1874 | PINCTRL_GRP_RESERVED, |
| 1875 | PINCTRL_GRP_UART0_18, |
| 1876 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1877 | PINCTRL_GRP_SDIO0_4BIT_2_1, |
| 1878 | PINCTRL_GRP_SDIO0_1BIT_2_7, |
| 1879 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
| 1880 | END_OF_GROUPS, |
| 1881 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1882 | }, |
| 1883 | [PINCTRL_PIN_75] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1884 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1885 | PINCTRL_GRP_ETHERNET3_0, |
| 1886 | PINCTRL_GRP_USB1_0, |
| 1887 | PINCTRL_GRP_SDIO0_2_PC, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1888 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1889 | PINCTRL_GRP_RESERVED, |
| 1890 | PINCTRL_GRP_GPIO0_75, |
| 1891 | PINCTRL_GRP_CAN0_18, |
| 1892 | PINCTRL_GRP_I2C0_18, |
| 1893 | PINCTRL_GRP_SWDT0_12_RST, |
| 1894 | PINCTRL_GRP_SPI1_5, |
| 1895 | PINCTRL_GRP_RESERVED, |
| 1896 | PINCTRL_GRP_UART0_18, |
| 1897 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1898 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 1899 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 1900 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 1901 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
| 1902 | END_OF_GROUPS, |
| 1903 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1904 | }, |
| 1905 | [PINCTRL_PIN_76] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1906 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1907 | PINCTRL_GRP_RESERVED, |
| 1908 | PINCTRL_GRP_RESERVED, |
| 1909 | PINCTRL_GRP_SDIO0_2_WP, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1910 | PINCTRL_GRP_SDIO1_4BIT_1_0, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1911 | PINCTRL_GRP_RESERVED, |
| 1912 | PINCTRL_GRP_GPIO0_76, |
| 1913 | PINCTRL_GRP_CAN1_19, |
| 1914 | PINCTRL_GRP_I2C1_19, |
| 1915 | PINCTRL_GRP_MDIO0_0, |
| 1916 | PINCTRL_GRP_MDIO1_1, |
| 1917 | PINCTRL_GRP_MDIO2_0, |
| 1918 | PINCTRL_GRP_MDIO3_0, |
| 1919 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1920 | PINCTRL_GRP_SDIO1_1BIT_1_0, |
| 1921 | PINCTRL_GRP_SDIO1_1BIT_1_1, |
| 1922 | PINCTRL_GRP_SDIO1_1BIT_1_2, |
| 1923 | PINCTRL_GRP_SDIO1_1BIT_1_3, |
| 1924 | END_OF_GROUPS, |
| 1925 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1926 | }, |
| 1927 | [PINCTRL_PIN_77] = { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1928 | .groups = &((uint16_t []) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1929 | PINCTRL_GRP_RESERVED, |
| 1930 | PINCTRL_GRP_RESERVED, |
| 1931 | PINCTRL_GRP_RESERVED, |
| 1932 | PINCTRL_GRP_SDIO1_1_CD, |
| 1933 | PINCTRL_GRP_RESERVED, |
| 1934 | PINCTRL_GRP_GPIO0_77, |
| 1935 | PINCTRL_GRP_CAN1_19, |
| 1936 | PINCTRL_GRP_I2C1_19, |
| 1937 | PINCTRL_GRP_MDIO0_0, |
| 1938 | PINCTRL_GRP_MDIO1_1, |
| 1939 | PINCTRL_GRP_MDIO2_0, |
| 1940 | PINCTRL_GRP_MDIO3_0, |
| 1941 | PINCTRL_GRP_RESERVED, |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 1942 | END_OF_GROUPS, |
| 1943 | }), |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1944 | }, |
| 1945 | }; |
| 1946 | |
| 1947 | /** |
| 1948 | * pm_api_pinctrl_get_num_pins() - PM call to request number of pins |
| 1949 | * @npins Number of pins |
| 1950 | * |
| 1951 | * This function is used by master to get number of pins |
| 1952 | * |
| 1953 | * @return Returns success. |
| 1954 | */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 1955 | enum pm_ret_status pm_api_pinctrl_get_num_pins(uint32_t *npins) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1956 | { |
| 1957 | *npins = MAX_PIN; |
| 1958 | |
| 1959 | return PM_RET_SUCCESS; |
| 1960 | } |
| 1961 | |
| 1962 | /** |
| 1963 | * pm_api_pinctrl_get_num_functions() - PM call to request number of functions |
| 1964 | * @nfuncs Number of functions |
| 1965 | * |
| 1966 | * This function is used by master to get number of functions |
| 1967 | * |
| 1968 | * @return Returns success. |
| 1969 | */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 1970 | enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1971 | { |
| 1972 | *nfuncs = MAX_FUNCTION; |
| 1973 | |
| 1974 | return PM_RET_SUCCESS; |
| 1975 | } |
| 1976 | |
| 1977 | /** |
| 1978 | * pm_api_pinctrl_get_num_func_groups() - PM call to request number of |
| 1979 | * function groups |
| 1980 | * @fid Function Id |
| 1981 | * @ngroups Number of function groups |
| 1982 | * |
| 1983 | * This function is used by master to get number of function groups |
| 1984 | * |
| 1985 | * @return Returns success. |
| 1986 | */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 1987 | enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid, |
| 1988 | uint32_t *ngroups) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1989 | { |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 1990 | if (fid >= MAX_FUNCTION) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1991 | return PM_RET_ERROR_ARGS; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 1992 | } |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1993 | |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 1994 | *ngroups = pinctrl_functions[fid].group_size; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 1995 | |
| 1996 | return PM_RET_SUCCESS; |
| 1997 | } |
| 1998 | |
| 1999 | /** |
| 2000 | * pm_api_pinctrl_get_function_name() - PM call to request a function name |
| 2001 | * @fid Function ID |
| 2002 | * @name Name of function (max 16 bytes) |
| 2003 | * |
| 2004 | * This function is used by master to get name of function specified |
| 2005 | * by given function ID. |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2006 | */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 2007 | void pm_api_pinctrl_get_function_name(uint32_t fid, char *name) |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2008 | { |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2009 | if (fid >= MAX_FUNCTION) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2010 | memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2011 | } else { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2012 | memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2013 | } |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2014 | } |
| 2015 | |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2016 | /** |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2017 | * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function |
| 2018 | * groups of function Id |
| 2019 | * @fid Function ID |
| 2020 | * @index Index of next function groups |
| 2021 | * @groups Function groups |
| 2022 | * |
| 2023 | * This function is used by master to get function groups specified |
| 2024 | * by given function Id. This API will return 6 function groups with |
| 2025 | * a single response. To get other function groups, master should call |
| 2026 | * same API in loop with new function groups index till error is returned. |
| 2027 | * |
| 2028 | * E.g First call should have index 0 which will return function groups |
| 2029 | * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return |
| 2030 | * function groups 6, 7, 8, 9, 10 and 11 and so on. |
| 2031 | * |
| 2032 | * Return: Returns status, either success or error+reason. |
| 2033 | */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 2034 | enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid, |
| 2035 | uint32_t index, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2036 | uint16_t *groups) |
| 2037 | { |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 2038 | uint16_t grps; |
| 2039 | uint16_t end_of_grp_offset; |
HariBabu Gattem | 9f9db61 | 2022-09-15 22:35:11 -0700 | [diff] [blame] | 2040 | uint16_t i; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2041 | |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2042 | if (fid >= MAX_FUNCTION) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2043 | return PM_RET_ERROR_ARGS; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2044 | } |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2045 | |
| 2046 | memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); |
| 2047 | |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 2048 | grps = pinctrl_functions[fid].group_base; |
| 2049 | end_of_grp_offset = grps + pinctrl_functions[fid].group_size; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2050 | |
HariBabu Gattem | 9f9db61 | 2022-09-15 22:35:11 -0700 | [diff] [blame] | 2051 | for (i = 0U; i < NUM_GROUPS_PER_RESP; i++) { |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 2052 | if ((grps + index + i) >= end_of_grp_offset) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2053 | break; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2054 | } |
Ronak Jain | 0ac9078 | 2022-05-06 04:45:59 -0700 | [diff] [blame] | 2055 | groups[i] = (grps + index + i); |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2056 | } |
| 2057 | |
| 2058 | return PM_RET_SUCCESS; |
| 2059 | } |
| 2060 | |
| 2061 | /** |
| 2062 | * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin |
| 2063 | * groups of pin |
| 2064 | * @pin Pin |
| 2065 | * @index Index of next pin groups |
| 2066 | * @groups pin groups |
| 2067 | * |
| 2068 | * This function is used by master to get pin groups specified |
| 2069 | * by given pin Id. This API will return 6 pin groups with |
| 2070 | * a single response. To get other pin groups, master should call |
| 2071 | * same API in loop with new pin groups index till error is returned. |
| 2072 | * |
| 2073 | * E.g First call should have index 0 which will return pin groups |
| 2074 | * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return |
| 2075 | * pin groups 6, 7, 8, 9, 10 and 11 and so on. |
| 2076 | * |
| 2077 | * Return: Returns status, either success or error+reason. |
| 2078 | */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 2079 | enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin, |
| 2080 | uint32_t index, |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2081 | uint16_t *groups) |
| 2082 | { |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 2083 | uint32_t i; |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2084 | uint16_t *grps; |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2085 | |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2086 | if (pin >= MAX_PIN) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2087 | return PM_RET_ERROR_ARGS; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2088 | } |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2089 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2090 | memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); |
| 2091 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2092 | grps = *zynqmp_pin_groups[pin].groups; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2093 | if (grps == NULL) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2094 | return PM_RET_SUCCESS; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2095 | } |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2096 | |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2097 | /* Skip groups till index */ |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2098 | for (i = 0; i < index; i++) { |
| 2099 | if (grps[i] == (uint16_t)END_OF_GROUPS) { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2100 | return PM_RET_SUCCESS; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2101 | } |
| 2102 | } |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2103 | |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2104 | for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2105 | groups[i] = grps[index + i]; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2106 | if (groups[i] == (uint16_t)END_OF_GROUPS) { |
Rajan Vaja | c82ce46 | 2018-02-22 01:06:52 -0800 | [diff] [blame] | 2107 | break; |
Venkatesh Yadav Abbarapu | 987fad3 | 2022-04-29 13:52:00 +0530 | [diff] [blame] | 2108 | } |
Rajan Vaja | d5dd836 | 2018-01-30 04:16:31 -0800 | [diff] [blame] | 2109 | } |
| 2110 | |
| 2111 | return PM_RET_SUCCESS; |
| 2112 | } |