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git01.mediatek.com / filogic / atf / d5dd8367fdb5fa8187e236c66100a54e56422528 / . / plat / xilinx / zynqmp / pm_service / pm_api_pinctrl.c
blob: 97c50c436c47f600038eb376019212dc91a4ca34 [file] [log] [blame]
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]1/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * ZynqMP system level PM-API functions for pin control.
9 */
10
11#include <arch_helpers.h>
12#include <platform.h>
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]13#include <string.h>
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]14#include "pm_api_pinctrl.h"
15#include "pm_api_sys.h"
16#include "pm_client.h"
17#include "pm_common.h"
18#include "pm_ipi.h"
19
20#define PINCTRL_FUNCTION_MASK 0xFE
Rajan Vaja5e139e72018-01-17 02:39:22 -0800[diff] [blame]21#define PINCTRL_VOLTAGE_STATUS_MASK 0x01
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]22#define NFUNCS_PER_PIN 13
Rajan Vaja5e139e72018-01-17 02:39:22 -0800[diff] [blame]23#define PINCTRL_NUM_MIOS 78
24#define MAX_PIN_PER_REG 26
25#define PINCTRL_BANK_ADDR_STEP 28
26
27#define PINCTRL_DRVSTRN0_REG_OFFSET 0
28#define PINCTRL_DRVSTRN1_REG_OFFSET 4
29#define PINCTRL_SCHCMOS_REG_OFFSET 8
30#define PINCTRL_PULLCTRL_REG_OFFSET 12
31#define PINCTRL_PULLSTAT_REG_OFFSET 16
32#define PINCTRL_SLEWCTRL_REG_OFFSET 20
33#define PINCTRL_VOLTAGE_STAT_REG_OFFSET 24
34
35#define IOU_SLCR_BANK1_CTRL5 0XFF180164
36
37#define PINCTRL_CFG_ADDR_OFFSET(addr, reg, pin) \
38 ((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \
39 ((pin) / MAX_PIN_PER_REG) + (reg))
40
41#define PINCTRL_PIN_OFFSET(pin) \
42 ((pin) - (MAX_PIN_PER_REG * ((pin) / MAX_PIN_PER_REG)))
43
44#define PINCTRL_REGVAL_TO_PIN_CONFIG(pin, value) \
45 (((value) >> PINCTRL_PIN_OFFSET(pin)) & 0x1)
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]46
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]47static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = {
48 0x02, 0x04, 0x08, 0x10, 0x18,
49 0x00, 0x20, 0x40, 0x60, 0x80,
50 0xA0, 0xC0, 0xE0
51};
52
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]53struct pinctrl_function {
54 char name[FUNCTION_NAME_LEN];
55 uint16_t (*groups)[];
56 uint8_t regval;
57};
58
59/* Max groups for one pin */
60#define MAX_PIN_GROUPS 13
61
62struct zynqmp_pin_group {
63 uint16_t groups[MAX_PIN_GROUPS];
64};
65
66static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = {
67 [PINCTRL_FUNC_CAN0] = {
68 .name = "can0",
69 .regval = 0x20,
70 .groups = &((uint16_t []) {
71 PINCTRL_GRP_CAN0_0,
72 PINCTRL_GRP_CAN0_1,
73 PINCTRL_GRP_CAN0_2,
74 PINCTRL_GRP_CAN0_3,
75 PINCTRL_GRP_CAN0_4,
76 PINCTRL_GRP_CAN0_5,
77 PINCTRL_GRP_CAN0_6,
78 PINCTRL_GRP_CAN0_7,
79 PINCTRL_GRP_CAN0_8,
80 PINCTRL_GRP_CAN0_9,
81 PINCTRL_GRP_CAN0_10,
82 PINCTRL_GRP_CAN0_11,
83 PINCTRL_GRP_CAN0_12,
84 PINCTRL_GRP_CAN0_13,
85 PINCTRL_GRP_CAN0_14,
86 PINCTRL_GRP_CAN0_15,
87 PINCTRL_GRP_CAN0_16,
88 PINCTRL_GRP_CAN0_17,
89 PINCTRL_GRP_CAN0_18,
90 END_OF_GROUPS,
91 }),
92 },
93 [PINCTRL_FUNC_CAN1] = {
94 .name = "can1",
95 .regval = 0x20,
96 .groups = &((uint16_t []) {
97 PINCTRL_GRP_CAN1_0,
98 PINCTRL_GRP_CAN1_1,
99 PINCTRL_GRP_CAN1_2,
100 PINCTRL_GRP_CAN1_3,
101 PINCTRL_GRP_CAN1_4,
102 PINCTRL_GRP_CAN1_5,
103 PINCTRL_GRP_CAN1_6,
104 PINCTRL_GRP_CAN1_7,
105 PINCTRL_GRP_CAN1_8,
106 PINCTRL_GRP_CAN1_9,
107 PINCTRL_GRP_CAN1_10,
108 PINCTRL_GRP_CAN1_11,
109 PINCTRL_GRP_CAN1_12,
110 PINCTRL_GRP_CAN1_13,
111 PINCTRL_GRP_CAN1_14,
112 PINCTRL_GRP_CAN1_15,
113 PINCTRL_GRP_CAN1_16,
114 PINCTRL_GRP_CAN1_17,
115 PINCTRL_GRP_CAN1_18,
116 PINCTRL_GRP_CAN1_19,
117 END_OF_GROUPS,
118 }),
119 },
120 [PINCTRL_FUNC_ETHERNET0] = {
121 .name = "ethernet0",
122 .regval = 0x02,
123 .groups = &((uint16_t []) {
124 PINCTRL_GRP_ETHERNET0_0,
125 END_OF_GROUPS,
126 }),
127 },
128 [PINCTRL_FUNC_ETHERNET1] = {
129 .name = "ethernet1",
130 .regval = 0x02,
131 .groups = &((uint16_t []) {
132 PINCTRL_GRP_ETHERNET1_0,
133 END_OF_GROUPS,
134 }),
135 },
136 [PINCTRL_FUNC_ETHERNET2] = {
137 .name = "ethernet2",
138 .regval = 0x02,
139 .groups = &((uint16_t []) {
140 PINCTRL_GRP_ETHERNET2_0,
141 END_OF_GROUPS,
142 }),
143 },
144 [PINCTRL_FUNC_ETHERNET3] = {
145 .name = "ethernet3",
146 .regval = 0x02,
147 .groups = &((uint16_t []) {
148 PINCTRL_GRP_ETHERNET3_0,
149 END_OF_GROUPS,
150 }),
151 },
152 [PINCTRL_FUNC_GEMTSU0] = {
153 .name = "gemtsu0",
154 .regval = 0x02,
155 .groups = &((uint16_t []) {
156 PINCTRL_GRP_GEMTSU0_0,
157 PINCTRL_GRP_GEMTSU0_1,
158 PINCTRL_GRP_GEMTSU0_2,
159 END_OF_GROUPS,
160 }),
161 },
162 [PINCTRL_FUNC_GPIO0] = {
163 .name = "gpio0",
164 .regval = 0x00,
165 .groups = &((uint16_t []) {
166 PINCTRL_GRP_GPIO0_0,
167 PINCTRL_GRP_GPIO0_1,
168 PINCTRL_GRP_GPIO0_2,
169 PINCTRL_GRP_GPIO0_3,
170 PINCTRL_GRP_GPIO0_4,
171 PINCTRL_GRP_GPIO0_5,
172 PINCTRL_GRP_GPIO0_6,
173 PINCTRL_GRP_GPIO0_7,
174 PINCTRL_GRP_GPIO0_8,
175 PINCTRL_GRP_GPIO0_9,
176 PINCTRL_GRP_GPIO0_10,
177 PINCTRL_GRP_GPIO0_11,
178 PINCTRL_GRP_GPIO0_12,
179 PINCTRL_GRP_GPIO0_13,
180 PINCTRL_GRP_GPIO0_14,
181 PINCTRL_GRP_GPIO0_15,
182 PINCTRL_GRP_GPIO0_16,
183 PINCTRL_GRP_GPIO0_17,
184 PINCTRL_GRP_GPIO0_18,
185 PINCTRL_GRP_GPIO0_19,
186 PINCTRL_GRP_GPIO0_20,
187 PINCTRL_GRP_GPIO0_21,
188 PINCTRL_GRP_GPIO0_22,
189 PINCTRL_GRP_GPIO0_23,
190 PINCTRL_GRP_GPIO0_24,
191 PINCTRL_GRP_GPIO0_25,
192 PINCTRL_GRP_GPIO0_26,
193 PINCTRL_GRP_GPIO0_27,
194 PINCTRL_GRP_GPIO0_28,
195 PINCTRL_GRP_GPIO0_29,
196 PINCTRL_GRP_GPIO0_30,
197 PINCTRL_GRP_GPIO0_31,
198 PINCTRL_GRP_GPIO0_32,
199 PINCTRL_GRP_GPIO0_33,
200 PINCTRL_GRP_GPIO0_34,
201 PINCTRL_GRP_GPIO0_35,
202 PINCTRL_GRP_GPIO0_36,
203 PINCTRL_GRP_GPIO0_37,
204 PINCTRL_GRP_GPIO0_38,
205 PINCTRL_GRP_GPIO0_39,
206 PINCTRL_GRP_GPIO0_40,
207 PINCTRL_GRP_GPIO0_41,
208 PINCTRL_GRP_GPIO0_42,
209 PINCTRL_GRP_GPIO0_43,
210 PINCTRL_GRP_GPIO0_44,
211 PINCTRL_GRP_GPIO0_45,
212 PINCTRL_GRP_GPIO0_46,
213 PINCTRL_GRP_GPIO0_47,
214 PINCTRL_GRP_GPIO0_48,
215 PINCTRL_GRP_GPIO0_49,
216 PINCTRL_GRP_GPIO0_50,
217 PINCTRL_GRP_GPIO0_51,
218 PINCTRL_GRP_GPIO0_52,
219 PINCTRL_GRP_GPIO0_53,
220 PINCTRL_GRP_GPIO0_54,
221 PINCTRL_GRP_GPIO0_55,
222 PINCTRL_GRP_GPIO0_56,
223 PINCTRL_GRP_GPIO0_57,
224 PINCTRL_GRP_GPIO0_58,
225 PINCTRL_GRP_GPIO0_59,
226 PINCTRL_GRP_GPIO0_60,
227 PINCTRL_GRP_GPIO0_61,
228 PINCTRL_GRP_GPIO0_62,
229 PINCTRL_GRP_GPIO0_63,
230 PINCTRL_GRP_GPIO0_64,
231 PINCTRL_GRP_GPIO0_65,
232 PINCTRL_GRP_GPIO0_66,
233 PINCTRL_GRP_GPIO0_67,
234 PINCTRL_GRP_GPIO0_68,
235 PINCTRL_GRP_GPIO0_69,
236 PINCTRL_GRP_GPIO0_70,
237 PINCTRL_GRP_GPIO0_71,
238 PINCTRL_GRP_GPIO0_72,
239 PINCTRL_GRP_GPIO0_73,
240 PINCTRL_GRP_GPIO0_74,
241 PINCTRL_GRP_GPIO0_75,
242 PINCTRL_GRP_GPIO0_76,
243 PINCTRL_GRP_GPIO0_77,
244 END_OF_GROUPS,
245 }),
246 },
247 [PINCTRL_FUNC_I2C0] = {
248 .name = "i2c0",
249 .regval = 0x40,
250 .groups = &((uint16_t []) {
251 PINCTRL_GRP_I2C0_0,
252 PINCTRL_GRP_I2C0_1,
253 PINCTRL_GRP_I2C0_2,
254 PINCTRL_GRP_I2C0_3,
255 PINCTRL_GRP_I2C0_4,
256 PINCTRL_GRP_I2C0_5,
257 PINCTRL_GRP_I2C0_6,
258 PINCTRL_GRP_I2C0_7,
259 PINCTRL_GRP_I2C0_8,
260 PINCTRL_GRP_I2C0_9,
261 PINCTRL_GRP_I2C0_10,
262 PINCTRL_GRP_I2C0_11,
263 PINCTRL_GRP_I2C0_12,
264 PINCTRL_GRP_I2C0_13,
265 PINCTRL_GRP_I2C0_14,
266 PINCTRL_GRP_I2C0_15,
267 PINCTRL_GRP_I2C0_16,
268 PINCTRL_GRP_I2C0_17,
269 PINCTRL_GRP_I2C0_18,
270 END_OF_GROUPS,
271 }),
272 },
273 [PINCTRL_FUNC_I2C1] = {
274 .name = "i2c1",
275 .regval = 0x40,
276 .groups = &((uint16_t []) {
277 PINCTRL_GRP_I2C1_0,
278 PINCTRL_GRP_I2C1_1,
279 PINCTRL_GRP_I2C1_2,
280 PINCTRL_GRP_I2C1_3,
281 PINCTRL_GRP_I2C1_4,
282 PINCTRL_GRP_I2C1_5,
283 PINCTRL_GRP_I2C1_6,
284 PINCTRL_GRP_I2C1_7,
285 PINCTRL_GRP_I2C1_8,
286 PINCTRL_GRP_I2C1_9,
287 PINCTRL_GRP_I2C1_10,
288 PINCTRL_GRP_I2C1_11,
289 PINCTRL_GRP_I2C1_12,
290 PINCTRL_GRP_I2C1_13,
291 PINCTRL_GRP_I2C1_14,
292 PINCTRL_GRP_I2C1_15,
293 PINCTRL_GRP_I2C1_16,
294 PINCTRL_GRP_I2C1_17,
295 PINCTRL_GRP_I2C1_18,
296 PINCTRL_GRP_I2C1_19,
297 END_OF_GROUPS,
298 }),
299 },
300 [PINCTRL_FUNC_MDIO0] = {
301 .name = "mdio0",
302 .regval = 0x60,
303 .groups = &((uint16_t []) {
304 PINCTRL_GRP_MDIO0_0,
305 END_OF_GROUPS,
306 }),
307 },
308 [PINCTRL_FUNC_MDIO1] = {
309 .name = "mdio1",
310 .regval = 0x80,
311 .groups = &((uint16_t []) {
312 PINCTRL_GRP_MDIO1_0,
313 PINCTRL_GRP_MDIO1_1,
314 END_OF_GROUPS,
315 }),
316 },
317 [PINCTRL_FUNC_MDIO2] = {
318 .name = "mdio2",
319 .regval = 0xa0,
320 .groups = &((uint16_t []) {
321 PINCTRL_GRP_MDIO2_0,
322 END_OF_GROUPS,
323 }),
324 },
325 [PINCTRL_FUNC_MDIO3] = {
326 .name = "mdio3",
327 .regval = 0xc0,
328 .groups = &((uint16_t []) {
329 PINCTRL_GRP_MDIO3_0,
330 END_OF_GROUPS,
331 }),
332 },
333 [PINCTRL_FUNC_QSPI0] = {
334 .name = "qspi0",
335 .regval = 0x02,
336 .groups = &((uint16_t []) {
337 PINCTRL_GRP_QSPI0_0,
338 END_OF_GROUPS,
339 }),
340 },
341 [PINCTRL_FUNC_QSPI_FBCLK] = {
342 .name = "qspi_fbclk",
343 .regval = 0x02,
344 .groups = &((uint16_t []) {
345 PINCTRL_GRP_QSPI_FBCLK,
346 END_OF_GROUPS,
347 }),
348 },
349 [PINCTRL_FUNC_QSPI_SS] = {
350 .name = "qspi_ss",
351 .regval = 0x02,
352 .groups = &((uint16_t []) {
353 PINCTRL_GRP_QSPI_SS,
354 END_OF_GROUPS,
355 }),
356 },
357 [PINCTRL_FUNC_SPI0] = {
358 .name = "spi0",
359 .regval = 0x80,
360 .groups = &((uint16_t []) {
361 PINCTRL_GRP_SPI0_0,
362 PINCTRL_GRP_SPI0_1,
363 PINCTRL_GRP_SPI0_2,
364 PINCTRL_GRP_SPI0_3,
365 PINCTRL_GRP_SPI0_4,
366 PINCTRL_GRP_SPI0_5,
367 END_OF_GROUPS,
368 }),
369 },
370 [PINCTRL_FUNC_SPI1] = {
371 .name = "spi1",
372 .regval = 0x80,
373 .groups = &((uint16_t []) {
374 PINCTRL_GRP_SPI1_0,
375 PINCTRL_GRP_SPI1_1,
376 PINCTRL_GRP_SPI1_2,
377 PINCTRL_GRP_SPI1_3,
378 PINCTRL_GRP_SPI1_4,
379 PINCTRL_GRP_SPI1_5,
380 END_OF_GROUPS,
381 }),
382 },
383 [PINCTRL_FUNC_SPI0_SS] = {
384 .name = "spi0_ss",
385 .regval = 0x80,
386 .groups = &((uint16_t []) {
387 PINCTRL_GRP_SPI0_0_SS0,
388 PINCTRL_GRP_SPI0_0_SS1,
389 PINCTRL_GRP_SPI0_0_SS2,
390 PINCTRL_GRP_SPI0_1_SS0,
391 PINCTRL_GRP_SPI0_1_SS1,
392 PINCTRL_GRP_SPI0_1_SS2,
393 PINCTRL_GRP_SPI0_2_SS0,
394 PINCTRL_GRP_SPI0_2_SS1,
395 PINCTRL_GRP_SPI0_2_SS2,
396 PINCTRL_GRP_SPI0_3_SS0,
397 PINCTRL_GRP_SPI0_3_SS1,
398 PINCTRL_GRP_SPI0_3_SS2,
399 PINCTRL_GRP_SPI0_4_SS0,
400 PINCTRL_GRP_SPI0_4_SS1,
401 PINCTRL_GRP_SPI0_4_SS2,
402 PINCTRL_GRP_SPI0_5_SS0,
403 PINCTRL_GRP_SPI0_5_SS1,
404 PINCTRL_GRP_SPI0_5_SS2,
405 END_OF_GROUPS,
406 }),
407 },
408 [PINCTRL_FUNC_SPI1_SS] = {
409 .name = "spi1_ss",
410 .regval = 0x80,
411 .groups = &((uint16_t []) {
412 PINCTRL_GRP_SPI1_0_SS0,
413 PINCTRL_GRP_SPI1_0_SS1,
414 PINCTRL_GRP_SPI1_0_SS2,
415 PINCTRL_GRP_SPI1_1_SS0,
416 PINCTRL_GRP_SPI1_1_SS1,
417 PINCTRL_GRP_SPI1_1_SS2,
418 PINCTRL_GRP_SPI1_2_SS0,
419 PINCTRL_GRP_SPI1_2_SS1,
420 PINCTRL_GRP_SPI1_2_SS2,
421 PINCTRL_GRP_SPI1_3_SS0,
422 PINCTRL_GRP_SPI1_3_SS1,
423 PINCTRL_GRP_SPI1_3_SS2,
424 PINCTRL_GRP_SPI1_4_SS0,
425 PINCTRL_GRP_SPI1_4_SS1,
426 PINCTRL_GRP_SPI1_4_SS2,
427 PINCTRL_GRP_SPI1_5_SS0,
428 PINCTRL_GRP_SPI1_5_SS1,
429 PINCTRL_GRP_SPI1_5_SS2,
430 END_OF_GROUPS,
431 }),
432 },
433 [PINCTRL_FUNC_SDIO0] = {
434 .name = "sdio0",
435 .regval = 0x08,
436 .groups = &((uint16_t []) {
437 PINCTRL_GRP_SDIO0_0,
438 PINCTRL_GRP_SDIO0_1,
439 PINCTRL_GRP_SDIO0_2,
440 PINCTRL_GRP_SDIO0_4BIT_0_0,
441 PINCTRL_GRP_SDIO0_4BIT_0_1,
442 PINCTRL_GRP_SDIO0_4BIT_1_0,
443 PINCTRL_GRP_SDIO0_4BIT_1_1,
444 PINCTRL_GRP_SDIO0_4BIT_2_0,
445 PINCTRL_GRP_SDIO0_4BIT_2_1,
446 PINCTRL_GRP_SDIO0_1BIT_0_0,
447 PINCTRL_GRP_SDIO0_1BIT_0_1,
448 PINCTRL_GRP_SDIO0_1BIT_0_2,
449 PINCTRL_GRP_SDIO0_1BIT_0_3,
450 PINCTRL_GRP_SDIO0_1BIT_0_4,
451 PINCTRL_GRP_SDIO0_1BIT_0_5,
452 PINCTRL_GRP_SDIO0_1BIT_0_6,
453 PINCTRL_GRP_SDIO0_1BIT_0_7,
454 PINCTRL_GRP_SDIO0_1BIT_1_0,
455 PINCTRL_GRP_SDIO0_1BIT_1_1,
456 PINCTRL_GRP_SDIO0_1BIT_1_2,
457 PINCTRL_GRP_SDIO0_1BIT_1_3,
458 PINCTRL_GRP_SDIO0_1BIT_1_4,
459 PINCTRL_GRP_SDIO0_1BIT_1_5,
460 PINCTRL_GRP_SDIO0_1BIT_1_6,
461 PINCTRL_GRP_SDIO0_1BIT_1_7,
462 PINCTRL_GRP_SDIO0_1BIT_2_0,
463 PINCTRL_GRP_SDIO0_1BIT_2_1,
464 PINCTRL_GRP_SDIO0_1BIT_2_2,
465 PINCTRL_GRP_SDIO0_1BIT_2_3,
466 PINCTRL_GRP_SDIO0_1BIT_2_4,
467 PINCTRL_GRP_SDIO0_1BIT_2_5,
468 PINCTRL_GRP_SDIO0_1BIT_2_6,
469 PINCTRL_GRP_SDIO0_1BIT_2_7,
470 END_OF_GROUPS,
471 }),
472 },
473 [PINCTRL_FUNC_SDIO0_PC] = {
474 .name = "sdio0_pc",
475 .regval = 0x08,
476 .groups = &((uint16_t []) {
477 PINCTRL_GRP_SDIO0_0_PC,
478 PINCTRL_GRP_SDIO0_1_PC,
479 PINCTRL_GRP_SDIO0_2_PC,
480 END_OF_GROUPS,
481 }),
482 },
483 [PINCTRL_FUNC_SDIO0_CD] = {
484 .name = "sdio0_cd",
485 .regval = 0x08,
486 .groups = &((uint16_t []) {
487 PINCTRL_GRP_SDIO0_0_CD,
488 PINCTRL_GRP_SDIO0_1_CD,
489 PINCTRL_GRP_SDIO0_2_CD,
490 END_OF_GROUPS,
491 }),
492 },
493 [PINCTRL_FUNC_SDIO0_WP] = {
494 .name = "sdio0_wp",
495 .regval = 0x08,
496 .groups = &((uint16_t []) {
497 PINCTRL_GRP_SDIO0_0_WP,
498 PINCTRL_GRP_SDIO0_1_WP,
499 PINCTRL_GRP_SDIO0_2_WP,
500 END_OF_GROUPS,
501 }),
502 },
503 [PINCTRL_FUNC_SDIO1] = {
504 .name = "sdio1",
505 .regval = 0x10,
506 .groups = &((uint16_t []) {
507 PINCTRL_GRP_SDIO1_0,
508 PINCTRL_GRP_SDIO1_4BIT_0_0,
509 PINCTRL_GRP_SDIO1_4BIT_0_1,
510 PINCTRL_GRP_SDIO1_4BIT_1_0,
511 PINCTRL_GRP_SDIO1_1BIT_0_0,
512 PINCTRL_GRP_SDIO1_1BIT_0_1,
513 PINCTRL_GRP_SDIO1_1BIT_0_2,
514 PINCTRL_GRP_SDIO1_1BIT_0_3,
515 PINCTRL_GRP_SDIO1_1BIT_0_4,
516 PINCTRL_GRP_SDIO1_1BIT_0_5,
517 PINCTRL_GRP_SDIO1_1BIT_0_6,
518 PINCTRL_GRP_SDIO1_1BIT_0_7,
519 PINCTRL_GRP_SDIO1_1BIT_1_0,
520 PINCTRL_GRP_SDIO1_1BIT_1_1,
521 PINCTRL_GRP_SDIO1_1BIT_1_2,
522 PINCTRL_GRP_SDIO1_1BIT_1_3,
523 END_OF_GROUPS,
524 }),
525 },
526 [PINCTRL_FUNC_SDIO1_PC] = {
527 .name = "sdio1_pc",
528 .regval = 0x10,
529 .groups = &((uint16_t []) {
530 PINCTRL_GRP_SDIO1_0_PC,
531 PINCTRL_GRP_SDIO1_1_PC,
532 END_OF_GROUPS,
533 }),
534 },
535 [PINCTRL_FUNC_SDIO1_CD] = {
536 .name = "sdio1_cd",
537 .regval = 0x10,
538 .groups = &((uint16_t []) {
539 PINCTRL_GRP_SDIO1_0_CD,
540 PINCTRL_GRP_SDIO1_1_CD,
541 END_OF_GROUPS,
542 }),
543 },
544 [PINCTRL_FUNC_SDIO1_WP] = {
545 .name = "sdio1_wp",
546 .regval = 0x10,
547 .groups = &((uint16_t []) {
548 PINCTRL_GRP_SDIO1_0_WP,
549 PINCTRL_GRP_SDIO1_1_WP,
550 END_OF_GROUPS,
551 }),
552 },
553 [PINCTRL_FUNC_NAND0] = {
554 .name = "nand0",
555 .regval = 0x04,
556 .groups = &((uint16_t []) {
557 PINCTRL_GRP_NAND0_0,
558 END_OF_GROUPS,
559 }),
560 },
561 [PINCTRL_FUNC_NAND0_CE] = {
562 .name = "nand0_ce",
563 .regval = 0x04,
564 .groups = &((uint16_t []) {
565 PINCTRL_GRP_NAND0_0_CE,
566 PINCTRL_GRP_NAND0_1_CE,
567 END_OF_GROUPS,
568 }),
569 },
570 [PINCTRL_FUNC_NAND0_RB] = {
571 .name = "nand0_rb",
572 .regval = 0x04,
573 .groups = &((uint16_t []) {
574 PINCTRL_GRP_NAND0_0_RB,
575 PINCTRL_GRP_NAND0_1_RB,
576 END_OF_GROUPS,
577 }),
578 },
579 [PINCTRL_FUNC_NAND0_DQS] = {
580 .name = "nand0_dqs",
581 .regval = 0x04,
582 .groups = &((uint16_t []) {
583 PINCTRL_GRP_NAND0_0_DQS,
584 PINCTRL_GRP_NAND0_1_DQS,
585 END_OF_GROUPS,
586 }),
587 },
588 [PINCTRL_FUNC_TTC0_CLK] = {
589 .name = "ttc0_clk",
590 .regval = 0xa0,
591 .groups = &((uint16_t []) {
592 PINCTRL_GRP_TTC0_0_CLK,
593 PINCTRL_GRP_TTC0_1_CLK,
594 PINCTRL_GRP_TTC0_2_CLK,
595 PINCTRL_GRP_TTC0_3_CLK,
596 PINCTRL_GRP_TTC0_4_CLK,
597 PINCTRL_GRP_TTC0_5_CLK,
598 PINCTRL_GRP_TTC0_6_CLK,
599 PINCTRL_GRP_TTC0_7_CLK,
600 PINCTRL_GRP_TTC0_8_CLK,
601 END_OF_GROUPS,
602 }),
603 },
604 [PINCTRL_FUNC_TTC0_WAV] = {
605 .name = "ttc0_wav",
606 .regval = 0xa0,
607 .groups = &((uint16_t []) {
608 PINCTRL_GRP_TTC0_0_WAV,
609 PINCTRL_GRP_TTC0_1_WAV,
610 PINCTRL_GRP_TTC0_2_WAV,
611 PINCTRL_GRP_TTC0_3_WAV,
612 PINCTRL_GRP_TTC0_4_WAV,
613 PINCTRL_GRP_TTC0_5_WAV,
614 PINCTRL_GRP_TTC0_6_WAV,
615 PINCTRL_GRP_TTC0_7_WAV,
616 PINCTRL_GRP_TTC0_8_WAV,
617 END_OF_GROUPS,
618 }),
619 },
620 [PINCTRL_FUNC_TTC1_CLK] = {
621 .name = "ttc1_clk",
622 .regval = 0xa0,
623 .groups = &((uint16_t []) {
624 PINCTRL_GRP_TTC1_0_CLK,
625 PINCTRL_GRP_TTC1_1_CLK,
626 PINCTRL_GRP_TTC1_2_CLK,
627 PINCTRL_GRP_TTC1_3_CLK,
628 PINCTRL_GRP_TTC1_4_CLK,
629 PINCTRL_GRP_TTC1_5_CLK,
630 PINCTRL_GRP_TTC1_6_CLK,
631 PINCTRL_GRP_TTC1_7_CLK,
632 PINCTRL_GRP_TTC1_8_CLK,
633 END_OF_GROUPS,
634 }),
635 },
636 [PINCTRL_FUNC_TTC1_WAV] = {
637 .name = "ttc1_wav",
638 .regval = 0xa0,
639 .groups = &((uint16_t []) {
640 PINCTRL_GRP_TTC1_0_WAV,
641 PINCTRL_GRP_TTC1_1_WAV,
642 PINCTRL_GRP_TTC1_2_WAV,
643 PINCTRL_GRP_TTC1_3_WAV,
644 PINCTRL_GRP_TTC1_4_WAV,
645 PINCTRL_GRP_TTC1_5_WAV,
646 PINCTRL_GRP_TTC1_6_WAV,
647 PINCTRL_GRP_TTC1_7_WAV,
648 PINCTRL_GRP_TTC1_8_WAV,
649 END_OF_GROUPS,
650 }),
651 },
652 [PINCTRL_FUNC_TTC2_CLK] = {
653 .name = "ttc2_clk",
654 .regval = 0xa0,
655 .groups = &((uint16_t []) {
656 PINCTRL_GRP_TTC2_0_CLK,
657 PINCTRL_GRP_TTC2_1_CLK,
658 PINCTRL_GRP_TTC2_2_CLK,
659 PINCTRL_GRP_TTC2_3_CLK,
660 PINCTRL_GRP_TTC2_4_CLK,
661 PINCTRL_GRP_TTC2_5_CLK,
662 PINCTRL_GRP_TTC2_6_CLK,
663 PINCTRL_GRP_TTC2_7_CLK,
664 PINCTRL_GRP_TTC2_8_CLK,
665 END_OF_GROUPS,
666 }),
667 },
668 [PINCTRL_FUNC_TTC2_WAV] = {
669 .name = "ttc2_wav",
670 .regval = 0xa0,
671 .groups = &((uint16_t []) {
672 PINCTRL_GRP_TTC2_0_WAV,
673 PINCTRL_GRP_TTC2_1_WAV,
674 PINCTRL_GRP_TTC2_2_WAV,
675 PINCTRL_GRP_TTC2_3_WAV,
676 PINCTRL_GRP_TTC2_4_WAV,
677 PINCTRL_GRP_TTC2_5_WAV,
678 PINCTRL_GRP_TTC2_6_WAV,
679 PINCTRL_GRP_TTC2_7_WAV,
680 PINCTRL_GRP_TTC2_8_WAV,
681 END_OF_GROUPS,
682 }),
683 },
684 [PINCTRL_FUNC_TTC3_CLK] = {
685 .name = "ttc3_clk",
686 .regval = 0xa0,
687 .groups = &((uint16_t []) {
688 PINCTRL_GRP_TTC3_0_CLK,
689 PINCTRL_GRP_TTC3_1_CLK,
690 PINCTRL_GRP_TTC3_2_CLK,
691 PINCTRL_GRP_TTC3_3_CLK,
692 PINCTRL_GRP_TTC3_4_CLK,
693 PINCTRL_GRP_TTC3_5_CLK,
694 PINCTRL_GRP_TTC3_6_CLK,
695 PINCTRL_GRP_TTC3_7_CLK,
696 PINCTRL_GRP_TTC3_8_CLK,
697 END_OF_GROUPS,
698 }),
699 },
700 [PINCTRL_FUNC_TTC3_WAV] = {
701 .name = "ttc3_wav",
702 .regval = 0xa0,
703 .groups = &((uint16_t []) {
704 PINCTRL_GRP_TTC3_0_WAV,
705 PINCTRL_GRP_TTC3_1_WAV,
706 PINCTRL_GRP_TTC3_2_WAV,
707 PINCTRL_GRP_TTC3_3_WAV,
708 PINCTRL_GRP_TTC3_4_WAV,
709 PINCTRL_GRP_TTC3_5_WAV,
710 PINCTRL_GRP_TTC3_6_WAV,
711 PINCTRL_GRP_TTC3_7_WAV,
712 PINCTRL_GRP_TTC3_8_WAV,
713 END_OF_GROUPS,
714 }),
715 },
716 [PINCTRL_FUNC_UART0] = {
717 .name = "uart0",
718 .regval = 0xc0,
719 .groups = &((uint16_t []) {
720 PINCTRL_GRP_UART0_0,
721 PINCTRL_GRP_UART0_1,
722 PINCTRL_GRP_UART0_2,
723 PINCTRL_GRP_UART0_3,
724 PINCTRL_GRP_UART0_4,
725 PINCTRL_GRP_UART0_5,
726 PINCTRL_GRP_UART0_6,
727 PINCTRL_GRP_UART0_7,
728 PINCTRL_GRP_UART0_8,
729 PINCTRL_GRP_UART0_9,
730 PINCTRL_GRP_UART0_10,
731 PINCTRL_GRP_UART0_11,
732 PINCTRL_GRP_UART0_12,
733 PINCTRL_GRP_UART0_13,
734 PINCTRL_GRP_UART0_14,
735 PINCTRL_GRP_UART0_15,
736 PINCTRL_GRP_UART0_16,
737 PINCTRL_GRP_UART0_17,
738 PINCTRL_GRP_UART0_18,
739 END_OF_GROUPS,
740 }),
741 },
742 [PINCTRL_FUNC_UART1] = {
743 .name = "uart1",
744 .regval = 0xc0,
745 .groups = &((uint16_t []) {
746 PINCTRL_GRP_UART1_0,
747 PINCTRL_GRP_UART1_1,
748 PINCTRL_GRP_UART1_2,
749 PINCTRL_GRP_UART1_3,
750 PINCTRL_GRP_UART1_4,
751 PINCTRL_GRP_UART1_5,
752 PINCTRL_GRP_UART1_6,
753 PINCTRL_GRP_UART1_7,
754 PINCTRL_GRP_UART1_8,
755 PINCTRL_GRP_UART1_9,
756 PINCTRL_GRP_UART1_10,
757 PINCTRL_GRP_UART1_11,
758 PINCTRL_GRP_UART1_12,
759 PINCTRL_GRP_UART1_13,
760 PINCTRL_GRP_UART1_14,
761 PINCTRL_GRP_UART1_15,
762 PINCTRL_GRP_UART1_16,
763 PINCTRL_GRP_UART1_17,
764 PINCTRL_GRP_UART1_18,
765 END_OF_GROUPS,
766 }),
767 },
768 [PINCTRL_FUNC_USB0] = {
769 .name = "usb0",
770 .regval = 0x04,
771 .groups = &((uint16_t []) {
772 PINCTRL_GRP_USB0_0,
773 END_OF_GROUPS,
774 }),
775 },
776 [PINCTRL_FUNC_USB1] = {
777 .name = "usb1",
778 .regval = 0x04,
779 .groups = &((uint16_t []) {
780 PINCTRL_GRP_USB1_0,
781 END_OF_GROUPS,
782 }),
783 },
784 [PINCTRL_FUNC_SWDT0_CLK] = {
785 .name = "swdt0_clk",
786 .regval = 0x60,
787 .groups = &((uint16_t []) {
788 PINCTRL_GRP_SWDT0_0_CLK,
789 PINCTRL_GRP_SWDT0_1_CLK,
790 PINCTRL_GRP_SWDT0_2_CLK,
791 PINCTRL_GRP_SWDT0_3_CLK,
792 PINCTRL_GRP_SWDT0_4_CLK,
793 PINCTRL_GRP_SWDT0_5_CLK,
794 PINCTRL_GRP_SWDT0_6_CLK,
795 PINCTRL_GRP_SWDT0_7_CLK,
796 PINCTRL_GRP_SWDT0_8_CLK,
797 PINCTRL_GRP_SWDT0_9_CLK,
798 PINCTRL_GRP_SWDT0_10_CLK,
799 PINCTRL_GRP_SWDT0_11_CLK,
800 PINCTRL_GRP_SWDT0_12_CLK,
801 END_OF_GROUPS,
802 }),
803 },
804 [PINCTRL_FUNC_SWDT0_RST] = {
805 .name = "swdt0_rst",
806 .regval = 0x60,
807 .groups = &((uint16_t []) {
808 PINCTRL_GRP_SWDT0_0_RST,
809 PINCTRL_GRP_SWDT0_1_RST,
810 PINCTRL_GRP_SWDT0_2_RST,
811 PINCTRL_GRP_SWDT0_3_RST,
812 PINCTRL_GRP_SWDT0_4_RST,
813 PINCTRL_GRP_SWDT0_5_RST,
814 PINCTRL_GRP_SWDT0_6_RST,
815 PINCTRL_GRP_SWDT0_7_RST,
816 PINCTRL_GRP_SWDT0_8_RST,
817 PINCTRL_GRP_SWDT0_9_RST,
818 PINCTRL_GRP_SWDT0_10_RST,
819 PINCTRL_GRP_SWDT0_11_RST,
820 PINCTRL_GRP_SWDT0_12_RST,
821 END_OF_GROUPS,
822 }),
823 },
824 [PINCTRL_FUNC_SWDT1_CLK] = {
825 .name = "swdt1_clk",
826 .regval = 0x60,
827 .groups = &((uint16_t []) {
828 PINCTRL_GRP_SWDT1_0_CLK,
829 PINCTRL_GRP_SWDT1_1_CLK,
830 PINCTRL_GRP_SWDT1_2_CLK,
831 PINCTRL_GRP_SWDT1_3_CLK,
832 PINCTRL_GRP_SWDT1_4_CLK,
833 PINCTRL_GRP_SWDT1_5_CLK,
834 PINCTRL_GRP_SWDT1_6_CLK,
835 PINCTRL_GRP_SWDT1_7_CLK,
836 PINCTRL_GRP_SWDT1_8_CLK,
837 PINCTRL_GRP_SWDT1_9_CLK,
838 PINCTRL_GRP_SWDT1_10_CLK,
839 PINCTRL_GRP_SWDT1_11_CLK,
840 PINCTRL_GRP_SWDT1_12_CLK,
841 END_OF_GROUPS,
842 }),
843 },
844 [PINCTRL_FUNC_SWDT1_RST] = {
845 .name = "swdt1_rst",
846 .regval = 0x60,
847 .groups = &((uint16_t []) {
848 PINCTRL_GRP_SWDT1_0_RST,
849 PINCTRL_GRP_SWDT1_1_RST,
850 PINCTRL_GRP_SWDT1_2_RST,
851 PINCTRL_GRP_SWDT1_3_RST,
852 PINCTRL_GRP_SWDT1_4_RST,
853 PINCTRL_GRP_SWDT1_5_RST,
854 PINCTRL_GRP_SWDT1_6_RST,
855 PINCTRL_GRP_SWDT1_7_RST,
856 PINCTRL_GRP_SWDT1_8_RST,
857 PINCTRL_GRP_SWDT1_9_RST,
858 PINCTRL_GRP_SWDT1_10_RST,
859 PINCTRL_GRP_SWDT1_11_RST,
860 PINCTRL_GRP_SWDT1_12_RST,
861 END_OF_GROUPS,
862 }),
863 },
864 [PINCTRL_FUNC_PMU0] = {
865 .name = "pmu0",
866 .regval = 0x08,
867 .groups = &((uint16_t []) {
868 PINCTRL_GRP_PMU0_0,
869 PINCTRL_GRP_PMU0_1,
870 PINCTRL_GRP_PMU0_2,
871 PINCTRL_GRP_PMU0_3,
872 PINCTRL_GRP_PMU0_4,
873 PINCTRL_GRP_PMU0_5,
874 PINCTRL_GRP_PMU0_6,
875 PINCTRL_GRP_PMU0_7,
876 PINCTRL_GRP_PMU0_8,
877 PINCTRL_GRP_PMU0_9,
878 PINCTRL_GRP_PMU0_10,
879 PINCTRL_GRP_PMU0_11,
880 END_OF_GROUPS,
881 }),
882 },
883 [PINCTRL_FUNC_PCIE0] = {
884 .name = "pcie0",
885 .regval = 0x04,
886 .groups = &((uint16_t []) {
887 PINCTRL_GRP_PCIE0_0,
888 PINCTRL_GRP_PCIE0_1,
889 PINCTRL_GRP_PCIE0_2,
890 PINCTRL_GRP_PCIE0_3,
891 PINCTRL_GRP_PCIE0_4,
892 PINCTRL_GRP_PCIE0_5,
893 PINCTRL_GRP_PCIE0_6,
894 PINCTRL_GRP_PCIE0_7,
895 END_OF_GROUPS,
896 }),
897 },
898 [PINCTRL_FUNC_CSU0] = {
899 .name = "csu0",
900 .regval = 0x18,
901 .groups = &((uint16_t []) {
902 PINCTRL_GRP_CSU0_0,
903 PINCTRL_GRP_CSU0_1,
904 PINCTRL_GRP_CSU0_2,
905 PINCTRL_GRP_CSU0_3,
906 PINCTRL_GRP_CSU0_4,
907 PINCTRL_GRP_CSU0_5,
908 PINCTRL_GRP_CSU0_6,
909 PINCTRL_GRP_CSU0_7,
910 PINCTRL_GRP_CSU0_8,
911 PINCTRL_GRP_CSU0_9,
912 PINCTRL_GRP_CSU0_10,
913 PINCTRL_GRP_CSU0_11,
914 END_OF_GROUPS,
915 }),
916 },
917 [PINCTRL_FUNC_DPAUX0] = {
918 .name = "dpaux0",
919 .regval = 0x18,
920 .groups = &((uint16_t []) {
921 PINCTRL_GRP_DPAUX0_0,
922 PINCTRL_GRP_DPAUX0_1,
923 PINCTRL_GRP_DPAUX0_2,
924 PINCTRL_GRP_DPAUX0_3,
925 END_OF_GROUPS,
926 }),
927 },
928 [PINCTRL_FUNC_PJTAG0] = {
929 .name = "pjtag0",
930 .regval = 0x60,
931 .groups = &((uint16_t []) {
932 PINCTRL_GRP_PJTAG0_0,
933 PINCTRL_GRP_PJTAG0_1,
934 PINCTRL_GRP_PJTAG0_2,
935 PINCTRL_GRP_PJTAG0_3,
936 PINCTRL_GRP_PJTAG0_4,
937 PINCTRL_GRP_PJTAG0_5,
938 END_OF_GROUPS,
939 }),
940 },
941 [PINCTRL_FUNC_TRACE0] = {
942 .name = "trace0",
943 .regval = 0xe0,
944 .groups = &((uint16_t []) {
945 PINCTRL_GRP_TRACE0_0,
946 PINCTRL_GRP_TRACE0_1,
947 PINCTRL_GRP_TRACE0_2,
948 END_OF_GROUPS,
949 }),
950 },
951 [PINCTRL_FUNC_TRACE0_CLK] = {
952 .name = "trace0_clk",
953 .regval = 0xe0,
954 .groups = &((uint16_t []) {
955 PINCTRL_GRP_TRACE0_0_CLK,
956 PINCTRL_GRP_TRACE0_1_CLK,
957 PINCTRL_GRP_TRACE0_2_CLK,
958 END_OF_GROUPS,
959 }),
960 },
961 [PINCTRL_FUNC_TESTSCAN0] = {
962 .name = "testscan0",
963 .regval = 0x10,
964 .groups = &((uint16_t []) {
965 PINCTRL_GRP_TESTSCAN0_0,
966 END_OF_GROUPS,
967 }),
968 },
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]969};
970
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]971static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = {
972 [PINCTRL_PIN_0] = {
973 .groups = {
974 PINCTRL_GRP_QSPI0_0,
975 PINCTRL_GRP_RESERVED,
976 PINCTRL_GRP_RESERVED,
977 PINCTRL_GRP_TESTSCAN0_0,
978 PINCTRL_GRP_RESERVED,
979 PINCTRL_GRP_GPIO0_0,
980 PINCTRL_GRP_CAN1_0,
981 PINCTRL_GRP_I2C1_0,
982 PINCTRL_GRP_PJTAG0_0,
983 PINCTRL_GRP_SPI0_0,
984 PINCTRL_GRP_TTC3_0_CLK,
985 PINCTRL_GRP_UART1_0,
986 PINCTRL_GRP_TRACE0_0_CLK,
987 },
988 },
989 [PINCTRL_PIN_1] = {
990 .groups = {
991 PINCTRL_GRP_QSPI0_0,
992 PINCTRL_GRP_RESERVED,
993 PINCTRL_GRP_RESERVED,
994 PINCTRL_GRP_TESTSCAN0_0,
995 PINCTRL_GRP_RESERVED,
996 PINCTRL_GRP_GPIO0_1,
997 PINCTRL_GRP_CAN1_0,
998 PINCTRL_GRP_I2C1_0,
999 PINCTRL_GRP_PJTAG0_0,
1000 PINCTRL_GRP_SPI0_0_SS2,
1001 PINCTRL_GRP_TTC3_0_WAV,
1002 PINCTRL_GRP_UART1_0,
1003 PINCTRL_GRP_TRACE0_0_CLK,
1004 },
1005 },
1006 [PINCTRL_PIN_2] = {
1007 .groups = {
1008 PINCTRL_GRP_QSPI0_0,
1009 PINCTRL_GRP_RESERVED,
1010 PINCTRL_GRP_RESERVED,
1011 PINCTRL_GRP_TESTSCAN0_0,
1012 PINCTRL_GRP_RESERVED,
1013 PINCTRL_GRP_GPIO0_2,
1014 PINCTRL_GRP_CAN0_0,
1015 PINCTRL_GRP_I2C0_0,
1016 PINCTRL_GRP_PJTAG0_0,
1017 PINCTRL_GRP_SPI0_0_SS1,
1018 PINCTRL_GRP_TTC2_0_CLK,
1019 PINCTRL_GRP_UART0_0,
1020 PINCTRL_GRP_TRACE0_0,
1021 },
1022 },
1023 [PINCTRL_PIN_3] = {
1024 .groups = {
1025 PINCTRL_GRP_QSPI0_0,
1026 PINCTRL_GRP_RESERVED,
1027 PINCTRL_GRP_RESERVED,
1028 PINCTRL_GRP_TESTSCAN0_0,
1029 PINCTRL_GRP_RESERVED,
1030 PINCTRL_GRP_GPIO0_3,
1031 PINCTRL_GRP_CAN0_0,
1032 PINCTRL_GRP_I2C0_0,
1033 PINCTRL_GRP_PJTAG0_0,
1034 PINCTRL_GRP_SPI0_0_SS0,
1035 PINCTRL_GRP_TTC2_0_WAV,
1036 PINCTRL_GRP_UART0_0,
1037 PINCTRL_GRP_TRACE0_0,
1038 },
1039 },
1040 [PINCTRL_PIN_4] = {
1041 .groups = {
1042 PINCTRL_GRP_QSPI0_0,
1043 PINCTRL_GRP_RESERVED,
1044 PINCTRL_GRP_RESERVED,
1045 PINCTRL_GRP_TESTSCAN0_0,
1046 PINCTRL_GRP_RESERVED,
1047 PINCTRL_GRP_GPIO0_4,
1048 PINCTRL_GRP_CAN1_1,
1049 PINCTRL_GRP_I2C1_1,
1050 PINCTRL_GRP_SWDT1_0_CLK,
1051 PINCTRL_GRP_SPI0_0,
1052 PINCTRL_GRP_TTC1_0_CLK,
1053 PINCTRL_GRP_UART1_1,
1054 PINCTRL_GRP_TRACE0_0,
1055 },
1056 },
1057 [PINCTRL_PIN_5] = {
1058 .groups = {
1059 PINCTRL_GRP_QSPI_SS,
1060 PINCTRL_GRP_RESERVED,
1061 PINCTRL_GRP_RESERVED,
1062 PINCTRL_GRP_TESTSCAN0_0,
1063 PINCTRL_GRP_RESERVED,
1064 PINCTRL_GRP_GPIO0_5,
1065 PINCTRL_GRP_CAN1_1,
1066 PINCTRL_GRP_I2C1_1,
1067 PINCTRL_GRP_SWDT1_0_RST,
1068 PINCTRL_GRP_SPI0_0,
1069 PINCTRL_GRP_TTC1_0_WAV,
1070 PINCTRL_GRP_UART1_1,
1071 PINCTRL_GRP_TRACE0_0,
1072 },
1073 },
1074 [PINCTRL_PIN_6] = {
1075 .groups = {
1076 PINCTRL_GRP_QSPI_FBCLK,
1077 PINCTRL_GRP_RESERVED,
1078 PINCTRL_GRP_RESERVED,
1079 PINCTRL_GRP_TESTSCAN0_0,
1080 PINCTRL_GRP_RESERVED,
1081 PINCTRL_GRP_GPIO0_6,
1082 PINCTRL_GRP_CAN0_1,
1083 PINCTRL_GRP_I2C0_1,
1084 PINCTRL_GRP_SWDT0_0_CLK,
1085 PINCTRL_GRP_SPI1_0,
1086 PINCTRL_GRP_TTC0_0_CLK,
1087 PINCTRL_GRP_UART0_1,
1088 PINCTRL_GRP_TRACE0_0,
1089 },
1090 },
1091 [PINCTRL_PIN_7] = {
1092 .groups = {
1093 PINCTRL_GRP_QSPI_SS,
1094 PINCTRL_GRP_RESERVED,
1095 PINCTRL_GRP_RESERVED,
1096 PINCTRL_GRP_TESTSCAN0_0,
1097 PINCTRL_GRP_RESERVED,
1098 PINCTRL_GRP_GPIO0_7,
1099 PINCTRL_GRP_CAN0_1,
1100 PINCTRL_GRP_I2C0_1,
1101 PINCTRL_GRP_SWDT0_0_RST,
1102 PINCTRL_GRP_SPI1_0_SS2,
1103 PINCTRL_GRP_TTC0_0_WAV,
1104 PINCTRL_GRP_UART0_1,
1105 PINCTRL_GRP_TRACE0_0,
1106 },
1107 },
1108 [PINCTRL_PIN_8] = {
1109 .groups = {
1110 PINCTRL_GRP_QSPI0_0,
1111 PINCTRL_GRP_RESERVED,
1112 PINCTRL_GRP_RESERVED,
1113 PINCTRL_GRP_TESTSCAN0_0,
1114 PINCTRL_GRP_RESERVED,
1115 PINCTRL_GRP_GPIO0_8,
1116 PINCTRL_GRP_CAN1_2,
1117 PINCTRL_GRP_I2C1_2,
1118 PINCTRL_GRP_SWDT1_1_CLK,
1119 PINCTRL_GRP_SPI1_0_SS1,
1120 PINCTRL_GRP_TTC3_1_CLK,
1121 PINCTRL_GRP_UART1_2,
1122 PINCTRL_GRP_TRACE0_0,
1123 },
1124 },
1125 [PINCTRL_PIN_9] = {
1126 .groups = {
1127 PINCTRL_GRP_QSPI0_0,
1128 PINCTRL_GRP_NAND0_0_CE,
1129 PINCTRL_GRP_RESERVED,
1130 PINCTRL_GRP_TESTSCAN0_0,
1131 PINCTRL_GRP_RESERVED,
1132 PINCTRL_GRP_GPIO0_9,
1133 PINCTRL_GRP_CAN1_2,
1134 PINCTRL_GRP_I2C1_2,
1135 PINCTRL_GRP_SWDT1_1_RST,
1136 PINCTRL_GRP_SPI1_0_SS0,
1137 PINCTRL_GRP_TTC3_1_WAV,
1138 PINCTRL_GRP_UART1_2,
1139 PINCTRL_GRP_TRACE0_0,
1140 },
1141 },
1142 [PINCTRL_PIN_10] = {
1143 .groups = {
1144 PINCTRL_GRP_QSPI0_0,
1145 PINCTRL_GRP_NAND0_0_RB,
1146 PINCTRL_GRP_RESERVED,
1147 PINCTRL_GRP_TESTSCAN0_0,
1148 PINCTRL_GRP_RESERVED,
1149 PINCTRL_GRP_GPIO0_10,
1150 PINCTRL_GRP_CAN0_2,
1151 PINCTRL_GRP_I2C0_2,
1152 PINCTRL_GRP_SWDT0_1_CLK,
1153 PINCTRL_GRP_SPI1_0,
1154 PINCTRL_GRP_TTC2_1_CLK,
1155 PINCTRL_GRP_UART0_2,
1156 PINCTRL_GRP_TRACE0_0,
1157 },
1158 },
1159 [PINCTRL_PIN_11] = {
1160 .groups = {
1161 PINCTRL_GRP_QSPI0_0,
1162 PINCTRL_GRP_NAND0_0_RB,
1163 PINCTRL_GRP_RESERVED,
1164 PINCTRL_GRP_TESTSCAN0_0,
1165 PINCTRL_GRP_RESERVED,
1166 PINCTRL_GRP_GPIO0_11,
1167 PINCTRL_GRP_CAN0_2,
1168 PINCTRL_GRP_I2C0_2,
1169 PINCTRL_GRP_SWDT0_1_RST,
1170 PINCTRL_GRP_SPI1_0,
1171 PINCTRL_GRP_TTC2_1_WAV,
1172 PINCTRL_GRP_UART0_2,
1173 PINCTRL_GRP_TRACE0_0,
1174 },
1175 },
1176 [PINCTRL_PIN_12] = {
1177 .groups = {
1178 PINCTRL_GRP_QSPI0_0,
1179 PINCTRL_GRP_NAND0_0_DQS,
1180 PINCTRL_GRP_RESERVED,
1181 PINCTRL_GRP_TESTSCAN0_0,
1182 PINCTRL_GRP_RESERVED,
1183 PINCTRL_GRP_GPIO0_12,
1184 PINCTRL_GRP_CAN1_3,
1185 PINCTRL_GRP_I2C1_3,
1186 PINCTRL_GRP_PJTAG0_1,
1187 PINCTRL_GRP_SPI0_1,
1188 PINCTRL_GRP_TTC1_1_CLK,
1189 PINCTRL_GRP_UART1_3,
1190 PINCTRL_GRP_TRACE0_0,
1191 },
1192 },
1193 [PINCTRL_PIN_13] = {
1194 .groups = {
1195 PINCTRL_GRP_RESERVED,
1196 PINCTRL_GRP_NAND0_0,
1197 PINCTRL_GRP_SDIO0_1BIT_0_0,
1198 PINCTRL_GRP_TESTSCAN0_0,
1199 PINCTRL_GRP_RESERVED,
1200 PINCTRL_GRP_GPIO0_13,
1201 PINCTRL_GRP_CAN1_3,
1202 PINCTRL_GRP_I2C1_3,
1203 PINCTRL_GRP_PJTAG0_1,
1204 PINCTRL_GRP_SPI0_1_SS2,
1205 PINCTRL_GRP_TTC1_1_WAV,
1206 PINCTRL_GRP_UART1_3,
1207 PINCTRL_GRP_TRACE0_0,
1208 },
1209 },
1210 [PINCTRL_PIN_14] = {
1211 .groups = {
1212 PINCTRL_GRP_RESERVED,
1213 PINCTRL_GRP_NAND0_0,
1214 PINCTRL_GRP_SDIO0_1BIT_0_1,
1215 PINCTRL_GRP_TESTSCAN0_0,
1216 PINCTRL_GRP_RESERVED,
1217 PINCTRL_GRP_GPIO0_14,
1218 PINCTRL_GRP_CAN0_3,
1219 PINCTRL_GRP_I2C0_3,
1220 PINCTRL_GRP_PJTAG0_1,
1221 PINCTRL_GRP_SPI0_1_SS1,
1222 PINCTRL_GRP_TTC0_1_CLK,
1223 PINCTRL_GRP_UART0_3,
1224 PINCTRL_GRP_TRACE0_0,
1225 },
1226 },
1227 [PINCTRL_PIN_15] = {
1228 .groups = {
1229 PINCTRL_GRP_RESERVED,
1230 PINCTRL_GRP_NAND0_0,
1231 PINCTRL_GRP_SDIO0_1BIT_0_2,
1232 PINCTRL_GRP_TESTSCAN0_0,
1233 PINCTRL_GRP_RESERVED,
1234 PINCTRL_GRP_GPIO0_15,
1235 PINCTRL_GRP_CAN0_3,
1236 PINCTRL_GRP_I2C0_3,
1237 PINCTRL_GRP_PJTAG0_1,
1238 PINCTRL_GRP_SPI0_1_SS0,
1239 PINCTRL_GRP_TTC0_1_WAV,
1240 PINCTRL_GRP_UART0_3,
1241 PINCTRL_GRP_TRACE0_0,
1242 },
1243 },
1244 [PINCTRL_PIN_16] = {
1245 .groups = {
1246 PINCTRL_GRP_RESERVED,
1247 PINCTRL_GRP_NAND0_0,
1248 PINCTRL_GRP_SDIO0_1BIT_0_3,
1249 PINCTRL_GRP_TESTSCAN0_0,
1250 PINCTRL_GRP_RESERVED,
1251 PINCTRL_GRP_GPIO0_16,
1252 PINCTRL_GRP_CAN1_4,
1253 PINCTRL_GRP_I2C1_4,
1254 PINCTRL_GRP_SWDT1_2_CLK,
1255 PINCTRL_GRP_SPI0_1,
1256 PINCTRL_GRP_TTC3_2_CLK,
1257 PINCTRL_GRP_UART1_4,
1258 PINCTRL_GRP_TRACE0_0,
1259 },
1260 },
1261 [PINCTRL_PIN_17] = {
1262 .groups = {
1263 PINCTRL_GRP_RESERVED,
1264 PINCTRL_GRP_NAND0_0,
1265 PINCTRL_GRP_SDIO0_1BIT_0_4,
1266 PINCTRL_GRP_TESTSCAN0_0,
1267 PINCTRL_GRP_RESERVED,
1268 PINCTRL_GRP_GPIO0_17,
1269 PINCTRL_GRP_CAN1_4,
1270 PINCTRL_GRP_I2C1_4,
1271 PINCTRL_GRP_SWDT1_2_RST,
1272 PINCTRL_GRP_SPI0_1,
1273 PINCTRL_GRP_TTC3_2_WAV,
1274 PINCTRL_GRP_UART1_4,
1275 PINCTRL_GRP_TRACE0_0,
1276 },
1277 },
1278 [PINCTRL_PIN_18] = {
1279 .groups = {
1280 PINCTRL_GRP_RESERVED,
1281 PINCTRL_GRP_NAND0_0,
1282 PINCTRL_GRP_SDIO0_1BIT_0_5,
1283 PINCTRL_GRP_TESTSCAN0_0,
1284 PINCTRL_GRP_CSU0_0,
1285 PINCTRL_GRP_GPIO0_18,
1286 PINCTRL_GRP_CAN0_4,
1287 PINCTRL_GRP_I2C0_4,
1288 PINCTRL_GRP_SWDT0_2_CLK,
1289 PINCTRL_GRP_SPI1_1,
1290 PINCTRL_GRP_TTC2_2_CLK,
1291 PINCTRL_GRP_UART0_4,
1292 PINCTRL_GRP_RESERVED,
1293 },
1294 },
1295 [PINCTRL_PIN_19] = {
1296 .groups = {
1297 PINCTRL_GRP_RESERVED,
1298 PINCTRL_GRP_NAND0_0,
1299 PINCTRL_GRP_SDIO0_1BIT_0_6,
1300 PINCTRL_GRP_TESTSCAN0_0,
1301 PINCTRL_GRP_CSU0_1,
1302 PINCTRL_GRP_GPIO0_19,
1303 PINCTRL_GRP_CAN0_4,
1304 PINCTRL_GRP_I2C0_4,
1305 PINCTRL_GRP_SWDT0_2_RST,
1306 PINCTRL_GRP_SPI1_1_SS2,
1307 PINCTRL_GRP_TTC2_2_WAV,
1308 PINCTRL_GRP_UART0_4,
1309 PINCTRL_GRP_RESERVED,
1310 },
1311 },
1312 [PINCTRL_PIN_20] = {
1313 .groups = {
1314 PINCTRL_GRP_RESERVED,
1315 PINCTRL_GRP_NAND0_0,
1316 PINCTRL_GRP_SDIO0_1BIT_0_7,
1317 PINCTRL_GRP_TESTSCAN0_0,
1318 PINCTRL_GRP_CSU0_2,
1319 PINCTRL_GRP_GPIO0_20,
1320 PINCTRL_GRP_CAN1_5,
1321 PINCTRL_GRP_I2C1_5,
1322 PINCTRL_GRP_SWDT1_3_CLK,
1323 PINCTRL_GRP_SPI1_1_SS1,
1324 PINCTRL_GRP_TTC1_2_CLK,
1325 PINCTRL_GRP_UART1_5,
1326 PINCTRL_GRP_RESERVED,
1327 },
1328 },
1329 [PINCTRL_PIN_21] = {
1330 .groups = {
1331 PINCTRL_GRP_RESERVED,
1332 PINCTRL_GRP_NAND0_0,
1333 PINCTRL_GRP_SDIO0_1BIT_0_7,
1334 PINCTRL_GRP_TESTSCAN0_0,
1335 PINCTRL_GRP_CSU0_3,
1336 PINCTRL_GRP_GPIO0_21,
1337 PINCTRL_GRP_CAN1_5,
1338 PINCTRL_GRP_I2C1_5,
1339 PINCTRL_GRP_SWDT1_3_RST,
1340 PINCTRL_GRP_SPI1_1_SS0,
1341 PINCTRL_GRP_TTC1_2_WAV,
1342 PINCTRL_GRP_UART1_5,
1343 PINCTRL_GRP_RESERVED,
1344 },
1345 },
1346 [PINCTRL_PIN_22] = {
1347 .groups = {
1348 PINCTRL_GRP_RESERVED,
1349 PINCTRL_GRP_NAND0_0,
1350 PINCTRL_GRP_SDIO0_1BIT_0_7,
1351 PINCTRL_GRP_TESTSCAN0_0,
1352 PINCTRL_GRP_CSU0_4,
1353 PINCTRL_GRP_GPIO0_22,
1354 PINCTRL_GRP_CAN0_5,
1355 PINCTRL_GRP_I2C0_5,
1356 PINCTRL_GRP_SWDT0_3_CLK,
1357 PINCTRL_GRP_SPI1_1,
1358 PINCTRL_GRP_TTC0_2_CLK,
1359 PINCTRL_GRP_UART0_5,
1360 PINCTRL_GRP_RESERVED,
1361 },
1362 },
1363 [PINCTRL_PIN_23] = {
1364 .groups = {
1365 PINCTRL_GRP_RESERVED,
1366 PINCTRL_GRP_NAND0_0,
1367 PINCTRL_GRP_SDIO0_0_PC,
1368 PINCTRL_GRP_TESTSCAN0_0,
1369 PINCTRL_GRP_CSU0_5,
1370 PINCTRL_GRP_GPIO0_23,
1371 PINCTRL_GRP_CAN0_5,
1372 PINCTRL_GRP_I2C0_5,
1373 PINCTRL_GRP_SWDT0_3_RST,
1374 PINCTRL_GRP_SPI1_1,
1375 PINCTRL_GRP_TTC0_2_WAV,
1376 PINCTRL_GRP_UART0_5,
1377 PINCTRL_GRP_RESERVED,
1378 },
1379 },
1380 [PINCTRL_PIN_24] = {
1381 .groups = {
1382 PINCTRL_GRP_RESERVED,
1383 PINCTRL_GRP_NAND0_0,
1384 PINCTRL_GRP_SDIO0_0_CD,
1385 PINCTRL_GRP_TESTSCAN0_0,
1386 PINCTRL_GRP_CSU0_6,
1387 PINCTRL_GRP_GPIO0_24,
1388 PINCTRL_GRP_CAN1_6,
1389 PINCTRL_GRP_I2C1_6,
1390 PINCTRL_GRP_SWDT1_4_CLK,
1391 PINCTRL_GRP_RESERVED,
1392 PINCTRL_GRP_TTC3_3_CLK,
1393 PINCTRL_GRP_UART1_6,
1394 PINCTRL_GRP_RESERVED,
1395 },
1396 },
1397 [PINCTRL_PIN_25] = {
1398 .groups = {
1399 PINCTRL_GRP_RESERVED,
1400 PINCTRL_GRP_NAND0_0,
1401 PINCTRL_GRP_SDIO0_0_WP,
1402 PINCTRL_GRP_TESTSCAN0_0,
1403 PINCTRL_GRP_CSU0_7,
1404 PINCTRL_GRP_GPIO0_25,
1405 PINCTRL_GRP_CAN1_6,
1406 PINCTRL_GRP_I2C1_6,
1407 PINCTRL_GRP_SWDT1_4_RST,
1408 PINCTRL_GRP_RESERVED,
1409 PINCTRL_GRP_TTC3_3_WAV,
1410 PINCTRL_GRP_UART1_6,
1411 PINCTRL_GRP_RESERVED,
1412 },
1413 },
1414 [PINCTRL_PIN_26] = {
1415 .groups = {
1416 PINCTRL_GRP_GEMTSU0_0,
1417 PINCTRL_GRP_NAND0_1_CE,
1418 PINCTRL_GRP_PMU0_0,
1419 PINCTRL_GRP_TESTSCAN0_0,
1420 PINCTRL_GRP_CSU0_8,
1421 PINCTRL_GRP_GPIO0_26,
1422 PINCTRL_GRP_CAN0_6,
1423 PINCTRL_GRP_I2C0_6,
1424 PINCTRL_GRP_PJTAG0_2,
1425 PINCTRL_GRP_SPI0_2,
1426 PINCTRL_GRP_TTC2_3_CLK,
1427 PINCTRL_GRP_UART0_6,
1428 PINCTRL_GRP_TRACE0_1,
1429 },
1430 },
1431 [PINCTRL_PIN_27] = {
1432 .groups = {
1433 PINCTRL_GRP_ETHERNET0_0,
1434 PINCTRL_GRP_NAND0_1_RB,
1435 PINCTRL_GRP_PMU0_1,
1436 PINCTRL_GRP_TESTSCAN0_0,
1437 PINCTRL_GRP_DPAUX0_0,
1438 PINCTRL_GRP_GPIO0_27,
1439 PINCTRL_GRP_CAN0_6,
1440 PINCTRL_GRP_I2C0_6,
1441 PINCTRL_GRP_PJTAG0_2,
1442 PINCTRL_GRP_SPI0_2_SS2,
1443 PINCTRL_GRP_TTC2_3_WAV,
1444 PINCTRL_GRP_UART0_6,
1445 PINCTRL_GRP_TRACE0_1,
1446 },
1447 },
1448 [PINCTRL_PIN_28] = {
1449 .groups = {
1450 PINCTRL_GRP_ETHERNET0_0,
1451 PINCTRL_GRP_NAND0_1_RB,
1452 PINCTRL_GRP_PMU0_2,
1453 PINCTRL_GRP_TESTSCAN0_0,
1454 PINCTRL_GRP_DPAUX0_0,
1455 PINCTRL_GRP_GPIO0_28,
1456 PINCTRL_GRP_CAN1_7,
1457 PINCTRL_GRP_I2C1_7,
1458 PINCTRL_GRP_PJTAG0_2,
1459 PINCTRL_GRP_SPI0_2_SS1,
1460 PINCTRL_GRP_TTC1_3_CLK,
1461 PINCTRL_GRP_UART1_7,
1462 PINCTRL_GRP_TRACE0_1,
1463 },
1464 },
1465 [PINCTRL_PIN_29] = {
1466 .groups = {
1467 PINCTRL_GRP_ETHERNET0_0,
1468 PINCTRL_GRP_PCIE0_0,
1469 PINCTRL_GRP_PMU0_3,
1470 PINCTRL_GRP_TESTSCAN0_0,
1471 PINCTRL_GRP_DPAUX0_1,
1472 PINCTRL_GRP_GPIO0_29,
1473 PINCTRL_GRP_CAN1_7,
1474 PINCTRL_GRP_I2C1_7,
1475 PINCTRL_GRP_PJTAG0_2,
1476 PINCTRL_GRP_SPI0_2_SS0,
1477 PINCTRL_GRP_TTC1_3_WAV,
1478 PINCTRL_GRP_UART1_7,
1479 PINCTRL_GRP_TRACE0_1,
1480 },
1481 },
1482 [PINCTRL_PIN_30] = {
1483 .groups = {
1484 PINCTRL_GRP_ETHERNET0_0,
1485 PINCTRL_GRP_PCIE0_1,
1486 PINCTRL_GRP_PMU0_4,
1487 PINCTRL_GRP_TESTSCAN0_0,
1488 PINCTRL_GRP_DPAUX0_1,
1489 PINCTRL_GRP_GPIO0_30,
1490 PINCTRL_GRP_CAN0_7,
1491 PINCTRL_GRP_I2C0_7,
1492 PINCTRL_GRP_SWDT0_4_CLK,
1493 PINCTRL_GRP_SPI0_2,
1494 PINCTRL_GRP_TTC0_3_CLK,
1495 PINCTRL_GRP_UART0_7,
1496 PINCTRL_GRP_TRACE0_1,
1497 },
1498 },
1499 [PINCTRL_PIN_31] = {
1500 .groups = {
1501 PINCTRL_GRP_ETHERNET0_0,
1502 PINCTRL_GRP_PCIE0_2,
1503 PINCTRL_GRP_PMU0_5,
1504 PINCTRL_GRP_TESTSCAN0_0,
1505 PINCTRL_GRP_CSU0_9,
1506 PINCTRL_GRP_GPIO0_31,
1507 PINCTRL_GRP_CAN0_7,
1508 PINCTRL_GRP_I2C0_7,
1509 PINCTRL_GRP_SWDT0_4_RST,
1510 PINCTRL_GRP_SPI0_2,
1511 PINCTRL_GRP_TTC0_3_WAV,
1512 PINCTRL_GRP_UART0_7,
1513 PINCTRL_GRP_TRACE0_1,
1514 },
1515 },
1516 [PINCTRL_PIN_32] = {
1517 .groups = {
1518 PINCTRL_GRP_ETHERNET0_0,
1519 PINCTRL_GRP_NAND0_1_DQS,
1520 PINCTRL_GRP_PMU0_6,
1521 PINCTRL_GRP_TESTSCAN0_0,
1522 PINCTRL_GRP_CSU0_10,
1523 PINCTRL_GRP_GPIO0_32,
1524 PINCTRL_GRP_CAN1_8,
1525 PINCTRL_GRP_I2C1_8,
1526 PINCTRL_GRP_SWDT1_5_CLK,
1527 PINCTRL_GRP_SPI1_2,
1528 PINCTRL_GRP_TTC3_4_CLK,
1529 PINCTRL_GRP_UART1_8,
1530 PINCTRL_GRP_TRACE0_1,
1531 },
1532 },
1533 [PINCTRL_PIN_33] = {
1534 .groups = {
1535 PINCTRL_GRP_ETHERNET0_0,
1536 PINCTRL_GRP_PCIE0_3,
1537 PINCTRL_GRP_PMU0_7,
1538 PINCTRL_GRP_TESTSCAN0_0,
1539 PINCTRL_GRP_CSU0_11,
1540 PINCTRL_GRP_GPIO0_33,
1541 PINCTRL_GRP_CAN1_8,
1542 PINCTRL_GRP_I2C1_8,
1543 PINCTRL_GRP_SWDT1_5_RST,
1544 PINCTRL_GRP_SPI1_2_SS2,
1545 PINCTRL_GRP_TTC3_4_WAV,
1546 PINCTRL_GRP_UART1_8,
1547 PINCTRL_GRP_TRACE0_1,
1548 },
1549 },
1550 [PINCTRL_PIN_34] = {
1551 .groups = {
1552 PINCTRL_GRP_ETHERNET0_0,
1553 PINCTRL_GRP_PCIE0_4,
1554 PINCTRL_GRP_PMU0_8,
1555 PINCTRL_GRP_TESTSCAN0_0,
1556 PINCTRL_GRP_DPAUX0_2,
1557 PINCTRL_GRP_GPIO0_34,
1558 PINCTRL_GRP_CAN0_8,
1559 PINCTRL_GRP_I2C0_8,
1560 PINCTRL_GRP_SWDT0_5_CLK,
1561 PINCTRL_GRP_SPI1_2_SS1,
1562 PINCTRL_GRP_TTC2_4_CLK,
1563 PINCTRL_GRP_UART0_8,
1564 PINCTRL_GRP_TRACE0_1,
1565 },
1566 },
1567 [PINCTRL_PIN_35] = {
1568 .groups = {
1569 PINCTRL_GRP_ETHERNET0_0,
1570 PINCTRL_GRP_PCIE0_5,
1571 PINCTRL_GRP_PMU0_9,
1572 PINCTRL_GRP_TESTSCAN0_0,
1573 PINCTRL_GRP_DPAUX0_2,
1574 PINCTRL_GRP_GPIO0_35,
1575 PINCTRL_GRP_CAN0_8,
1576 PINCTRL_GRP_I2C0_8,
1577 PINCTRL_GRP_SWDT0_5_RST,
1578 PINCTRL_GRP_SPI1_2_SS0,
1579 PINCTRL_GRP_TTC2_4_WAV,
1580 PINCTRL_GRP_UART0_8,
1581 PINCTRL_GRP_TRACE0_1,
1582 },
1583 },
1584 [PINCTRL_PIN_36] = {
1585 .groups = {
1586 PINCTRL_GRP_ETHERNET0_0,
1587 PINCTRL_GRP_PCIE0_6,
1588 PINCTRL_GRP_PMU0_10,
1589 PINCTRL_GRP_TESTSCAN0_0,
1590 PINCTRL_GRP_DPAUX0_3,
1591 PINCTRL_GRP_GPIO0_36,
1592 PINCTRL_GRP_CAN1_9,
1593 PINCTRL_GRP_I2C1_9,
1594 PINCTRL_GRP_SWDT1_6_CLK,
1595 PINCTRL_GRP_SPI1_2,
1596 PINCTRL_GRP_TTC1_4_CLK,
1597 PINCTRL_GRP_UART1_9,
1598 PINCTRL_GRP_TRACE0_1,
1599 },
1600 },
1601 [PINCTRL_PIN_37] = {
1602 .groups = {
1603 PINCTRL_GRP_ETHERNET0_0,
1604 PINCTRL_GRP_PCIE0_7,
1605 PINCTRL_GRP_PMU0_11,
1606 PINCTRL_GRP_TESTSCAN0_0,
1607 PINCTRL_GRP_DPAUX0_3,
1608 PINCTRL_GRP_GPIO0_37,
1609 PINCTRL_GRP_CAN1_9,
1610 PINCTRL_GRP_I2C1_9,
1611 PINCTRL_GRP_SWDT1_6_RST,
1612 PINCTRL_GRP_SPI1_2,
1613 PINCTRL_GRP_TTC1_4_WAV,
1614 PINCTRL_GRP_UART1_9,
1615 PINCTRL_GRP_TRACE0_1,
1616 },
1617 },
1618 [PINCTRL_PIN_38] = {
1619 .groups = {
1620 PINCTRL_GRP_ETHERNET1_0,
1621 PINCTRL_GRP_RESERVED,
1622 PINCTRL_GRP_SDIO0_1BIT_1_7,
1623 PINCTRL_GRP_RESERVED,
1624 PINCTRL_GRP_RESERVED,
1625 PINCTRL_GRP_GPIO0_38,
1626 PINCTRL_GRP_CAN0_9,
1627 PINCTRL_GRP_I2C0_9,
1628 PINCTRL_GRP_PJTAG0_3,
1629 PINCTRL_GRP_SPI0_3,
1630 PINCTRL_GRP_TTC0_4_CLK,
1631 PINCTRL_GRP_UART0_9,
1632 PINCTRL_GRP_TRACE0_1_CLK,
1633 },
1634 },
1635 [PINCTRL_PIN_39] = {
1636 .groups = {
1637 PINCTRL_GRP_ETHERNET1_0,
1638 PINCTRL_GRP_RESERVED,
1639 PINCTRL_GRP_SDIO0_1_CD,
1640 PINCTRL_GRP_SDIO1_1BIT_0_0,
1641 PINCTRL_GRP_RESERVED,
1642 PINCTRL_GRP_GPIO0_39,
1643 PINCTRL_GRP_CAN0_9,
1644 PINCTRL_GRP_I2C0_9,
1645 PINCTRL_GRP_PJTAG0_3,
1646 PINCTRL_GRP_SPI0_3_SS2,
1647 PINCTRL_GRP_TTC0_4_WAV,
1648 PINCTRL_GRP_UART0_9,
1649 PINCTRL_GRP_TRACE0_1_CLK,
1650 },
1651 },
1652 [PINCTRL_PIN_40] = {
1653 .groups = {
1654 PINCTRL_GRP_ETHERNET1_0,
1655 PINCTRL_GRP_RESERVED,
1656 PINCTRL_GRP_SDIO0_1BIT_1_7,
1657 PINCTRL_GRP_SDIO1_1BIT_0_1,
1658 PINCTRL_GRP_RESERVED,
1659 PINCTRL_GRP_GPIO0_40,
1660 PINCTRL_GRP_CAN1_10,
1661 PINCTRL_GRP_I2C1_10,
1662 PINCTRL_GRP_PJTAG0_3,
1663 PINCTRL_GRP_SPI0_3_SS1,
1664 PINCTRL_GRP_TTC3_5_CLK,
1665 PINCTRL_GRP_UART1_10,
1666 PINCTRL_GRP_TRACE0_1,
1667 },
1668 },
1669 [PINCTRL_PIN_41] = {
1670 .groups = {
1671 PINCTRL_GRP_ETHERNET1_0,
1672 PINCTRL_GRP_RESERVED,
1673 PINCTRL_GRP_SDIO0_1BIT_1_0,
1674 PINCTRL_GRP_SDIO1_1BIT_0_2,
1675 PINCTRL_GRP_RESERVED,
1676 PINCTRL_GRP_GPIO0_41,
1677 PINCTRL_GRP_CAN1_10,
1678 PINCTRL_GRP_I2C1_10,
1679 PINCTRL_GRP_PJTAG0_3,
1680 PINCTRL_GRP_SPI0_3_SS0,
1681 PINCTRL_GRP_TTC3_5_WAV,
1682 PINCTRL_GRP_UART1_10,
1683 PINCTRL_GRP_TRACE0_1,
1684 },
1685 },
1686 [PINCTRL_PIN_42] = {
1687 .groups = {
1688 PINCTRL_GRP_ETHERNET1_0,
1689 PINCTRL_GRP_RESERVED,
1690 PINCTRL_GRP_SDIO0_1BIT_1_1,
1691 PINCTRL_GRP_SDIO1_1BIT_0_3,
1692 PINCTRL_GRP_RESERVED,
1693 PINCTRL_GRP_GPIO0_42,
1694 PINCTRL_GRP_CAN0_10,
1695 PINCTRL_GRP_I2C0_10,
1696 PINCTRL_GRP_SWDT0_6_CLK,
1697 PINCTRL_GRP_SPI0_3,
1698 PINCTRL_GRP_TTC2_5_CLK,
1699 PINCTRL_GRP_UART0_10,
1700 PINCTRL_GRP_TRACE0_1,
1701 },
1702 },
1703 [PINCTRL_PIN_43] = {
1704 .groups = {
1705 PINCTRL_GRP_ETHERNET1_0,
1706 PINCTRL_GRP_RESERVED,
1707 PINCTRL_GRP_SDIO0_1BIT_1_2,
1708 PINCTRL_GRP_SDIO1_0_PC,
1709 PINCTRL_GRP_RESERVED,
1710 PINCTRL_GRP_GPIO0_43,
1711 PINCTRL_GRP_CAN0_10,
1712 PINCTRL_GRP_I2C0_10,
1713 PINCTRL_GRP_SWDT0_6_RST,
1714 PINCTRL_GRP_SPI0_3,
1715 PINCTRL_GRP_TTC2_5_WAV,
1716 PINCTRL_GRP_UART0_10,
1717 PINCTRL_GRP_TRACE0_1,
1718 },
1719 },
1720 [PINCTRL_PIN_44] = {
1721 .groups = {
1722 PINCTRL_GRP_ETHERNET1_0,
1723 PINCTRL_GRP_RESERVED,
1724 PINCTRL_GRP_SDIO0_1BIT_1_3,
1725 PINCTRL_GRP_SDIO1_0_WP,
1726 PINCTRL_GRP_RESERVED,
1727 PINCTRL_GRP_GPIO0_44,
1728 PINCTRL_GRP_CAN1_11,
1729 PINCTRL_GRP_I2C1_11,
1730 PINCTRL_GRP_SWDT1_7_CLK,
1731 PINCTRL_GRP_SPI1_3,
1732 PINCTRL_GRP_TTC1_5_CLK,
1733 PINCTRL_GRP_UART1_11,
1734 PINCTRL_GRP_RESERVED,
1735 },
1736 },
1737 [PINCTRL_PIN_45] = {
1738 .groups = {
1739 PINCTRL_GRP_ETHERNET1_0,
1740 PINCTRL_GRP_RESERVED,
1741 PINCTRL_GRP_SDIO0_1BIT_1_4,
1742 PINCTRL_GRP_SDIO1_0_CD,
1743 PINCTRL_GRP_RESERVED,
1744 PINCTRL_GRP_GPIO0_45,
1745 PINCTRL_GRP_CAN1_11,
1746 PINCTRL_GRP_I2C1_11,
1747 PINCTRL_GRP_SWDT1_7_RST,
1748 PINCTRL_GRP_SPI1_3_SS2,
1749 PINCTRL_GRP_TTC1_5_WAV,
1750 PINCTRL_GRP_UART1_11,
1751 PINCTRL_GRP_RESERVED,
1752 },
1753 },
1754 [PINCTRL_PIN_46] = {
1755 .groups = {
1756 PINCTRL_GRP_ETHERNET1_0,
1757 PINCTRL_GRP_RESERVED,
1758 PINCTRL_GRP_SDIO0_1BIT_1_5,
1759 PINCTRL_GRP_SDIO1_1BIT_0_4,
1760 PINCTRL_GRP_RESERVED,
1761 PINCTRL_GRP_GPIO0_46,
1762 PINCTRL_GRP_CAN0_11,
1763 PINCTRL_GRP_I2C0_11,
1764 PINCTRL_GRP_SWDT0_7_CLK,
1765 PINCTRL_GRP_SPI1_3_SS1,
1766 PINCTRL_GRP_TTC0_5_CLK,
1767 PINCTRL_GRP_UART0_11,
1768 PINCTRL_GRP_RESERVED,
1769 },
1770 },
1771 [PINCTRL_PIN_47] = {
1772 .groups = {
1773 PINCTRL_GRP_ETHERNET1_0,
1774 PINCTRL_GRP_RESERVED,
1775 PINCTRL_GRP_SDIO0_1BIT_1_6,
1776 PINCTRL_GRP_SDIO1_1BIT_0_5,
1777 PINCTRL_GRP_RESERVED,
1778 PINCTRL_GRP_GPIO0_47,
1779 PINCTRL_GRP_CAN0_11,
1780 PINCTRL_GRP_I2C0_11,
1781 PINCTRL_GRP_SWDT0_7_RST,
1782 PINCTRL_GRP_SPI1_3_SS0,
1783 PINCTRL_GRP_TTC0_5_WAV,
1784 PINCTRL_GRP_UART0_11,
1785 PINCTRL_GRP_RESERVED,
1786 },
1787 },
1788 [PINCTRL_PIN_48] = {
1789 .groups = {
1790 PINCTRL_GRP_ETHERNET1_0,
1791 PINCTRL_GRP_RESERVED,
1792 PINCTRL_GRP_SDIO0_1BIT_1_7,
1793 PINCTRL_GRP_SDIO1_1BIT_0_6,
1794 PINCTRL_GRP_RESERVED,
1795 PINCTRL_GRP_GPIO0_48,
1796 PINCTRL_GRP_CAN1_12,
1797 PINCTRL_GRP_I2C1_12,
1798 PINCTRL_GRP_SWDT1_8_CLK,
1799 PINCTRL_GRP_SPI1_3,
1800 PINCTRL_GRP_TTC3_6_CLK,
1801 PINCTRL_GRP_UART1_12,
1802 PINCTRL_GRP_RESERVED,
1803 },
1804 },
1805 [PINCTRL_PIN_49] = {
1806 .groups = {
1807 PINCTRL_GRP_ETHERNET1_0,
1808 PINCTRL_GRP_RESERVED,
1809 PINCTRL_GRP_SDIO0_1_PC,
1810 PINCTRL_GRP_SDIO1_1BIT_0_7,
1811 PINCTRL_GRP_RESERVED,
1812 PINCTRL_GRP_GPIO0_49,
1813 PINCTRL_GRP_CAN1_12,
1814 PINCTRL_GRP_I2C1_12,
1815 PINCTRL_GRP_SWDT1_8_RST,
1816 PINCTRL_GRP_SPI1_3,
1817 PINCTRL_GRP_TTC3_6_WAV,
1818 PINCTRL_GRP_UART1_12,
1819 PINCTRL_GRP_RESERVED,
1820 },
1821 },
1822 [PINCTRL_PIN_50] = {
1823 .groups = {
1824 PINCTRL_GRP_GEMTSU0_1,
1825 PINCTRL_GRP_RESERVED,
1826 PINCTRL_GRP_SDIO0_1_WP,
1827 PINCTRL_GRP_SDIO1_1BIT_0_7,
1828 PINCTRL_GRP_RESERVED,
1829 PINCTRL_GRP_GPIO0_50,
1830 PINCTRL_GRP_CAN0_12,
1831 PINCTRL_GRP_I2C0_12,
1832 PINCTRL_GRP_SWDT0_8_CLK,
1833 PINCTRL_GRP_MDIO1_0,
1834 PINCTRL_GRP_TTC2_6_CLK,
1835 PINCTRL_GRP_UART0_12,
1836 PINCTRL_GRP_RESERVED,
1837 },
1838 },
1839 [PINCTRL_PIN_51] = {
1840 .groups = {
1841 PINCTRL_GRP_GEMTSU0_2,
1842 PINCTRL_GRP_RESERVED,
1843 PINCTRL_GRP_RESERVED,
1844 PINCTRL_GRP_SDIO1_1BIT_0_7,
1845 PINCTRL_GRP_RESERVED,
1846 PINCTRL_GRP_GPIO0_51,
1847 PINCTRL_GRP_CAN0_12,
1848 PINCTRL_GRP_I2C0_12,
1849 PINCTRL_GRP_SWDT0_8_RST,
1850 PINCTRL_GRP_MDIO1_0,
1851 PINCTRL_GRP_TTC2_6_WAV,
1852 PINCTRL_GRP_UART0_12,
1853 PINCTRL_GRP_RESERVED,
1854 },
1855 },
1856 [PINCTRL_PIN_52] = {
1857 .groups = {
1858 PINCTRL_GRP_ETHERNET2_0,
1859 PINCTRL_GRP_USB0_0,
1860 PINCTRL_GRP_RESERVED,
1861 PINCTRL_GRP_RESERVED,
1862 PINCTRL_GRP_RESERVED,
1863 PINCTRL_GRP_GPIO0_52,
1864 PINCTRL_GRP_CAN1_13,
1865 PINCTRL_GRP_I2C1_13,
1866 PINCTRL_GRP_PJTAG0_4,
1867 PINCTRL_GRP_SPI0_4,
1868 PINCTRL_GRP_TTC1_6_CLK,
1869 PINCTRL_GRP_UART1_13,
1870 PINCTRL_GRP_TRACE0_2_CLK,
1871 },
1872 },
1873 [PINCTRL_PIN_53] = {
1874 .groups = {
1875 PINCTRL_GRP_ETHERNET2_0,
1876 PINCTRL_GRP_USB0_0,
1877 PINCTRL_GRP_RESERVED,
1878 PINCTRL_GRP_RESERVED,
1879 PINCTRL_GRP_RESERVED,
1880 PINCTRL_GRP_GPIO0_53,
1881 PINCTRL_GRP_CAN1_13,
1882 PINCTRL_GRP_I2C1_13,
1883 PINCTRL_GRP_PJTAG0_4,
1884 PINCTRL_GRP_SPI0_4_SS2,
1885 PINCTRL_GRP_TTC1_6_WAV,
1886 PINCTRL_GRP_UART1_13,
1887 PINCTRL_GRP_TRACE0_2_CLK,
1888 },
1889 },
1890 [PINCTRL_PIN_54] = {
1891 .groups = {
1892 PINCTRL_GRP_ETHERNET2_0,
1893 PINCTRL_GRP_USB0_0,
1894 PINCTRL_GRP_RESERVED,
1895 PINCTRL_GRP_RESERVED,
1896 PINCTRL_GRP_RESERVED,
1897 PINCTRL_GRP_GPIO0_54,
1898 PINCTRL_GRP_CAN0_13,
1899 PINCTRL_GRP_I2C0_13,
1900 PINCTRL_GRP_PJTAG0_4,
1901 PINCTRL_GRP_SPI0_4_SS1,
1902 PINCTRL_GRP_TTC0_6_CLK,
1903 PINCTRL_GRP_UART0_13,
1904 PINCTRL_GRP_TRACE0_2,
1905 },
1906 },
1907 [PINCTRL_PIN_55] = {
1908 .groups = {
1909 PINCTRL_GRP_ETHERNET2_0,
1910 PINCTRL_GRP_USB0_0,
1911 PINCTRL_GRP_RESERVED,
1912 PINCTRL_GRP_RESERVED,
1913 PINCTRL_GRP_RESERVED,
1914 PINCTRL_GRP_GPIO0_55,
1915 PINCTRL_GRP_CAN0_13,
1916 PINCTRL_GRP_I2C0_13,
1917 PINCTRL_GRP_PJTAG0_4,
1918 PINCTRL_GRP_SPI0_4_SS0,
1919 PINCTRL_GRP_TTC0_6_WAV,
1920 PINCTRL_GRP_UART0_13,
1921 PINCTRL_GRP_TRACE0_2,
1922 },
1923 },
1924 [PINCTRL_PIN_56] = {
1925 .groups = {
1926 PINCTRL_GRP_ETHERNET2_0,
1927 PINCTRL_GRP_USB0_0,
1928 PINCTRL_GRP_RESERVED,
1929 PINCTRL_GRP_RESERVED,
1930 PINCTRL_GRP_RESERVED,
1931 PINCTRL_GRP_GPIO0_56,
1932 PINCTRL_GRP_CAN1_14,
1933 PINCTRL_GRP_I2C1_14,
1934 PINCTRL_GRP_SWDT1_9_CLK,
1935 PINCTRL_GRP_SPI0_4,
1936 PINCTRL_GRP_TTC3_7_CLK,
1937 PINCTRL_GRP_UART1_14,
1938 PINCTRL_GRP_TRACE0_2,
1939 },
1940 },
1941 [PINCTRL_PIN_57] = {
1942 .groups = {
1943 PINCTRL_GRP_ETHERNET2_0,
1944 PINCTRL_GRP_USB0_0,
1945 PINCTRL_GRP_RESERVED,
1946 PINCTRL_GRP_RESERVED,
1947 PINCTRL_GRP_RESERVED,
1948 PINCTRL_GRP_GPIO0_57,
1949 PINCTRL_GRP_CAN1_14,
1950 PINCTRL_GRP_I2C1_14,
1951 PINCTRL_GRP_SWDT1_9_RST,
1952 PINCTRL_GRP_SPI0_4,
1953 PINCTRL_GRP_TTC3_7_WAV,
1954 PINCTRL_GRP_UART1_14,
1955 PINCTRL_GRP_TRACE0_2,
1956 },
1957 },
1958 [PINCTRL_PIN_58] = {
1959 .groups = {
1960 PINCTRL_GRP_ETHERNET2_0,
1961 PINCTRL_GRP_USB0_0,
1962 PINCTRL_GRP_RESERVED,
1963 PINCTRL_GRP_RESERVED,
1964 PINCTRL_GRP_RESERVED,
1965 PINCTRL_GRP_GPIO0_58,
1966 PINCTRL_GRP_CAN0_14,
1967 PINCTRL_GRP_I2C0_14,
1968 PINCTRL_GRP_PJTAG0_5,
1969 PINCTRL_GRP_SPI1_4,
1970 PINCTRL_GRP_TTC2_7_CLK,
1971 PINCTRL_GRP_UART0_14,
1972 PINCTRL_GRP_TRACE0_2,
1973 },
1974 },
1975 [PINCTRL_PIN_59] = {
1976 .groups = {
1977 PINCTRL_GRP_ETHERNET2_0,
1978 PINCTRL_GRP_USB0_0,
1979 PINCTRL_GRP_RESERVED,
1980 PINCTRL_GRP_RESERVED,
1981 PINCTRL_GRP_RESERVED,
1982 PINCTRL_GRP_GPIO0_59,
1983 PINCTRL_GRP_CAN0_14,
1984 PINCTRL_GRP_I2C0_14,
1985 PINCTRL_GRP_PJTAG0_5,
1986 PINCTRL_GRP_SPI1_4_SS2,
1987 PINCTRL_GRP_TTC2_7_WAV,
1988 PINCTRL_GRP_UART0_14,
1989 PINCTRL_GRP_TRACE0_2,
1990 },
1991 },
1992 [PINCTRL_PIN_60] = {
1993 .groups = {
1994 PINCTRL_GRP_ETHERNET2_0,
1995 PINCTRL_GRP_USB0_0,
1996 PINCTRL_GRP_RESERVED,
1997 PINCTRL_GRP_RESERVED,
1998 PINCTRL_GRP_RESERVED,
1999 PINCTRL_GRP_GPIO0_60,
2000 PINCTRL_GRP_CAN1_15,
2001 PINCTRL_GRP_I2C1_15,
2002 PINCTRL_GRP_PJTAG0_5,
2003 PINCTRL_GRP_SPI1_4_SS1,
2004 PINCTRL_GRP_TTC1_7_CLK,
2005 PINCTRL_GRP_UART1_15,
2006 PINCTRL_GRP_TRACE0_2,
2007 },
2008 },
2009 [PINCTRL_PIN_61] = {
2010 .groups = {
2011 PINCTRL_GRP_ETHERNET2_0,
2012 PINCTRL_GRP_USB0_0,
2013 PINCTRL_GRP_RESERVED,
2014 PINCTRL_GRP_RESERVED,
2015 PINCTRL_GRP_RESERVED,
2016 PINCTRL_GRP_GPIO0_61,
2017 PINCTRL_GRP_CAN1_15,
2018 PINCTRL_GRP_I2C1_15,
2019 PINCTRL_GRP_PJTAG0_5,
2020 PINCTRL_GRP_SPI1_4_SS0,
2021 PINCTRL_GRP_TTC1_7_WAV,
2022 PINCTRL_GRP_UART1_15,
2023 PINCTRL_GRP_TRACE0_2,
2024 },
2025 },
2026 [PINCTRL_PIN_62] = {
2027 .groups = {
2028 PINCTRL_GRP_ETHERNET2_0,
2029 PINCTRL_GRP_USB0_0,
2030 PINCTRL_GRP_RESERVED,
2031 PINCTRL_GRP_RESERVED,
2032 PINCTRL_GRP_RESERVED,
2033 PINCTRL_GRP_GPIO0_62,
2034 PINCTRL_GRP_CAN0_15,
2035 PINCTRL_GRP_I2C0_15,
2036 PINCTRL_GRP_SWDT0_9_CLK,
2037 PINCTRL_GRP_SPI1_4,
2038 PINCTRL_GRP_TTC0_7_CLK,
2039 PINCTRL_GRP_UART0_15,
2040 PINCTRL_GRP_TRACE0_2,
2041 },
2042 },
2043 [PINCTRL_PIN_63] = {
2044 .groups = {
2045 PINCTRL_GRP_ETHERNET2_0,
2046 PINCTRL_GRP_USB0_0,
2047 PINCTRL_GRP_RESERVED,
2048 PINCTRL_GRP_RESERVED,
2049 PINCTRL_GRP_RESERVED,
2050 PINCTRL_GRP_GPIO0_63,
2051 PINCTRL_GRP_CAN0_15,
2052 PINCTRL_GRP_I2C0_15,
2053 PINCTRL_GRP_SWDT0_9_RST,
2054 PINCTRL_GRP_SPI1_4,
2055 PINCTRL_GRP_TTC0_7_WAV,
2056 PINCTRL_GRP_UART0_15,
2057 PINCTRL_GRP_TRACE0_2,
2058 },
2059 },
2060 [PINCTRL_PIN_64] = {
2061 .groups = {
2062 PINCTRL_GRP_ETHERNET3_0,
2063 PINCTRL_GRP_USB1_0,
2064 PINCTRL_GRP_SDIO0_1BIT_2_7,
2065 PINCTRL_GRP_RESERVED,
2066 PINCTRL_GRP_RESERVED,
2067 PINCTRL_GRP_GPIO0_64,
2068 PINCTRL_GRP_CAN1_16,
2069 PINCTRL_GRP_I2C1_16,
2070 PINCTRL_GRP_SWDT1_10_CLK,
2071 PINCTRL_GRP_SPI0_5,
2072 PINCTRL_GRP_TTC3_8_CLK,
2073 PINCTRL_GRP_UART1_16,
2074 PINCTRL_GRP_TRACE0_2,
2075 },
2076 },
2077 [PINCTRL_PIN_65] = {
2078 .groups = {
2079 PINCTRL_GRP_ETHERNET3_0,
2080 PINCTRL_GRP_USB1_0,
2081 PINCTRL_GRP_SDIO0_2_CD,
2082 PINCTRL_GRP_RESERVED,
2083 PINCTRL_GRP_RESERVED,
2084 PINCTRL_GRP_GPIO0_65,
2085 PINCTRL_GRP_CAN1_16,
2086 PINCTRL_GRP_I2C1_16,
2087 PINCTRL_GRP_SWDT1_10_RST,
2088 PINCTRL_GRP_SPI0_5_SS2,
2089 PINCTRL_GRP_TTC3_8_WAV,
2090 PINCTRL_GRP_UART1_16,
2091 PINCTRL_GRP_TRACE0_2,
2092 },
2093 },
2094 [PINCTRL_PIN_66] = {
2095 .groups = {
2096 PINCTRL_GRP_ETHERNET3_0,
2097 PINCTRL_GRP_USB1_0,
2098 PINCTRL_GRP_SDIO0_1BIT_2_7,
2099 PINCTRL_GRP_RESERVED,
2100 PINCTRL_GRP_RESERVED,
2101 PINCTRL_GRP_GPIO0_66,
2102 PINCTRL_GRP_CAN0_16,
2103 PINCTRL_GRP_I2C0_16,
2104 PINCTRL_GRP_SWDT0_10_CLK,
2105 PINCTRL_GRP_SPI0_5_SS1,
2106 PINCTRL_GRP_TTC2_8_CLK,
2107 PINCTRL_GRP_UART0_16,
2108 PINCTRL_GRP_TRACE0_2,
2109 },
2110 },
2111 [PINCTRL_PIN_67] = {
2112 .groups = {
2113 PINCTRL_GRP_ETHERNET3_0,
2114 PINCTRL_GRP_USB1_0,
2115 PINCTRL_GRP_SDIO0_1BIT_2_0,
2116 PINCTRL_GRP_RESERVED,
2117 PINCTRL_GRP_RESERVED,
2118 PINCTRL_GRP_GPIO0_67,
2119 PINCTRL_GRP_CAN0_16,
2120 PINCTRL_GRP_I2C0_16,
2121 PINCTRL_GRP_SWDT0_10_RST,
2122 PINCTRL_GRP_SPI0_5_SS0,
2123 PINCTRL_GRP_TTC2_8_WAV,
2124 PINCTRL_GRP_UART0_16,
2125 PINCTRL_GRP_TRACE0_2,
2126 },
2127 },
2128 [PINCTRL_PIN_68] = {
2129 .groups = {
2130 PINCTRL_GRP_ETHERNET3_0,
2131 PINCTRL_GRP_USB1_0,
2132 PINCTRL_GRP_SDIO0_1BIT_2_1,
2133 PINCTRL_GRP_RESERVED,
2134 PINCTRL_GRP_RESERVED,
2135 PINCTRL_GRP_GPIO0_68,
2136 PINCTRL_GRP_CAN1_17,
2137 PINCTRL_GRP_I2C1_17,
2138 PINCTRL_GRP_SWDT1_11_CLK,
2139 PINCTRL_GRP_SPI0_5,
2140 PINCTRL_GRP_TTC1_8_CLK,
2141 PINCTRL_GRP_UART1_17,
2142 PINCTRL_GRP_TRACE0_2,
2143 },
2144 },
2145 [PINCTRL_PIN_69] = {
2146 .groups = {
2147 PINCTRL_GRP_ETHERNET3_0,
2148 PINCTRL_GRP_USB1_0,
2149 PINCTRL_GRP_SDIO0_1BIT_2_2,
2150 PINCTRL_GRP_SDIO1_1_WP,
2151 PINCTRL_GRP_RESERVED,
2152 PINCTRL_GRP_GPIO0_69,
2153 PINCTRL_GRP_CAN1_17,
2154 PINCTRL_GRP_I2C1_17,
2155 PINCTRL_GRP_SWDT1_11_RST,
2156 PINCTRL_GRP_SPI0_5,
2157 PINCTRL_GRP_TTC1_8_WAV,
2158 PINCTRL_GRP_UART1_17,
2159 PINCTRL_GRP_TRACE0_2,
2160 },
2161 },
2162 [PINCTRL_PIN_70] = {
2163 .groups = {
2164 PINCTRL_GRP_ETHERNET3_0,
2165 PINCTRL_GRP_USB1_0,
2166 PINCTRL_GRP_SDIO0_1BIT_2_3,
2167 PINCTRL_GRP_SDIO1_1_PC,
2168 PINCTRL_GRP_RESERVED,
2169 PINCTRL_GRP_GPIO0_70,
2170 PINCTRL_GRP_CAN0_17,
2171 PINCTRL_GRP_I2C0_17,
2172 PINCTRL_GRP_SWDT0_11_CLK,
2173 PINCTRL_GRP_SPI1_5,
2174 PINCTRL_GRP_TTC0_8_CLK,
2175 PINCTRL_GRP_UART0_17,
2176 PINCTRL_GRP_RESERVED,
2177 },
2178 },
2179 [PINCTRL_PIN_71] = {
2180 .groups = {
2181 PINCTRL_GRP_ETHERNET3_0,
2182 PINCTRL_GRP_USB1_0,
2183 PINCTRL_GRP_SDIO0_1BIT_2_4,
2184 PINCTRL_GRP_SDIO1_1BIT_1_0,
2185 PINCTRL_GRP_RESERVED,
2186 PINCTRL_GRP_GPIO0_71,
2187 PINCTRL_GRP_CAN0_17,
2188 PINCTRL_GRP_I2C0_17,
2189 PINCTRL_GRP_SWDT0_11_RST,
2190 PINCTRL_GRP_SPI1_5_SS2,
2191 PINCTRL_GRP_TTC0_8_WAV,
2192 PINCTRL_GRP_UART0_17,
2193 PINCTRL_GRP_RESERVED,
2194 },
2195 },
2196 [PINCTRL_PIN_72] = {
2197 .groups = {
2198 PINCTRL_GRP_ETHERNET3_0,
2199 PINCTRL_GRP_USB1_0,
2200 PINCTRL_GRP_SDIO0_1BIT_2_5,
2201 PINCTRL_GRP_SDIO1_1BIT_1_1,
2202 PINCTRL_GRP_RESERVED,
2203 PINCTRL_GRP_GPIO0_72,
2204 PINCTRL_GRP_CAN1_18,
2205 PINCTRL_GRP_I2C1_18,
2206 PINCTRL_GRP_SWDT1_12_CLK,
2207 PINCTRL_GRP_SPI1_5_SS1,
2208 PINCTRL_GRP_RESERVED,
2209 PINCTRL_GRP_UART1_18,
2210 PINCTRL_GRP_RESERVED,
2211 },
2212 },
2213 [PINCTRL_PIN_73] = {
2214 .groups = {
2215 PINCTRL_GRP_ETHERNET3_0,
2216 PINCTRL_GRP_USB1_0,
2217 PINCTRL_GRP_SDIO0_1BIT_2_6,
2218 PINCTRL_GRP_SDIO1_1BIT_1_2,
2219 PINCTRL_GRP_RESERVED,
2220 PINCTRL_GRP_GPIO0_73,
2221 PINCTRL_GRP_CAN1_18,
2222 PINCTRL_GRP_I2C1_18,
2223 PINCTRL_GRP_SWDT1_12_RST,
2224 PINCTRL_GRP_SPI1_5_SS0,
2225 PINCTRL_GRP_RESERVED,
2226 PINCTRL_GRP_UART1_18,
2227 PINCTRL_GRP_RESERVED,
2228 },
2229 },
2230 [PINCTRL_PIN_74] = {
2231 .groups = {
2232 PINCTRL_GRP_ETHERNET3_0,
2233 PINCTRL_GRP_USB1_0,
2234 PINCTRL_GRP_SDIO0_1BIT_2_7,
2235 PINCTRL_GRP_SDIO1_1BIT_1_3,
2236 PINCTRL_GRP_RESERVED,
2237 PINCTRL_GRP_GPIO0_74,
2238 PINCTRL_GRP_CAN0_18,
2239 PINCTRL_GRP_I2C0_18,
2240 PINCTRL_GRP_SWDT0_12_CLK,
2241 PINCTRL_GRP_SPI1_5,
2242 PINCTRL_GRP_RESERVED,
2243 PINCTRL_GRP_UART0_18,
2244 PINCTRL_GRP_RESERVED,
2245 },
2246 },
2247 [PINCTRL_PIN_75] = {
2248 .groups = {
2249 PINCTRL_GRP_ETHERNET3_0,
2250 PINCTRL_GRP_USB1_0,
2251 PINCTRL_GRP_SDIO0_2_PC,
2252 PINCTRL_GRP_SDIO1_1BIT_1_3,
2253 PINCTRL_GRP_RESERVED,
2254 PINCTRL_GRP_GPIO0_75,
2255 PINCTRL_GRP_CAN0_18,
2256 PINCTRL_GRP_I2C0_18,
2257 PINCTRL_GRP_SWDT0_12_RST,
2258 PINCTRL_GRP_SPI1_5,
2259 PINCTRL_GRP_RESERVED,
2260 PINCTRL_GRP_UART0_18,
2261 PINCTRL_GRP_RESERVED,
2262 },
2263 },
2264 [PINCTRL_PIN_76] = {
2265 .groups = {
2266 PINCTRL_GRP_RESERVED,
2267 PINCTRL_GRP_RESERVED,
2268 PINCTRL_GRP_SDIO0_2_WP,
2269 PINCTRL_GRP_SDIO1_1BIT_1_3,
2270 PINCTRL_GRP_RESERVED,
2271 PINCTRL_GRP_GPIO0_76,
2272 PINCTRL_GRP_CAN1_19,
2273 PINCTRL_GRP_I2C1_19,
2274 PINCTRL_GRP_MDIO0_0,
2275 PINCTRL_GRP_MDIO1_1,
2276 PINCTRL_GRP_MDIO2_0,
2277 PINCTRL_GRP_MDIO3_0,
2278 PINCTRL_GRP_RESERVED,
2279 },
2280 },
2281 [PINCTRL_PIN_77] = {
2282 .groups = {
2283 PINCTRL_GRP_RESERVED,
2284 PINCTRL_GRP_RESERVED,
2285 PINCTRL_GRP_RESERVED,
2286 PINCTRL_GRP_SDIO1_1_CD,
2287 PINCTRL_GRP_RESERVED,
2288 PINCTRL_GRP_GPIO0_77,
2289 PINCTRL_GRP_CAN1_19,
2290 PINCTRL_GRP_I2C1_19,
2291 PINCTRL_GRP_MDIO0_0,
2292 PINCTRL_GRP_MDIO1_1,
2293 PINCTRL_GRP_MDIO2_0,
2294 PINCTRL_GRP_MDIO3_0,
2295 PINCTRL_GRP_RESERVED,
2296 },
2297 },
2298};
2299
2300/**
2301 * pm_api_pinctrl_get_num_pins() - PM call to request number of pins
2302 * @npins Number of pins
2303 *
2304 * This function is used by master to get number of pins
2305 *
2306 * @return Returns success.
2307 */
2308enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins)
2309{
2310 *npins = MAX_PIN;
2311
2312 return PM_RET_SUCCESS;
2313}
2314
2315/**
2316 * pm_api_pinctrl_get_num_functions() - PM call to request number of functions
2317 * @nfuncs Number of functions
2318 *
2319 * This function is used by master to get number of functions
2320 *
2321 * @return Returns success.
2322 */
2323enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs)
2324{
2325 *nfuncs = MAX_FUNCTION;
2326
2327 return PM_RET_SUCCESS;
2328}
2329
2330/**
2331 * pm_api_pinctrl_get_num_func_groups() - PM call to request number of
2332 * function groups
2333 * @fid Function Id
2334 * @ngroups Number of function groups
2335 *
2336 * This function is used by master to get number of function groups
2337 *
2338 * @return Returns success.
2339 */
2340enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid,
2341 unsigned int *ngroups)
2342{
2343 int i = 0;
2344 uint16_t *grps;
2345
2346 if (fid >= MAX_FUNCTION)
2347 return PM_RET_ERROR_ARGS;
2348
2349 *ngroups = 0;
2350
2351 grps = *pinctrl_functions[fid].groups;
2352 if (!grps)
2353 return PM_RET_SUCCESS;
2354
2355 while (grps[i++] != (uint16_t)END_OF_GROUPS)
2356 (*ngroups)++;
2357
2358 return PM_RET_SUCCESS;
2359}
2360
2361/**
2362 * pm_api_pinctrl_get_function_name() - PM call to request a function name
2363 * @fid Function ID
2364 * @name Name of function (max 16 bytes)
2365 *
2366 * This function is used by master to get name of function specified
2367 * by given function ID.
2368 *
2369 * @return Returns success. In case of error, name data is 0.
2370 */
2371enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid,
2372 char *name)
2373{
2374 if (fid >= MAX_FUNCTION)
2375 memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
2376 else
2377 memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
2378
2379 return PM_RET_SUCCESS;
2380}
2381
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2382/**
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2383 * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function
2384 * groups of function Id
2385 * @fid Function ID
2386 * @index Index of next function groups
2387 * @groups Function groups
2388 *
2389 * This function is used by master to get function groups specified
2390 * by given function Id. This API will return 6 function groups with
2391 * a single response. To get other function groups, master should call
2392 * same API in loop with new function groups index till error is returned.
2393 *
2394 * E.g First call should have index 0 which will return function groups
2395 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
2396 * function groups 6, 7, 8, 9, 10 and 11 and so on.
2397 *
2398 * Return: Returns status, either success or error+reason.
2399 */
2400enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid,
2401 unsigned int index,
2402 uint16_t *groups)
2403{
2404 int i;
2405 uint16_t *grps;
2406
2407 if (fid >= MAX_FUNCTION)
2408 return PM_RET_ERROR_ARGS;
2409
2410 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
2411
2412 grps = *pinctrl_functions[fid].groups;
2413 if (!grps)
2414 return PM_RET_SUCCESS;
2415
2416 /* Skip groups till index */
2417 for (i = 0; i < index; i++)
2418 if (grps[i] == (uint16_t)END_OF_GROUPS)
2419 return PM_RET_SUCCESS;
2420
2421 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
2422 groups[i] = grps[index + i];
2423 if (groups[i] == (uint16_t)END_OF_GROUPS)
2424 break;
2425 }
2426
2427 return PM_RET_SUCCESS;
2428}
2429
2430/**
2431 * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin
2432 * groups of pin
2433 * @pin Pin
2434 * @index Index of next pin groups
2435 * @groups pin groups
2436 *
2437 * This function is used by master to get pin groups specified
2438 * by given pin Id. This API will return 6 pin groups with
2439 * a single response. To get other pin groups, master should call
2440 * same API in loop with new pin groups index till error is returned.
2441 *
2442 * E.g First call should have index 0 which will return pin groups
2443 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return
2444 * pin groups 6, 7, 8, 9, 10 and 11 and so on.
2445 *
2446 * Return: Returns status, either success or error+reason.
2447 */
2448enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin,
2449 unsigned int index,
2450 uint16_t *groups)
2451{
2452 int i;
2453 uint16_t *grps, zeros[MAX_PIN_GROUPS] = {0};
2454
2455 if (pin >= MAX_PIN)
2456 return PM_RET_ERROR_ARGS;
2457
2458 grps = zynqmp_pin_groups[pin].groups;
2459
2460 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
2461
2462 if (!memcmp(grps, zeros, MAX_PIN_GROUPS))
2463 return PM_RET_SUCCESS;
2464
2465 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
2466 if ((index + i) >= MAX_PIN_GROUPS)
2467 break;
2468 groups[i] = grps[index + i];
2469 }
2470
2471 return PM_RET_SUCCESS;
2472}
2473
2474/**
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2475 * pm_api_pinctrl_get_function() - Read function id set for the given pin
2476 * @pin Pin number
2477 * @nid Node ID of function currently set for given pin
2478 *
2479 * This function provides the function currently set for the given pin.
2480 *
2481 * @return Returns status, either success or error+reason
2482 */
2483enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2484 unsigned int *id)
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2485{
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2486 int i = 0, j = 0, ret = PM_RET_SUCCESS;
2487 unsigned int reg, val, gid;
2488 uint16_t *grps;
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2489
2490 reg = IOU_SLCR_BASEADDR + 4 * pin;
2491 ret = pm_mmio_read(reg, &val);
2492 if (ret)
2493 return ret;
2494
2495 val &= PINCTRL_FUNCTION_MASK;
2496
2497 for (i = 0; i < NFUNCS_PER_PIN; i++)
2498 if (val == pm_pinctrl_mux[i])
2499 break;
2500
2501 if (i == NFUNCS_PER_PIN)
2502 return PM_RET_ERROR_NOTSUPPORTED;
2503
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2504 gid = zynqmp_pin_groups[pin].groups[i];
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2505
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2506 for (i = 0; i < MAX_FUNCTION; i++) {
2507 grps = *pinctrl_functions[i].groups;
2508 if (!grps)
2509 continue;
2510 if (val != pinctrl_functions[i].regval)
2511 continue;
2512
2513 for (j = 0; grps[j] != (uint16_t)END_OF_GROUPS; j++) {
2514 if (gid == grps[j]) {
2515 *id = i;
2516 goto done;
2517 }
2518 }
2519 }
2520 if (i == MAX_FUNCTION)
2521 ret = PM_RET_ERROR_ARGS;
2522done:
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2523 return ret;
2524}
2525
2526/**
2527 * pm_api_pinctrl_set_function() - Set function id set for the given pin
2528 * @pin Pin number
2529 * @nid Node ID of function to set for given pin
2530 *
2531 * This function provides the function currently set for the given pin.
2532 *
2533 * @return Returns status, either success or error+reason
2534 */
2535enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2536 unsigned int fid)
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2537{
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2538 int i = 0;
2539 unsigned int reg, val, gid;
2540 uint16_t *grps;
2541
2542 reg = IOU_SLCR_BASEADDR + 4 * pin;
2543 val = pinctrl_functions[fid].regval;
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2544
2545 for (i = 0; i < NFUNCS_PER_PIN; i++)
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2546 if (val == pm_pinctrl_mux[i])
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2547 break;
2548
2549 if (i == NFUNCS_PER_PIN)
2550 return PM_RET_ERROR_NOTSUPPORTED;
2551
Rajan Vajad5dd8362018-01-30 04:16:31 -0800[diff] [blame^]2552 gid = zynqmp_pin_groups[pin].groups[i];
2553 grps = *pinctrl_functions[fid].groups;
2554 if (!grps)
2555 return PM_RET_ERROR_NOTSUPPORTED;
2556
2557 for (i = 0; grps[i] != (uint16_t)END_OF_GROUPS; i++) {
2558 if (gid == grps[i])
2559 break;
2560 }
2561 if (gid != grps[i])
2562 return PM_RET_ERROR_NOTSUPPORTED;
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800[diff] [blame]2563
2564 return pm_mmio_write(reg, PINCTRL_FUNCTION_MASK, val);
2565}
Rajan Vaja5e139e72018-01-17 02:39:22 -0800[diff] [blame]2566
2567/**
2568 * pm_api_pinctrl_set_config() - Set configuration parameter for given pin
2569 * @pin: Pin for which configuration is to be set
2570 * @param: Configuration parameter to be set
2571 * @value: Value to be set for configuration parameter
2572 *
2573 * This function sets value of requested configuration parameter for given pin.
2574 *
2575 * @return Returns status, either success or error+reason
2576 */
2577enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
2578 unsigned int param,
2579 unsigned int value)
2580{
2581 int ret;
2582 unsigned int reg, mask, val, offset;
2583
2584 if (param >= PINCTRL_CONFIG_MAX)
2585 return PM_RET_ERROR_NOTSUPPORTED;
2586
2587 if (pin >= PINCTRL_NUM_MIOS)
2588 return PM_RET_ERROR_ARGS;
2589
2590 mask = 1 << PINCTRL_PIN_OFFSET(pin);
2591
2592 switch (param) {
2593 case PINCTRL_CONFIG_SLEW_RATE:
2594 if (value != PINCTRL_SLEW_RATE_FAST &&
2595 value != PINCTRL_SLEW_RATE_SLOW)
2596 return PM_RET_ERROR_ARGS;
2597
2598 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2599 PINCTRL_SLEWCTRL_REG_OFFSET,
2600 pin);
2601 val = value << PINCTRL_PIN_OFFSET(pin);
2602 ret = pm_mmio_write(reg, mask, val);
2603 break;
2604 case PINCTRL_CONFIG_BIAS_STATUS:
2605 if (value != PINCTRL_BIAS_ENABLE &&
2606 value != PINCTRL_BIAS_DISABLE)
2607 return PM_RET_ERROR_ARGS;
2608
2609 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2610 PINCTRL_PULLSTAT_REG_OFFSET,
2611 pin);
2612
2613 offset = PINCTRL_PIN_OFFSET(pin);
2614 if (reg == IOU_SLCR_BANK1_CTRL5)
2615 offset = (offset < 12) ? (offset + 14) : (offset - 12);
2616
2617 val = value << offset;
2618 mask = 1 << offset;
2619 ret = pm_mmio_write(reg, mask, val);
2620 break;
2621 case PINCTRL_CONFIG_PULL_CTRL:
2622
2623 if (value != PINCTRL_BIAS_PULL_DOWN &&
2624 value != PINCTRL_BIAS_PULL_UP)
2625 return PM_RET_ERROR_ARGS;
2626
2627 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2628 PINCTRL_PULLSTAT_REG_OFFSET,
2629 pin);
2630
2631 offset = PINCTRL_PIN_OFFSET(pin);
2632 if (reg == IOU_SLCR_BANK1_CTRL5)
2633 offset = (offset < 12) ? (offset + 14) : (offset - 12);
2634
2635 val = PINCTRL_BIAS_ENABLE << offset;
2636 ret = pm_mmio_write(reg, 1 << offset, val);
2637 if (ret)
2638 return ret;
2639
2640 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2641 PINCTRL_PULLCTRL_REG_OFFSET,
2642 pin);
2643 val = value << PINCTRL_PIN_OFFSET(pin);
2644 ret = pm_mmio_write(reg, mask, val);
2645 break;
2646 case PINCTRL_CONFIG_SCHMITT_CMOS:
2647 if (value != PINCTRL_INPUT_TYPE_CMOS &&
2648 value != PINCTRL_INPUT_TYPE_SCHMITT)
2649 return PM_RET_ERROR_ARGS;
2650
2651 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2652 PINCTRL_SCHCMOS_REG_OFFSET,
2653 pin);
2654
2655 val = value << PINCTRL_PIN_OFFSET(pin);
2656 ret = pm_mmio_write(reg, mask, val);
2657 break;
2658 case PINCTRL_CONFIG_DRIVE_STRENGTH:
2659 if (value > PINCTRL_DRIVE_STRENGTH_12MA)
2660 return PM_RET_ERROR_ARGS;
2661
2662 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2663 PINCTRL_DRVSTRN0_REG_OFFSET,
2664 pin);
2665 val = (value >> 1) << PINCTRL_PIN_OFFSET(pin);
2666 ret = pm_mmio_write(reg, mask, val);
2667 if (ret)
2668 return ret;
2669
2670 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2671 PINCTRL_DRVSTRN1_REG_OFFSET,
2672 pin);
2673 val = (value & 0x01) << PINCTRL_PIN_OFFSET(pin);
2674 ret = pm_mmio_write(reg, mask, val);
2675 break;
2676 default:
2677 ERROR("Invalid parameter %u\n", param);
2678 ret = PM_RET_ERROR_NOTSUPPORTED;
2679 break;
2680 }
2681
2682 return ret;
2683}
2684
2685/**
2686 * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin
2687 * @pin: Pin for which configuration is to be read
2688 * @param: Configuration parameter to be read
2689 * @value: buffer to store value of configuration parameter
2690 *
2691 * This function reads value of requested configuration parameter for given pin.
2692 *
2693 * @return Returns status, either success or error+reason
2694 */
2695enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
2696 unsigned int param,
2697 unsigned int *value)
2698{
2699 int ret;
2700 unsigned int reg, val;
2701
2702 if (param >= PINCTRL_CONFIG_MAX)
2703 return PM_RET_ERROR_NOTSUPPORTED;
2704
2705 if (pin >= PINCTRL_NUM_MIOS)
2706 return PM_RET_ERROR_ARGS;
2707
2708 switch (param) {
2709 case PINCTRL_CONFIG_SLEW_RATE:
2710 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2711 PINCTRL_SLEWCTRL_REG_OFFSET,
2712 pin);
2713
2714 ret = pm_mmio_read(reg, &val);
2715 if (ret)
2716 return ret;
2717
2718 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
2719 break;
2720 case PINCTRL_CONFIG_BIAS_STATUS:
2721 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2722 PINCTRL_PULLSTAT_REG_OFFSET,
2723 pin);
2724
2725 ret = pm_mmio_read(reg, &val);
2726 if (ret)
2727 return ret;
2728
2729 if (reg == IOU_SLCR_BANK1_CTRL5)
2730 val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF);
2731
2732 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
2733 break;
2734 case PINCTRL_CONFIG_PULL_CTRL:
2735
2736 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2737 PINCTRL_PULLCTRL_REG_OFFSET,
2738 pin);
2739
2740 ret = pm_mmio_read(reg, &val);
2741 if (ret)
2742 return ret;
2743
2744 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
2745 break;
2746 case PINCTRL_CONFIG_SCHMITT_CMOS:
2747 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2748 PINCTRL_SCHCMOS_REG_OFFSET,
2749 pin);
2750
2751 ret = pm_mmio_read(reg, &val);
2752 if (ret)
2753 return ret;
2754
2755 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
2756 break;
2757 case PINCTRL_CONFIG_DRIVE_STRENGTH:
2758 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2759 PINCTRL_DRVSTRN0_REG_OFFSET,
2760 pin);
2761 ret = pm_mmio_read(reg, &val);
2762 if (ret)
2763 return ret;
2764
2765 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1;
2766
2767 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2768 PINCTRL_DRVSTRN1_REG_OFFSET,
2769 pin);
2770 ret = pm_mmio_read(reg, &val);
2771 if (ret)
2772 return ret;
2773
2774 *value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
2775 break;
2776 case PINCTRL_CONFIG_VOLTAGE_STATUS:
2777 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
2778 PINCTRL_VOLTAGE_STAT_REG_OFFSET,
2779 pin);
2780
2781 ret = pm_mmio_read(reg, &val);
2782 if (ret)
2783 return ret;
2784
2785 *value = val & PINCTRL_VOLTAGE_STATUS_MASK;
2786 break;
2787 default:
2788 return PM_RET_ERROR_NOTSUPPORTED;
2789 }
2790
2791 return 0;
2792}