blob: 8f7d1e9a197dcc41b14f8d9a37e2b8752fd4f58f [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
Varun Wadekar4edc17c2017-11-20 17:14:47 -08002 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl31/bl31.h>
10#include <common/bl_common.h>
11#include <common/interrupt_props.h>
12#include <drivers/console.h>
13#include <context.h>
14#include <lib/el3_runtime/context_mgmt.h>
15#include <cortex_a57.h>
16#include <common/debug.h>
17#include <denver.h>
18#include <drivers/arm/gic_common.h>
19#include <drivers/arm/gicv2.h>
20#include <bl31/interrupt_mgmt.h>
21#include <mce.h>
Dilan Lee4e7a63c2017-08-10 16:01:42 +080022#include <mce_private.h>
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -070023#include <memctrl.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070024#include <plat/common/platform.h>
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -070025#include <smmu.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070026#include <spe.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070027#include <tegra_def.h>
28#include <tegra_platform.h>
29#include <tegra_private.h>
30#include <lib/xlat_tables/xlat_tables_v2.h>
31
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070032/* ID for spe-console */
33#define TEGRA_CONSOLE_SPE_ID 0xFE
34
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070035/*******************************************************************************
Kalyani Chidambaram Vaidyanathan3118cbf2019-10-02 13:57:23 -070036 * Structure to store the SCR addresses and its expected settings.
37 *******************************************************************************
38 */
39typedef struct {
40 uint32_t scr_addr;
41 uint32_t scr_val;
42} scr_settings_t;
43
44static const scr_settings_t t194_scr_settings[] = {
45 { SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL },
46 { SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL },
47 { SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL },
48 { SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL },
49 { SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL },
50 { SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL },
51 { SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL },
52 { SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL },
53 { MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL }
54};
55
56/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070057 * The Tegra power domain tree has a single system level power domain i.e. a
58 * single root node. The first entry in the power domain descriptor specifies
59 * the number of power domains at the highest power level.
60 *******************************************************************************
61 */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080062static const uint8_t tegra_power_domain_tree_desc[] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070063 /* No of root nodes */
64 1,
65 /* No of clusters */
66 PLATFORM_CLUSTER_COUNT,
67 /* No of CPU cores - cluster0 */
68 PLATFORM_MAX_CPUS_PER_CLUSTER,
69 /* No of CPU cores - cluster1 */
Varun Wadekara07d1c72017-08-23 14:59:09 -070070 PLATFORM_MAX_CPUS_PER_CLUSTER,
71 /* No of CPU cores - cluster2 */
72 PLATFORM_MAX_CPUS_PER_CLUSTER,
73 /* No of CPU cores - cluster3 */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070074 PLATFORM_MAX_CPUS_PER_CLUSTER
75};
76
Varun Wadekara7265be2017-04-28 08:45:53 -070077/*******************************************************************************
78 * This function returns the Tegra default topology tree information.
79 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080080const uint8_t *plat_get_power_domain_tree_desc(void)
Varun Wadekara7265be2017-04-28 08:45:53 -070081{
82 return tegra_power_domain_tree_desc;
83}
84
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070085/*
86 * Table of regions to map using the MMU.
87 */
88static const mmap_region_t tegra_mmap[] = {
Varun Wadekar03aa0142018-01-23 14:51:40 -080089 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080090 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar602cf7e2018-04-03 13:10:48 -070091 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080093 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080094 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080095 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080096 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070097#if !ENABLE_CONSOLE_SPE
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080098 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
99 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
100 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
101 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
102 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
103 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700104#endif
Varun Wadekar03aa0142018-01-23 14:51:40 -0800105 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800107 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800109 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800111 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */
steven kaoe5796062018-01-02 19:09:04 -0800112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800113 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800114 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800115 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */
116 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
117 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800118 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700119#if ENABLE_CONSOLE_SPE
Varun Wadekar03aa0142018-01-23 14:51:40 -0800120 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700121 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
122#endif
Varun Wadekar03aa0142018-01-23 14:51:40 -0800123 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */
steven kaoe5796062018-01-02 19:09:04 -0800124 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800125 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800126 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800127 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800128 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800129 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800130 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800131 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800132 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800133 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800134 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800135 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800136 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700137 {0}
138};
139
140/*******************************************************************************
141 * Set up the pagetables as per the platform memory map & initialize the MMU
142 ******************************************************************************/
143const mmap_region_t *plat_get_mmio_map(void)
144{
145 /* MMIO space */
146 return tegra_mmap;
147}
148
149/*******************************************************************************
150 * Handler to get the System Counter Frequency
151 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800152uint32_t plat_get_syscnt_freq2(void)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700153{
154 return 31250000;
155}
156
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700157#if !ENABLE_CONSOLE_SPE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700158/*******************************************************************************
159 * Maximum supported UART controllers
160 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800161#define TEGRA194_MAX_UART_PORTS 7
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700162
163/*******************************************************************************
164 * This variable holds the UART port base addresses
165 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800166static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700167 0, /* undefined - treated as an error case */
168 TEGRA_UARTA_BASE,
169 TEGRA_UARTB_BASE,
170 TEGRA_UARTC_BASE,
171 TEGRA_UARTD_BASE,
172 TEGRA_UARTE_BASE,
173 TEGRA_UARTF_BASE,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800174 TEGRA_UARTG_BASE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700175};
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700176#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700177
178/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700179 * Enable console corresponding to the console ID
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700180 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700181void plat_enable_console(int32_t id)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700182{
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700183 uint32_t console_clock = 0U;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700184
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700185#if ENABLE_CONSOLE_SPE
Andre Przywaraabe890f2020-01-25 00:58:35 +0000186 static console_t spe_console;
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700187
188 if (id == TEGRA_CONSOLE_SPE_ID) {
189 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
190 console_clock,
191 TEGRA_CONSOLE_BAUDRATE,
192 &spe_console);
Andre Przywara15069ea2020-01-25 00:58:35 +0000193 console_set_scope(&spe_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700194 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800195 }
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700196#else
Andre Przywara98b5a112020-01-25 00:58:35 +0000197 static console_t uart_console;
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800198
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700199 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
200 /*
201 * Reference clock used by the FPGAs is a lot slower.
202 */
203 if (tegra_platform_is_fpga()) {
204 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
205 } else {
206 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
207 }
208
209 (void)console_16550_register(tegra194_uart_addresses[id],
210 console_clock,
211 TEGRA_CONSOLE_BAUDRATE,
212 &uart_console);
Andre Przywara15069ea2020-01-25 00:58:35 +0000213 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700214 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
215 }
216#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700217}
218
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700219/*******************************************************************************
Kalyani Chidambaram Vaidyanathan3118cbf2019-10-02 13:57:23 -0700220 * Verify SCR settings
221 ******************************************************************************/
222static inline bool tegra194_is_scr_valid(void)
223{
224 uint32_t scr_val;
225 bool ret = true;
226
227 for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) {
228 scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr);
229 if (scr_val != t194_scr_settings[i].scr_val) {
230 ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr);
231 ret = false;
232 }
233 }
234 return ret;
235}
236
237/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700238 * Handler for early platform setup
239 ******************************************************************************/
240void plat_early_platform_setup(void)
241{
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700242 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
243 uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
244 uint64_t actlr_elx;
245
kalyanic0a2cc612019-09-13 14:49:39 -0700246 /* Verify chip id is t194 */
247 assert(tegra_chipid_is_t194());
248
Kalyani Chidambaram Vaidyanathan3118cbf2019-10-02 13:57:23 -0700249 /* Verify SCR settings */
250 if (tegra_platform_is_silicon()) {
251 assert(tegra194_is_scr_valid());
252 }
253
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700254 /* sanity check MCE firmware compatibility */
255 mce_verify_firmware_version();
256
David Pu70f65972019-03-18 15:14:49 -0700257#if RAS_EXTENSION
258 /* Enable Uncorrectable RAS error */
259 tegra194_ras_enable();
260#endif
261
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800262 /*
263 * Program XUSB STREAMIDs
264 * ======================
265 * T19x XUSB has support for XUSB virtualization. It will have one
Ajay Gupta81621092017-08-01 15:53:04 -0700266 * physical function (PF) and four Virtual function (VF)
267 *
268 * There were below two SIDs for XUSB until T186.
269 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU
270 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU
271 *
272 * We have below four new SIDs added for VF(s)
273 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU
274 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU
275 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU
276 * 6) #define TEGRA_SID_XUSB_VF3 0x60U
277 *
278 * When virtualization is enabled then we have to disable SID override
279 * and program above SIDs in below newly added SID registers in XUSB
280 * PADCTL MMIO space. These registers are TZ protected and so need to
281 * be done in ATF.
282 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
283 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
284 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
285 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
286 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
287 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
288 *
289 * This change disables SID override and programs XUSB SIDs in
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800290 * above registers to support both virtualization and
291 * non-virtualization platforms
Ajay Gupta81621092017-08-01 15:53:04 -0700292 */
Varun Wadekara2eb6632018-03-23 10:44:40 -0700293 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
294
295 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
296 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
Anthony Zhou9de77f62019-11-13 18:36:07 +0800297 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
298 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST);
Varun Wadekara2eb6632018-03-23 10:44:40 -0700299 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
300 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
Anthony Zhou9de77f62019-11-13 18:36:07 +0800301 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
302 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0);
Varun Wadekara2eb6632018-03-23 10:44:40 -0700303 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
304 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
Anthony Zhou9de77f62019-11-13 18:36:07 +0800305 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
306 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1);
Varun Wadekara2eb6632018-03-23 10:44:40 -0700307 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
308 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
Anthony Zhou9de77f62019-11-13 18:36:07 +0800309 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
310 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2);
Varun Wadekara2eb6632018-03-23 10:44:40 -0700311 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
312 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
Anthony Zhou9de77f62019-11-13 18:36:07 +0800313 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
314 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3);
Varun Wadekara2eb6632018-03-23 10:44:40 -0700315 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
316 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
Anthony Zhou9de77f62019-11-13 18:36:07 +0800317 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE +
318 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV);
Varun Wadekara2eb6632018-03-23 10:44:40 -0700319 }
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700320
321 /*
322 * Enable dual execution optimized translations for all ELx.
323 */
324 if (enable_ccplex_lock_step != 0U) {
325 actlr_elx = read_actlr_el3();
326 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
327 write_actlr_el3(actlr_elx);
Kalyani Chidambaram Vaidyanathan05df7ac2019-11-07 13:31:19 -0800328 /* check if the bit is actually set */
329 assert((read_actlr_el3() & DENVER_CPU_ENABLE_DUAL_EXEC_EL3) != 0ULL);
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700330
331 actlr_elx = read_actlr_el2();
332 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
333 write_actlr_el2(actlr_elx);
Kalyani Chidambaram Vaidyanathan05df7ac2019-11-07 13:31:19 -0800334 /* check if the bit is actually set */
335 assert((read_actlr_el2() & DENVER_CPU_ENABLE_DUAL_EXEC_EL2) != 0ULL);
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700336
337 actlr_elx = read_actlr_el1();
338 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
339 write_actlr_el1(actlr_elx);
Kalyani Chidambaram Vaidyanathan05df7ac2019-11-07 13:31:19 -0800340 /* check if the bit is actually set */
341 assert((read_actlr_el1() & DENVER_CPU_ENABLE_DUAL_EXEC_EL1) != 0ULL);
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700342 }
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700343}
344
Varun Wadekar362a6b22017-11-10 11:04:42 -0800345/* Secure IRQs for Tegra194 */
346static const interrupt_prop_t tegra194_interrupt_props[] = {
Varun Wadekarbef02f02020-04-17 19:09:21 -0700347 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
348 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700349 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar362a6b22017-11-10 11:04:42 -0800350 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700351};
352
353/*******************************************************************************
354 * Initialize the GIC and SGIs
355 ******************************************************************************/
356void plat_gic_setup(void)
357{
Varun Wadekar362a6b22017-11-10 11:04:42 -0800358 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
359 tegra_gic_init();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700360
361 /*
Varun Wadekar362a6b22017-11-10 11:04:42 -0800362 * Initialize the FIQ handler
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700363 */
Varun Wadekar362a6b22017-11-10 11:04:42 -0800364 tegra_fiq_handler_setup();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700365}
366
367/*******************************************************************************
368 * Return pointer to the BL31 params from previous bootloader
369 ******************************************************************************/
370struct tegra_bl31_params *plat_get_bl31_params(void)
371{
Steven Kao08ac2732018-02-09 21:35:20 +0800372 uint64_t val;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700373
Steven Kao08ac2732018-02-09 21:35:20 +0800374 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) &
375 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT;
376 val <<= 32;
377 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700378
379 return (struct tegra_bl31_params *)(uintptr_t)val;
380}
381
382/*******************************************************************************
383 * Return pointer to the BL31 platform params from previous bootloader
384 ******************************************************************************/
385plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
386{
Steven Kao08ac2732018-02-09 21:35:20 +0800387 uint64_t val;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700388
Steven Kao08ac2732018-02-09 21:35:20 +0800389 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) &
390 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT;
391 val <<= 32;
392 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700393
394 return (plat_params_from_bl2_t *)(uintptr_t)val;
395}
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800396
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700397/*******************************************************************************
398 * Handler for late platform setup
399 ******************************************************************************/
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800400void plat_late_platform_setup(void)
401{
Steven Kao8f4f1022017-12-13 06:39:15 +0800402#if ENABLE_STRICT_CHECKING_MODE
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800403 /*
404 * Enable strict checking after programming the GSC for
405 * enabling TZSRAM and TZDRAM
406 */
407 mce_enable_strict_checking();
Anthony Zhou10b970c2020-02-05 20:42:36 +0800408 mce_verify_strict_checking();
Steven Kao8f4f1022017-12-13 06:39:15 +0800409#endif
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800410}
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700411
412/*******************************************************************************
413 * Handler to indicate support for System Suspend
414 ******************************************************************************/
415bool plat_supports_system_suspend(void)
416{
417 return true;
418}
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -0700419
420/*******************************************************************************
421 * Platform specific runtime setup.
422 ******************************************************************************/
423void plat_runtime_setup(void)
424{
425 /*
426 * During cold boot, it is observed that the arbitration
427 * bit is set in the Memory controller leading to false
428 * error interrupts in the non-secure world. To avoid
429 * this, clean the interrupt status register before
430 * booting into the non-secure world
431 */
432 tegra_memctrl_clear_pending_interrupts();
433
434 /*
435 * During boot, USB3 and flash media (SDMMC/SATA) devices need
436 * access to IRAM. Because these clients connect to the MC and
437 * do not have a direct path to the IRAM, the MC implements AHB
438 * redirection during boot to allow path to IRAM. In this mode
439 * accesses to a programmed memory address aperture are directed
440 * to the AHB bus, allowing access to the IRAM. This mode must be
441 * disabled before we jump to the non-secure world.
442 */
443 tegra_memctrl_disable_ahb_redirection();
444
445 /*
446 * Verify the integrity of the previously configured SMMU(s) settings
447 */
448 tegra_smmu_verify();
449}