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Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
Varun Wadekar4edc17c2017-11-20 17:14:47 -08002 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl31/bl31.h>
10#include <common/bl_common.h>
11#include <common/interrupt_props.h>
12#include <drivers/console.h>
13#include <context.h>
14#include <lib/el3_runtime/context_mgmt.h>
15#include <cortex_a57.h>
16#include <common/debug.h>
17#include <denver.h>
18#include <drivers/arm/gic_common.h>
19#include <drivers/arm/gicv2.h>
20#include <bl31/interrupt_mgmt.h>
21#include <mce.h>
Dilan Lee4e7a63c2017-08-10 16:01:42 +080022#include <mce_private.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070023#include <plat/common/platform.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070024#include <spe.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070025#include <tegra_def.h>
Varun Wadekar128f46a2019-10-24 16:06:12 -070026#include <tegra_mc_def.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070027#include <tegra_platform.h>
28#include <tegra_private.h>
29#include <lib/xlat_tables/xlat_tables_v2.h>
30
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070031/* ID for spe-console */
32#define TEGRA_CONSOLE_SPE_ID 0xFE
33
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070034/*******************************************************************************
35 * The Tegra power domain tree has a single system level power domain i.e. a
36 * single root node. The first entry in the power domain descriptor specifies
37 * the number of power domains at the highest power level.
38 *******************************************************************************
39 */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080040static const uint8_t tegra_power_domain_tree_desc[] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070041 /* No of root nodes */
42 1,
43 /* No of clusters */
44 PLATFORM_CLUSTER_COUNT,
45 /* No of CPU cores - cluster0 */
46 PLATFORM_MAX_CPUS_PER_CLUSTER,
47 /* No of CPU cores - cluster1 */
Varun Wadekara07d1c72017-08-23 14:59:09 -070048 PLATFORM_MAX_CPUS_PER_CLUSTER,
49 /* No of CPU cores - cluster2 */
50 PLATFORM_MAX_CPUS_PER_CLUSTER,
51 /* No of CPU cores - cluster3 */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070052 PLATFORM_MAX_CPUS_PER_CLUSTER
53};
54
Varun Wadekara7265be2017-04-28 08:45:53 -070055/*******************************************************************************
56 * This function returns the Tegra default topology tree information.
57 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080058const uint8_t *plat_get_power_domain_tree_desc(void)
Varun Wadekara7265be2017-04-28 08:45:53 -070059{
60 return tegra_power_domain_tree_desc;
61}
62
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070063/*
64 * Table of regions to map using the MMU.
65 */
66static const mmap_region_t tegra_mmap[] = {
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080067 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
68 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
69 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
70 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
71 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
72 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
73 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
74 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070075#if !ENABLE_CONSOLE_SPE
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080076 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
77 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
78 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
79 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
80 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
81 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070082#endif
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080083 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
84 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
85 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
86 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
87 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
88 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
89 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
90 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
91 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070093#if ENABLE_CONSOLE_SPE
94 MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */
95 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
96#endif
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080097 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
98 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
99 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
100 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
101 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
102 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
103 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
105 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
107 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */
108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
109 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */
110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
111 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */
112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700113 {0}
114};
115
116/*******************************************************************************
117 * Set up the pagetables as per the platform memory map & initialize the MMU
118 ******************************************************************************/
119const mmap_region_t *plat_get_mmio_map(void)
120{
121 /* MMIO space */
122 return tegra_mmap;
123}
124
125/*******************************************************************************
126 * Handler to get the System Counter Frequency
127 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800128uint32_t plat_get_syscnt_freq2(void)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700129{
130 return 31250000;
131}
132
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700133#if !ENABLE_CONSOLE_SPE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700134/*******************************************************************************
135 * Maximum supported UART controllers
136 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800137#define TEGRA194_MAX_UART_PORTS 7
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700138
139/*******************************************************************************
140 * This variable holds the UART port base addresses
141 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800142static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700143 0, /* undefined - treated as an error case */
144 TEGRA_UARTA_BASE,
145 TEGRA_UARTB_BASE,
146 TEGRA_UARTC_BASE,
147 TEGRA_UARTD_BASE,
148 TEGRA_UARTE_BASE,
149 TEGRA_UARTF_BASE,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800150 TEGRA_UARTG_BASE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700151};
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700152#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700153
154/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700155 * Enable console corresponding to the console ID
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700156 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700157void plat_enable_console(int32_t id)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700158{
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700159 uint32_t console_clock = 0U;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700160
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700161#if ENABLE_CONSOLE_SPE
162 static console_spe_t spe_console;
163
164 if (id == TEGRA_CONSOLE_SPE_ID) {
165 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
166 console_clock,
167 TEGRA_CONSOLE_BAUDRATE,
168 &spe_console);
169 console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT |
170 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800171 }
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700172#else
173 static console_16550_t uart_console;
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800174
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700175 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
176 /*
177 * Reference clock used by the FPGAs is a lot slower.
178 */
179 if (tegra_platform_is_fpga()) {
180 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
181 } else {
182 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
183 }
184
185 (void)console_16550_register(tegra194_uart_addresses[id],
186 console_clock,
187 TEGRA_CONSOLE_BAUDRATE,
188 &uart_console);
189 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
190 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
191 }
192#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700193}
194
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700195/*******************************************************************************
196 * Handler for early platform setup
197 ******************************************************************************/
198void plat_early_platform_setup(void)
199{
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700200 /* sanity check MCE firmware compatibility */
201 mce_verify_firmware_version();
202
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800203 /*
204 * Program XUSB STREAMIDs
205 * ======================
206 * T19x XUSB has support for XUSB virtualization. It will have one
Ajay Gupta81621092017-08-01 15:53:04 -0700207 * physical function (PF) and four Virtual function (VF)
208 *
209 * There were below two SIDs for XUSB until T186.
210 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU
211 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU
212 *
213 * We have below four new SIDs added for VF(s)
214 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU
215 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU
216 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU
217 * 6) #define TEGRA_SID_XUSB_VF3 0x60U
218 *
219 * When virtualization is enabled then we have to disable SID override
220 * and program above SIDs in below newly added SID registers in XUSB
221 * PADCTL MMIO space. These registers are TZ protected and so need to
222 * be done in ATF.
223 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
224 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
225 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
226 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
227 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
228 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
229 *
230 * This change disables SID override and programs XUSB SIDs in
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800231 * above registers to support both virtualization and
232 * non-virtualization platforms
Ajay Gupta81621092017-08-01 15:53:04 -0700233 */
234 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
235 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
236 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
237 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
238 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
239 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
240 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
241 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
242 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
243 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
244 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
245 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700246}
247
Varun Wadekar362a6b22017-11-10 11:04:42 -0800248/* Secure IRQs for Tegra194 */
249static const interrupt_prop_t tegra194_interrupt_props[] = {
250 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
251 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
252 INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
253 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700254};
255
256/*******************************************************************************
257 * Initialize the GIC and SGIs
258 ******************************************************************************/
259void plat_gic_setup(void)
260{
Varun Wadekar362a6b22017-11-10 11:04:42 -0800261 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
262 tegra_gic_init();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700263
264 /*
Varun Wadekar362a6b22017-11-10 11:04:42 -0800265 * Initialize the FIQ handler
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700266 */
Varun Wadekar362a6b22017-11-10 11:04:42 -0800267 tegra_fiq_handler_setup();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700268}
269
270/*******************************************************************************
271 * Return pointer to the BL31 params from previous bootloader
272 ******************************************************************************/
273struct tegra_bl31_params *plat_get_bl31_params(void)
274{
275 uint32_t val;
276
Steven Kao4607f172017-10-23 18:35:14 +0800277 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700278
279 return (struct tegra_bl31_params *)(uintptr_t)val;
280}
281
282/*******************************************************************************
283 * Return pointer to the BL31 platform params from previous bootloader
284 ******************************************************************************/
285plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
286{
287 uint32_t val;
288
Steven Kao4607f172017-10-23 18:35:14 +0800289 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700290
291 return (plat_params_from_bl2_t *)(uintptr_t)val;
292}
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800293
294void plat_late_platform_setup(void)
295{
Steven Kao8f4f1022017-12-13 06:39:15 +0800296#if ENABLE_STRICT_CHECKING_MODE
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800297 /*
298 * Enable strict checking after programming the GSC for
299 * enabling TZSRAM and TZDRAM
300 */
301 mce_enable_strict_checking();
Steven Kao8f4f1022017-12-13 06:39:15 +0800302#endif
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800303}