blob: a820a4421d64288aaf77276dfbd5277599766900 [file] [log] [blame]
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01001/*
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +01002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SMMU_V3_H
8#define SMMU_V3_H
Jeenu Viswambharan5c503042017-05-26 14:15:40 +01009
10#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010012
13/* SMMUv3 register offsets from device base */
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010014#define SMMU_GBPA U(0x0044)
Antonio Nino Diazfeacba32018-08-21 16:12:29 +010015#define SMMU_S_IDR1 U(0x8004)
16#define SMMU_S_INIT U(0x803c)
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010017#define SMMU_S_GBPA U(0x8044)
18
19/* SMMU_GBPA register fields */
20#define SMMU_GBPA_UPDATE (1UL << 31)
21#define SMMU_GBPA_ABORT (1UL << 20)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010022
23/* SMMU_S_IDR1 register fields */
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010024#define SMMU_S_IDR1_SECURE_IMPL (1UL << 31)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010025
26/* SMMU_S_INIT register fields */
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010027#define SMMU_S_INIT_INV_ALL (1UL << 0)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010028
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010029/* SMMU_S_GBPA register fields */
30#define SMMU_S_GBPA_UPDATE (1UL << 31)
31#define SMMU_S_GBPA_ABORT (1UL << 20)
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010032
33int smmuv3_init(uintptr_t smmu_base);
Alexei Fedorov896799a2019-05-09 12:14:40 +010034int smmuv3_security_init(uintptr_t smmu_base);
Jeenu Viswambharan5c503042017-05-26 14:15:40 +010035
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000036#endif /* SMMU_V3_H */