| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef SMMU_V3_H |
| 8 | #define SMMU_V3_H |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 9 | |
| 10 | #include <stdint.h> |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame^] | 11 | |
| 12 | #include <lib/utils_def.h> |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 13 | |
| 14 | /* SMMUv3 register offsets from device base */ |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 15 | #define SMMU_S_IDR1 U(0x8004) |
| 16 | #define SMMU_S_INIT U(0x803c) |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 17 | |
| 18 | /* SMMU_S_IDR1 register fields */ |
| 19 | #define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31 |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 20 | #define SMMU_S_IDR1_SECURE_IMPL_MASK U(0x1) |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 21 | |
| 22 | /* SMMU_S_INIT register fields */ |
| Antonio Nino Diaz | feacba3 | 2018-08-21 16:12:29 +0100 | [diff] [blame] | 23 | #define SMMU_S_INIT_INV_ALL_MASK U(0x1) |
| Jeenu Viswambharan | 5c50304 | 2017-05-26 14:15:40 +0100 | [diff] [blame] | 24 | |
| 25 | |
| 26 | int smmuv3_init(uintptr_t smmu_base); |
| 27 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 28 | #endif /* SMMU_V3_H */ |