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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +02002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Lionel Debieve7bd96f42019-09-03 12:22:23 +020022#include <stm32mp_auth.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010023#include <stm32mp_common.h>
24#include <stm32mp_dt.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010025#include <stm32mp_shres_helpers.h>
Yann Gautierc7374052019-06-04 18:02:37 +020026#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010027#include <stm32mp1_private.h>
Etienne Carriere316d6342019-12-02 10:08:48 +010028#include <stm32mp1_shared_resources.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010029#endif
30
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020031#if !STM32MP_USE_STM32IMAGE
32#include "stm32mp1_fip_def.h"
33#else /* STM32MP_USE_STM32IMAGE */
34#include "stm32mp1_stm32image_def.h"
35#endif /* STM32MP_USE_STM32IMAGE */
36
Yann Gautier4b0c72a2018-07-16 10:54:09 +020037/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020038 * CHIP ID
39 ******************************************************************************/
Yann Gautiera0a6ff62021-05-10 16:05:18 +020040#define STM32MP1_CHIP_ID U(0x500)
41
Yann Gautierc7374052019-06-04 18:02:37 +020042#define STM32MP157C_PART_NB U(0x05000000)
43#define STM32MP157A_PART_NB U(0x05000001)
44#define STM32MP153C_PART_NB U(0x05000024)
45#define STM32MP153A_PART_NB U(0x05000025)
46#define STM32MP151C_PART_NB U(0x0500002E)
47#define STM32MP151A_PART_NB U(0x0500002F)
Lionel Debieve7b64e3e2019-05-17 16:01:18 +020048#define STM32MP157F_PART_NB U(0x05000080)
49#define STM32MP157D_PART_NB U(0x05000081)
50#define STM32MP153F_PART_NB U(0x050000A4)
51#define STM32MP153D_PART_NB U(0x050000A5)
52#define STM32MP151F_PART_NB U(0x050000AE)
53#define STM32MP151D_PART_NB U(0x050000AF)
Yann Gautierc7374052019-06-04 18:02:37 +020054
55#define STM32MP1_REV_B U(0x2000)
Lionel Debieve2d64b532019-06-25 10:40:37 +020056#define STM32MP1_REV_Z U(0x2001)
Yann Gautierc7374052019-06-04 18:02:37 +020057
58/*******************************************************************************
59 * PACKAGE ID
60 ******************************************************************************/
61#define PKG_AA_LFBGA448 U(4)
62#define PKG_AB_LFBGA354 U(3)
63#define PKG_AC_TFBGA361 U(2)
64#define PKG_AD_TFBGA257 U(1)
65
66/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020067 * STM32MP1 memory map related constants
68 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020069#define STM32MP_ROM_BASE U(0x00000000)
70#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier3c93a252021-09-15 15:12:57 +020071#define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020072
Yann Gautiera2e2a302019-02-14 11:13:39 +010073#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
74#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020075
Etienne Carriere72369b12019-12-08 08:17:56 +010076#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
77#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
78 STM32MP_SYSRAM_SIZE - \
79 STM32MP_NS_SYSRAM_SIZE)
80
Etienne Carriere34f0e932020-07-16 17:36:18 +020081#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
82#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
83
Etienne Carriere72369b12019-12-08 08:17:56 +010084#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
85#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
86 STM32MP_NS_SYSRAM_SIZE)
87
Yann Gautier4b0c72a2018-07-16 10:54:09 +020088/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +010089#define STM32MP_DDR_BASE U(0xC0000000)
90#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020091
92/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -070093#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +020094enum ddr_type {
95 STM32MP_DDR3,
96 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +020097 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +020098};
99#endif
100
101/* Section used inside TF binaries */
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200102#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200103/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100104#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautiera1ee9ed2020-09-17 11:30:18 +0200105/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
106#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200107
Etienne Carriere72369b12019-12-08 08:17:56 +0100108#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100109 STM32MP_PARAM_LOAD_SIZE + \
110 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200111
Etienne Carriere72369b12019-12-08 08:17:56 +0100112#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100113 (STM32MP_PARAM_LOAD_SIZE + \
114 STM32MP_HEADER_SIZE))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200115
Yann Gautierebc765f2020-01-16 18:50:51 +0100116/* BL2 and BL32/sp_min require finer granularity tables */
117#if defined(IMAGE_BL2)
118#define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
119#endif
120
121#if defined(IMAGE_BL32)
122#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
123#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200124
125/*
126 * MAX_MMAP_REGIONS is usually:
127 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
128 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200129#if defined(IMAGE_BL2)
Yann Gautierebc765f2020-01-16 18:50:51 +0100130 #if STM32MP_USB_PROGRAMMER
131 #define MAX_MMAP_REGIONS 8
132 #else
133 #define MAX_MMAP_REGIONS 7
134 #endif
Yann Gautier9d135e42018-07-16 19:36:06 +0200135#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200136
Yann Gautiera2e2a302019-02-14 11:13:39 +0100137#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200138#define STM32MP_BL33_MAX_SIZE U(0x400000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200139
Lionel Debieve402a46b2019-11-04 12:28:15 +0100140/* Define maximum page size for NAND devices */
141#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
142
143/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200144 * STM32MP1 device/io map related constants (used for MMU)
145 ******************************************************************************/
146#define STM32MP1_DEVICE1_BASE U(0x40000000)
147#define STM32MP1_DEVICE1_SIZE U(0x40000000)
148
149#define STM32MP1_DEVICE2_BASE U(0x80000000)
150#define STM32MP1_DEVICE2_SIZE U(0x40000000)
151
152/*******************************************************************************
153 * STM32MP1 RCC
154 ******************************************************************************/
155#define RCC_BASE U(0x50000000)
156
157/*******************************************************************************
158 * STM32MP1 PWR
159 ******************************************************************************/
160#define PWR_BASE U(0x50001000)
161
162/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100163 * STM32MP1 GPIO
164 ******************************************************************************/
165#define GPIOA_BASE U(0x50002000)
166#define GPIOB_BASE U(0x50003000)
167#define GPIOC_BASE U(0x50004000)
168#define GPIOD_BASE U(0x50005000)
169#define GPIOE_BASE U(0x50006000)
170#define GPIOF_BASE U(0x50007000)
171#define GPIOG_BASE U(0x50008000)
172#define GPIOH_BASE U(0x50009000)
173#define GPIOI_BASE U(0x5000A000)
174#define GPIOJ_BASE U(0x5000B000)
175#define GPIOK_BASE U(0x5000C000)
176#define GPIOZ_BASE U(0x54004000)
177#define GPIO_BANK_OFFSET U(0x1000)
178
179/* Bank IDs used in GPIO driver API */
180#define GPIO_BANK_A U(0)
181#define GPIO_BANK_B U(1)
182#define GPIO_BANK_C U(2)
183#define GPIO_BANK_D U(3)
184#define GPIO_BANK_E U(4)
185#define GPIO_BANK_F U(5)
186#define GPIO_BANK_G U(6)
187#define GPIO_BANK_H U(7)
188#define GPIO_BANK_I U(8)
189#define GPIO_BANK_J U(9)
190#define GPIO_BANK_K U(10)
191#define GPIO_BANK_Z U(25)
192
193#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
194
195/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200196 * STM32MP1 UART
197 ******************************************************************************/
198#define USART1_BASE U(0x5C000000)
199#define USART2_BASE U(0x4000E000)
200#define USART3_BASE U(0x4000F000)
201#define UART4_BASE U(0x40010000)
202#define UART5_BASE U(0x40011000)
203#define USART6_BASE U(0x44003000)
204#define UART7_BASE U(0x40018000)
205#define UART8_BASE U(0x40019000)
Yann Gautiera2e2a302019-02-14 11:13:39 +0100206#define STM32MP_UART_BAUDRATE U(115200)
Yann Gautier038bff22019-01-17 19:17:47 +0100207
208/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100209#define STM32MP_DEBUG_USART_BASE UART4_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100210/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100211#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100212#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
213#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
214#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
215#define DEBUG_UART_TX_GPIO_PORT 11
216#define DEBUG_UART_TX_GPIO_ALTERNATE 6
217#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
218#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
219#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
220#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier5c84e742020-09-14 17:21:59 +0200221#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
222#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200223
224/*******************************************************************************
Etienne Carrieree96162e2020-04-10 11:32:54 +0200225 * STM32MP1 ETZPC
226 ******************************************************************************/
227#define STM32MP1_ETZPC_BASE U(0x5C007000)
228
229/* ETZPC TZMA IDs */
230#define STM32MP1_ETZPC_TZMA_ROM U(0)
231#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
232
233#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
234
235/* ETZPC DECPROT IDs */
236#define STM32MP1_ETZPC_STGENC_ID 0
237#define STM32MP1_ETZPC_BKPSRAM_ID 1
238#define STM32MP1_ETZPC_IWDG1_ID 2
239#define STM32MP1_ETZPC_USART1_ID 3
240#define STM32MP1_ETZPC_SPI6_ID 4
241#define STM32MP1_ETZPC_I2C4_ID 5
242#define STM32MP1_ETZPC_RNG1_ID 7
243#define STM32MP1_ETZPC_HASH1_ID 8
244#define STM32MP1_ETZPC_CRYP1_ID 9
245#define STM32MP1_ETZPC_DDRCTRL_ID 10
246#define STM32MP1_ETZPC_DDRPHYC_ID 11
247#define STM32MP1_ETZPC_I2C6_ID 12
248#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
249
250#define STM32MP1_ETZPC_TIM2_ID 16
251#define STM32MP1_ETZPC_TIM3_ID 17
252#define STM32MP1_ETZPC_TIM4_ID 18
253#define STM32MP1_ETZPC_TIM5_ID 19
254#define STM32MP1_ETZPC_TIM6_ID 20
255#define STM32MP1_ETZPC_TIM7_ID 21
256#define STM32MP1_ETZPC_TIM12_ID 22
257#define STM32MP1_ETZPC_TIM13_ID 23
258#define STM32MP1_ETZPC_TIM14_ID 24
259#define STM32MP1_ETZPC_LPTIM1_ID 25
260#define STM32MP1_ETZPC_WWDG1_ID 26
261#define STM32MP1_ETZPC_SPI2_ID 27
262#define STM32MP1_ETZPC_SPI3_ID 28
263#define STM32MP1_ETZPC_SPDIFRX_ID 29
264#define STM32MP1_ETZPC_USART2_ID 30
265#define STM32MP1_ETZPC_USART3_ID 31
266#define STM32MP1_ETZPC_UART4_ID 32
267#define STM32MP1_ETZPC_UART5_ID 33
268#define STM32MP1_ETZPC_I2C1_ID 34
269#define STM32MP1_ETZPC_I2C2_ID 35
270#define STM32MP1_ETZPC_I2C3_ID 36
271#define STM32MP1_ETZPC_I2C5_ID 37
272#define STM32MP1_ETZPC_CEC_ID 38
273#define STM32MP1_ETZPC_DAC_ID 39
274#define STM32MP1_ETZPC_UART7_ID 40
275#define STM32MP1_ETZPC_UART8_ID 41
276#define STM32MP1_ETZPC_MDIOS_ID 44
277#define STM32MP1_ETZPC_TIM1_ID 48
278#define STM32MP1_ETZPC_TIM8_ID 49
279#define STM32MP1_ETZPC_USART6_ID 51
280#define STM32MP1_ETZPC_SPI1_ID 52
281#define STM32MP1_ETZPC_SPI4_ID 53
282#define STM32MP1_ETZPC_TIM15_ID 54
283#define STM32MP1_ETZPC_TIM16_ID 55
284#define STM32MP1_ETZPC_TIM17_ID 56
285#define STM32MP1_ETZPC_SPI5_ID 57
286#define STM32MP1_ETZPC_SAI1_ID 58
287#define STM32MP1_ETZPC_SAI2_ID 59
288#define STM32MP1_ETZPC_SAI3_ID 60
289#define STM32MP1_ETZPC_DFSDM_ID 61
290#define STM32MP1_ETZPC_TT_FDCAN_ID 62
291#define STM32MP1_ETZPC_LPTIM2_ID 64
292#define STM32MP1_ETZPC_LPTIM3_ID 65
293#define STM32MP1_ETZPC_LPTIM4_ID 66
294#define STM32MP1_ETZPC_LPTIM5_ID 67
295#define STM32MP1_ETZPC_SAI4_ID 68
296#define STM32MP1_ETZPC_VREFBUF_ID 69
297#define STM32MP1_ETZPC_DCMI_ID 70
298#define STM32MP1_ETZPC_CRC2_ID 71
299#define STM32MP1_ETZPC_ADC_ID 72
300#define STM32MP1_ETZPC_HASH2_ID 73
301#define STM32MP1_ETZPC_RNG2_ID 74
302#define STM32MP1_ETZPC_CRYP2_ID 75
303#define STM32MP1_ETZPC_SRAM1_ID 80
304#define STM32MP1_ETZPC_SRAM2_ID 81
305#define STM32MP1_ETZPC_SRAM3_ID 82
306#define STM32MP1_ETZPC_SRAM4_ID 83
307#define STM32MP1_ETZPC_RETRAM_ID 84
308#define STM32MP1_ETZPC_OTG_ID 85
309#define STM32MP1_ETZPC_SDMMC3_ID 86
310#define STM32MP1_ETZPC_DLYBSD3_ID 87
311#define STM32MP1_ETZPC_DMA1_ID 88
312#define STM32MP1_ETZPC_DMA2_ID 89
313#define STM32MP1_ETZPC_DMAMUX_ID 90
314#define STM32MP1_ETZPC_FMC_ID 91
315#define STM32MP1_ETZPC_QSPI_ID 92
316#define STM32MP1_ETZPC_DLYBQ_ID 93
317#define STM32MP1_ETZPC_ETH_ID 94
318#define STM32MP1_ETZPC_RSV_ID 95
319
320#define STM32MP_ETZPC_MAX_ID 96
321
322/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200323 * STM32MP1 TZC (TZ400)
324 ******************************************************************************/
325#define STM32MP1_TZC_BASE U(0x5C006000)
326
Yann Gautier2f974232020-09-17 12:25:05 +0200327#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
328 TZC_400_REGION_ATTR_FILTER_BIT(1))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200329
330/*******************************************************************************
331 * STM32MP1 SDMMC
332 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100333#define STM32MP_SDMMC1_BASE U(0x58005000)
334#define STM32MP_SDMMC2_BASE U(0x58007000)
335#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200336
Yann Gautier4baf5822019-05-09 13:25:52 +0200337#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
338#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
339#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
340#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
341#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200342
343/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100344 * STM32MP1 BSEC / OTP
345 ******************************************************************************/
346#define STM32MP1_OTP_MAX_ID 0x5FU
347#define STM32MP1_UPPER_OTP_START 0x20U
348
349#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
350
351/* OTP offsets */
352#define DATA0_OTP U(0)
Yann Gautierc7374052019-06-04 18:02:37 +0200353#define PART_NUMBER_OTP U(1)
Lionel Debieve402a46b2019-11-04 12:28:15 +0100354#define NAND_OTP U(9)
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200355#define UID0_OTP U(13)
356#define UID1_OTP U(14)
357#define UID2_OTP U(15)
Yann Gautierc7374052019-06-04 18:02:37 +0200358#define PACKAGE_OTP U(16)
Yann Gautier3edc7c32019-05-20 19:17:08 +0200359#define HW2_OTP U(18)
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100360
361/* OTP mask */
362/* DATA0 */
363#define DATA0_OTP_SECURED BIT(6)
364
Yann Gautierc7374052019-06-04 18:02:37 +0200365/* PART NUMBER */
366#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
367#define PART_NUMBER_OTP_PART_SHIFT 0
368
369/* PACKAGE */
370#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
371#define PACKAGE_OTP_PKG_SHIFT 27
372
Yann Gautier091eab52019-06-04 18:06:34 +0200373/* IWDG OTP */
374#define HW2_OTP_IWDG_HW_POS U(3)
375#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
376#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
377
Yann Gautier3edc7c32019-05-20 19:17:08 +0200378/* HW2 OTP */
379#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
380
Lionel Debieve402a46b2019-11-04 12:28:15 +0100381/* NAND OTP */
382/* NAND parameter storage flag */
383#define NAND_PARAM_STORED_IN_OTP BIT(31)
384
385/* NAND page size in bytes */
386#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
387#define NAND_PAGE_SIZE_SHIFT 29
388#define NAND_PAGE_SIZE_2K U(0)
389#define NAND_PAGE_SIZE_4K U(1)
390#define NAND_PAGE_SIZE_8K U(2)
391
392/* NAND block size in pages */
393#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
394#define NAND_BLOCK_SIZE_SHIFT 27
395#define NAND_BLOCK_SIZE_64_PAGES U(0)
396#define NAND_BLOCK_SIZE_128_PAGES U(1)
397#define NAND_BLOCK_SIZE_256_PAGES U(2)
398
399/* NAND number of block (in unit of 256 blocs) */
400#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
401#define NAND_BLOCK_NB_SHIFT 19
402#define NAND_BLOCK_NB_UNIT U(256)
403
404/* NAND bus width in bits */
405#define NAND_WIDTH_MASK BIT(18)
406#define NAND_WIDTH_SHIFT 18
407
408/* NAND number of ECC bits per 512 bytes */
409#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
410#define NAND_ECC_BIT_NB_SHIFT 15
411#define NAND_ECC_BIT_NB_UNSET U(0)
412#define NAND_ECC_BIT_NB_1_BITS U(1)
413#define NAND_ECC_BIT_NB_4_BITS U(2)
414#define NAND_ECC_BIT_NB_8_BITS U(3)
415#define NAND_ECC_ON_DIE U(4)
416
Lionel Debieve186b0462019-09-24 18:30:12 +0200417/* NAND number of planes */
418#define NAND_PLANE_BIT_NB_MASK BIT(14)
419
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200420/* UID OTP */
421#define UID_WORD_NB U(3)
422
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100423/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200424 * STM32MP1 TAMP
425 ******************************************************************************/
426#define TAMP_BASE U(0x5C00A000)
427#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
428
Julius Werner53456fc2019-07-09 13:49:11 -0700429#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Yann Gautier41934662018-07-20 11:36:05 +0200430static inline uint32_t tamp_bkpr(uint32_t idx)
431{
432 return TAMP_BKP_REGISTER_BASE + (idx << 2);
433}
434#endif
435
436/*******************************************************************************
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200437 * STM32MP1 USB
438 ******************************************************************************/
439#define USB_OTG_BASE U(0x49000000)
440
441/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200442 * STM32MP1 DDRCTRL
443 ******************************************************************************/
444#define DDRCTRL_BASE U(0x5A003000)
445
446/*******************************************************************************
447 * STM32MP1 DDRPHYC
448 ******************************************************************************/
449#define DDRPHYC_BASE U(0x5A004000)
450
451/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200452 * STM32MP1 IWDG
453 ******************************************************************************/
454#define IWDG_MAX_INSTANCE U(2)
455#define IWDG1_INST U(0)
456#define IWDG2_INST U(1)
457
458#define IWDG1_BASE U(0x5C003000)
459#define IWDG2_BASE U(0x5A002000)
460
461/*******************************************************************************
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200462 * Miscellaneous STM32MP1 peripherals base address
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200463 ******************************************************************************/
Yann Gautiera18f61b2020-05-05 17:58:40 +0200464#define BSEC_BASE U(0x5C005000)
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200465#define CRYP1_BASE U(0x54001000)
Yann Gautier091eab52019-06-04 18:06:34 +0200466#define DBGMCU_BASE U(0x50081000)
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200467#define HASH1_BASE U(0x54002000)
468#define I2C4_BASE U(0x5C002000)
469#define I2C6_BASE U(0x5c009000)
470#define RNG1_BASE U(0x54003000)
471#define RTC_BASE U(0x5c004000)
472#define SPI6_BASE U(0x5c001000)
Yann Gautiera18f61b2020-05-05 17:58:40 +0200473#define STGEN_BASE U(0x5c008000)
474#define SYSCFG_BASE U(0x50020000)
Yann Gautier091eab52019-06-04 18:06:34 +0200475
476/*******************************************************************************
Yann Gautierb1279e72021-12-15 13:16:15 +0100477 * REGULATORS
478 ******************************************************************************/
479/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
480#define PLAT_NB_RDEVS U(19)
Pascal Pailletfc7b8052021-01-29 14:48:49 +0100481/* 1 FIXED */
482#define PLAT_NB_FIXED_REGS U(1)
Yann Gautierb1279e72021-12-15 13:16:15 +0100483
484/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100485 * Device Tree defines
486 ******************************************************************************/
Yann Gautier35dc0772019-05-13 18:34:48 +0200487#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +0200488#define DT_DDR_COMPAT "st,stm32mp1-ddr"
Yann Gautier091eab52019-06-04 18:06:34 +0200489#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Yann Gautier4ede20a2020-09-18 15:04:14 +0200490#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
Yann Gautier4d429472019-02-14 11:15:20 +0100491#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
492
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200493#endif /* STM32MP1_DEF_H */