blob: bd62614549640c47e098dbf1f4227676c573922d [file] [log] [blame]
Deepak Pandey9cbacf62018-08-08 10:32:51 +05301#
sah016ec01e82021-06-06 14:38:01 +05302# Copyright (c) 2018-2022, Arm Limited. All rights reserved.
Deepak Pandey9cbacf62018-08-08 10:32:51 +05303#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7
8N1SDP_BASE := plat/arm/board/n1sdp
9
10INTERCONNECT_SOURCES := ${N1SDP_BASE}/n1sdp_interconnect.c
11
12PLAT_INCLUDES := -I${N1SDP_BASE}/include
13
14
John Tsichritzis56369c12019-02-19 13:49:06 +000015N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
Deepak Pandey9cbacf62018-08-08 10:32:51 +053016
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000017# GIC-600 configuration
Andre Przywarae1cc1302020-03-25 15:50:38 +000018GICV3_SUPPORT_GIC600 := 1
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000019GICV3_IMPL_GIC600_MULTICHIP := 1
Deepak Pandey9cbacf62018-08-08 10:32:51 +053020
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000021# Include GICv3 driver files
22include drivers/arm/gic/v3/gicv3.mk
23
24N1SDP_GIC_SOURCES := ${GICV3_SOURCES} \
Deepak Pandey9cbacf62018-08-08 10:32:51 +053025 plat/common/plat_gicv3.c \
26 plat/arm/common/arm_gicv3.c \
Deepak Pandey9cbacf62018-08-08 10:32:51 +053027
28PLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \
29 ${N1SDP_BASE}/aarch64/n1sdp_helper.S
30
sah016ec01e82021-06-06 14:38:01 +053031BL1_SOURCES := ${N1SDP_CPU_SOURCES} \
32 ${INTERCONNECT_SOURCES} \
33 ${N1SDP_BASE}/n1sdp_err.c \
34 ${N1SDP_BASE}/n1sdp_trusted_boot.c \
35 ${N1SDP_BASE}/n1sdp_bl1_setup.c \
36 drivers/arm/sbsa/sbsa.c
37
38BL2_SOURCES := ${N1SDP_BASE}/n1sdp_security.c \
39 ${N1SDP_BASE}/n1sdp_err.c \
40 ${N1SDP_BASE}/n1sdp_trusted_boot.c \
41 lib/utils/mem_region.c \
42 ${N1SDP_BASE}/n1sdp_bl2_setup.c \
sahilf1c88612022-03-15 14:11:43 +053043 ${N1SDP_BASE}/n1sdp_image_load.c \
sah016ec01e82021-06-06 14:38:01 +053044 drivers/arm/css/sds/sds.c
Deepak Pandey9cbacf62018-08-08 10:32:51 +053045
46BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
47 ${INTERCONNECT_SOURCES} \
48 ${N1SDP_GIC_SOURCES} \
sah016ec01e82021-06-06 14:38:01 +053049 ${N1SDP_BASE}/n1sdp_bl31_setup.c \
Werner Lewisf32d2ad2023-02-21 14:40:12 +000050 ${N1SDP_BASE}/n1sdp_pm.c \
Deepak Pandey9cbacf62018-08-08 10:32:51 +053051 ${N1SDP_BASE}/n1sdp_topology.c \
Manoj Kumar69bebd82019-06-21 17:07:13 +010052 ${N1SDP_BASE}/n1sdp_security.c \
53 drivers/arm/css/sds/sds.c
Deepak Pandey9cbacf62018-08-08 10:32:51 +053054
Andre Przywarac2db6512020-07-06 11:19:41 +053055FDT_SOURCES += fdts/${PLAT}-single-chip.dts \
sah016ec01e82021-06-06 14:38:01 +053056 fdts/${PLAT}-multi-chip.dts \
sahilf1c88612022-03-15 14:11:43 +053057 ${N1SDP_BASE}/fdts/n1sdp_fw_config.dts \
58 ${N1SDP_BASE}/fdts/n1sdp_tb_fw_config.dts \
59 ${N1SDP_BASE}/fdts/n1sdp_nt_fw_config.dts
sah016ec01e82021-06-06 14:38:01 +053060
61FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_fw_config.dtb
62TB_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_tb_fw_config.dtb
sahilf1c88612022-03-15 14:11:43 +053063NT_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_nt_fw_config.dtb
sah016ec01e82021-06-06 14:38:01 +053064
65# Add the FW_CONFIG to FIP and specify the same to certtool
66$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
67# Add the TB_FW_CONFIG to FIP and specify the same to certtool
68$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
sahilf1c88612022-03-15 14:11:43 +053069# Add the NT_FW_CONFIG to FIP and specify the same to certtool
70$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
sah016ec01e82021-06-06 14:38:01 +053071
Vishnu Banavath7cac3de2022-06-20 18:20:21 +010072N1SDP_SPMC_MANIFEST_DTS := ${N1SDP_BASE}/fdts/${PLAT}_optee_spmc_manifest.dts
73FDT_SOURCES += ${N1SDP_SPMC_MANIFEST_DTS}
74N1SDP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_optee_spmc_manifest.dtb
75
76# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
77$(eval $(call TOOL_ADD_PAYLOAD,${N1SDP_TOS_FW_CONFIG},--tos-fw-config,${N1SDP_TOS_FW_CONFIG}))
78
sah016ec01e82021-06-06 14:38:01 +053079# Setting to 0 as no NVCTR in N1SDP
80N1SDP_FW_NVCTR_VAL := 0
81TFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL}
82NTFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL}
83
84# Add N1SDP_FW_NVCTR_VAL
85$(eval $(call add_define,N1SDP_FW_NVCTR_VAL))
Deepak Pandey9cbacf62018-08-08 10:32:51 +053086
87# TF-A not required to load the SCP Images
88override CSS_LOAD_SCP_IMAGES := 0
89
Deepak Pandey9cbacf62018-08-08 10:32:51 +053090override NEED_BL2U := no
91
Deepak Pandey9cbacf62018-08-08 10:32:51 +053092# 32 bit mode not supported
93override CTX_INCLUDE_AARCH32_REGS := 0
94
95override ARM_PLAT_MT := 1
96
97# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
98# SCP during power management operations and for SCP RAM Firmware transfer.
99CSS_USE_SCMI_SDS_DRIVER := 1
100
101# System coherency is managed in hardware
102HW_ASSISTED_COHERENCY := 1
103
104# When building for systems with hardware-assisted coherency, there's no need to
105# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
106USE_COHERENT_MEM := 0
Chandni Cherukurib9120872020-03-05 11:49:57 +0530107
108# Enable the flag since N1SDP has a system level cache
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100109NEOVERSE_Nx_EXTERNAL_LLC := 1
Deepak Pandey9cbacf62018-08-08 10:32:51 +0530110include plat/arm/common/arm_common.mk
111include plat/arm/css/common/css_common.mk
Deepak Pandey9cbacf62018-08-08 10:32:51 +0530112include plat/arm/board/common/board_common.mk