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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <assert.h>
32#include <arch_helpers.h>
33#include <platform.h>
34#include <bl2.h>
35#include <bl_common.h>
Vikram Kanigiri3ff77de2014-03-25 17:35:26 +000036#include <console.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010037
38/*******************************************************************************
39 * Declarations of linker defined symbols which will help us find the layout
40 * of trusted SRAM
41 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000042extern unsigned long __RO_START__;
43extern unsigned long __RO_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045extern unsigned long __COHERENT_RAM_START__;
46extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048/*
49 * The next 2 constants identify the extents of the code & RO data region.
50 * These addresses are used by the MMU setup code and therefore they must be
51 * page-aligned. It is the responsibility of the linker script to ensure that
52 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
53 */
54#define BL2_RO_BASE (unsigned long)(&__RO_START__)
55#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
56
57/*
58 * The next 2 constants identify the extents of the coherent memory region.
59 * These addresses are used by the MMU setup code and therefore they must be
60 * page-aligned. It is the responsibility of the linker script to ensure that
61 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
62 * page-aligned addresses.
63 */
64#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
65#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010066
67/* Pointer to memory visible to both BL2 and BL31 for passing data */
68extern unsigned char **bl2_el_change_mem_ptr;
69
70/* Data structure which holds the extents of the trusted SRAM for BL2 */
71static meminfo bl2_tzram_layout
72__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
Sandrine Bailleux204aa032013-10-28 15:14:00 +000073 section("tzfw_coherent_mem")));
Achin Guptae4d084e2014-02-19 17:18:23 +000074
75/*******************************************************************************
76 * Reference to structure which holds the arguments which need to be passed
77 * to BL31
78 ******************************************************************************/
79static bl31_args *bl2_to_bl31_args;
Achin Gupta4f6ad662013-10-25 09:08:21 +010080
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000081meminfo *bl2_plat_sec_mem_layout(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010082{
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000083 return &bl2_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010084}
85
Achin Guptae4d084e2014-02-19 17:18:23 +000086/*******************************************************************************
87 * This function returns a pointer to the memory that the platform has kept
88 * aside to pass all the information that BL31 could need.
89 ******************************************************************************/
90bl31_args *bl2_get_bl31_args_ptr(void)
Harry Liebel561cd332014-02-14 14:42:48 +000091{
Achin Guptae4d084e2014-02-19 17:18:23 +000092 return bl2_to_bl31_args;
Harry Liebel561cd332014-02-14 14:42:48 +000093}
94
Achin Gupta4f6ad662013-10-25 09:08:21 +010095/*******************************************************************************
96 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
97 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
98 * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
99 ******************************************************************************/
100void bl2_early_platform_setup(meminfo *mem_layout,
101 void *data)
102{
103 /* Setup the BL2 memory layout */
104 bl2_tzram_layout.total_base = mem_layout->total_base;
105 bl2_tzram_layout.total_size = mem_layout->total_size;
106 bl2_tzram_layout.free_base = mem_layout->free_base;
107 bl2_tzram_layout.free_size = mem_layout->free_size;
108 bl2_tzram_layout.attr = mem_layout->attr;
109 bl2_tzram_layout.next = 0;
110
111 /* Initialize the platform config for future decision making */
112 platform_config_setup();
113
Vikram Kanigiri3ff77de2014-03-25 17:35:26 +0000114 console_init(PL011_UART0_BASE);
115
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116 return;
117}
118
119/*******************************************************************************
Sandrine Bailleux942f4052013-11-19 17:14:22 +0000120 * Perform platform specific setup. For now just initialize the memory location
121 * to use for passing arguments to BL31.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122 ******************************************************************************/
123void bl2_platform_setup()
124{
Harry Liebelcef93392014-04-01 19:27:38 +0100125 /*
126 * Do initial security configuration to allow DRAM/device access. On
127 * Base FVP only DRAM security is programmable (via TrustZone), but
128 * other platforms might have more programmable security devices
129 * present.
130 */
131 plat_security_setup();
132
James Morrissey9d72b4e2014-02-10 17:04:32 +0000133 /* Initialise the IO layer and register platform IO devices */
134 io_setup();
135
Achin Guptaa3050ed2014-02-19 17:52:35 +0000136 /*
137 * Ensure that the secure DRAM memory used for passing BL31 arguments
138 * does not overlap with the BL32_BASE.
139 */
140 assert (BL32_BASE > TZDRAM_BASE + sizeof(bl31_args));
141
Achin Gupta4f6ad662013-10-25 09:08:21 +0100142 /* Use the Trusted DRAM for passing args to BL31 */
Achin Guptae4d084e2014-02-19 17:18:23 +0000143 bl2_to_bl31_args = (bl31_args *) TZDRAM_BASE;
144
145 /* Populate the extents of memory available for loading BL33 */
146 bl2_to_bl31_args->bl33_meminfo.total_base = DRAM_BASE;
147 bl2_to_bl31_args->bl33_meminfo.total_size = DRAM_SIZE;
148 bl2_to_bl31_args->bl33_meminfo.free_base = DRAM_BASE;
149 bl2_to_bl31_args->bl33_meminfo.free_size = DRAM_SIZE;
150 bl2_to_bl31_args->bl33_meminfo.attr = 0;
151 bl2_to_bl31_args->bl33_meminfo.next = 0;
Achin Guptaa3050ed2014-02-19 17:52:35 +0000152
153 /*
154 * Populate the extents of memory available for loading BL32.
155 * TODO: We are temporarily executing BL2 from TZDRAM; will eventually
156 * move to Trusted SRAM
157 */
158 bl2_to_bl31_args->bl32_meminfo.total_base = BL32_BASE;
159 bl2_to_bl31_args->bl32_meminfo.free_base = BL32_BASE;
160
161 bl2_to_bl31_args->bl32_meminfo.total_size =
162 (TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
163 bl2_to_bl31_args->bl32_meminfo.free_size =
164 (TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
165
166 bl2_to_bl31_args->bl32_meminfo.attr = BOT_LOAD;
167 bl2_to_bl31_args->bl32_meminfo.next = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168}
169
170/*******************************************************************************
171 * Perform the very early platform specific architectural setup here. At the
172 * moment this is only intializes the mmu in a quick and dirty way.
173 ******************************************************************************/
174void bl2_plat_arch_setup()
175{
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176 configure_mmu(&bl2_tzram_layout,
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000177 BL2_RO_BASE,
178 BL2_RO_LIMIT,
179 BL2_COHERENT_RAM_BASE,
180 BL2_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181}