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git01.mediatek.com / filogic / atf / f3c8f3289d3d5c3eea01ea1c930ad1f8d16466fb / . / common / aarch64 / early_exceptions.S
blob: 41bff97f37e19e44d4e966b7093d0fdaacd32add [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Dan Handleye83b0ca2014-01-14 18:17:09 +0000[diff] [blame]2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]33#include <platform.h>
34#include <runtime_svc.h>
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]35#include <asm_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]36
37 .globl early_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]38
Achin Guptab739f222014-01-18 16:50:09 +0000[diff] [blame]39 .section .vectors, "ax"; .align 11
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]40
41 /* -----------------------------------------------------
Sandrine Bailleux4d052752014-03-24 10:24:08 +0000[diff] [blame]42 * Very simple stackless exception handlers used by BL2
43 * and BL3-1 bootloader stages. BL3-1 uses them before
44 * stacks are setup. BL2 uses them throughout.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]45 * -----------------------------------------------------
46 */
47 .align 7
48early_exceptions:
49 /* -----------------------------------------------------
50 * Current EL with SP0 : 0x0 - 0x180
51 * -----------------------------------------------------
52 */
53SynchronousExceptionSP0:
54 mov x0, #SYNC_EXCEPTION_SP_EL0
55 bl plat_report_exception
56 b SynchronousExceptionSP0
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]57 check_vector_size SynchronousExceptionSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]58
59 .align 7
60IrqSP0:
61 mov x0, #IRQ_SP_EL0
62 bl plat_report_exception
63 b IrqSP0
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]64 check_vector_size IrqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]65
66 .align 7
67FiqSP0:
68 mov x0, #FIQ_SP_EL0
69 bl plat_report_exception
70 b FiqSP0
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]71 check_vector_size FiqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]72
73 .align 7
74SErrorSP0:
75 mov x0, #SERROR_SP_EL0
76 bl plat_report_exception
77 b SErrorSP0
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]78 check_vector_size SErrorSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]79
80 /* -----------------------------------------------------
81 * Current EL with SPx: 0x200 - 0x380
82 * -----------------------------------------------------
83 */
84 .align 7
85SynchronousExceptionSPx:
86 mov x0, #SYNC_EXCEPTION_SP_ELX
87 bl plat_report_exception
88 b SynchronousExceptionSPx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]89 check_vector_size SynchronousExceptionSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]90
91 .align 7
92IrqSPx:
93 mov x0, #IRQ_SP_ELX
94 bl plat_report_exception
95 b IrqSPx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]96 check_vector_size IrqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]97
98 .align 7
99FiqSPx:
100 mov x0, #FIQ_SP_ELX
101 bl plat_report_exception
102 b FiqSPx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]103 check_vector_size FiqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]104
105 .align 7
106SErrorSPx:
107 mov x0, #SERROR_SP_ELX
108 bl plat_report_exception
109 b SErrorSPx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]110 check_vector_size SErrorSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]111
112 /* -----------------------------------------------------
113 * Lower EL using AArch64 : 0x400 - 0x580
114 * -----------------------------------------------------
115 */
116 .align 7
117SynchronousExceptionA64:
Sandrine Bailleux4d052752014-03-24 10:24:08 +0000[diff] [blame]118 mov x0, #SYNC_EXCEPTION_AARCH64
119 bl plat_report_exception
120 b SynchronousExceptionA64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]121 check_vector_size SynchronousExceptionA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000[diff] [blame]122
123 .align 7
124IrqA64:
125 mov x0, #IRQ_AARCH64
126 bl plat_report_exception
127 b IrqA64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]128 check_vector_size IrqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000[diff] [blame]129
130 .align 7
131FiqA64:
132 mov x0, #FIQ_AARCH64
133 bl plat_report_exception
134 b FiqA64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]135 check_vector_size FiqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000[diff] [blame]136
137 .align 7
138SErrorA64:
139 mov x0, #SERROR_AARCH64
140 bl plat_report_exception
141 b SErrorA64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]142 check_vector_size SErrorA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000[diff] [blame]143
144 /* -----------------------------------------------------
145 * Lower EL using AArch32 : 0x0 - 0x180
146 * -----------------------------------------------------
147 */
148 .align 7
149SynchronousExceptionA32:
150 mov x0, #SYNC_EXCEPTION_AARCH32
151 bl plat_report_exception
152 b SynchronousExceptionA32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]153 check_vector_size SynchronousExceptionA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000[diff] [blame]154
155 .align 7
156IrqA32:
157 mov x0, #IRQ_AARCH32
158 bl plat_report_exception
159 b IrqA32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]160 check_vector_size IrqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000[diff] [blame]161
162 .align 7
163FiqA32:
164 mov x0, #FIQ_AARCH32
165 bl plat_report_exception
166 b FiqA32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]167 check_vector_size FiqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000[diff] [blame]168
169 .align 7
170SErrorA32:
171 mov x0, #SERROR_AARCH32
172 bl plat_report_exception
173 b SErrorA32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000[diff] [blame]174 check_vector_size SErrorA32